WO1998013763A3 - Multiport cache memory with address conflict detection - Google Patents

Multiport cache memory with address conflict detection Download PDF

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Publication number
WO1998013763A3
WO1998013763A3 PCT/IB1997/001146 IB9701146W WO9813763A3 WO 1998013763 A3 WO1998013763 A3 WO 1998013763A3 IB 9701146 W IB9701146 W IB 9701146W WO 9813763 A3 WO9813763 A3 WO 9813763A3
Authority
WO
WIPO (PCT)
Prior art keywords
port
bank
banks
access
microprocessor
Prior art date
Application number
PCT/IB1997/001146
Other languages
French (fr)
Other versions
WO1998013763A2 (en
Inventor
Eino Jacobs
Original Assignee
Philips Electronics Nv
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics Nv, Philips Norden Ab filed Critical Philips Electronics Nv
Priority to KR1019980703828A priority Critical patent/KR19990071554A/en
Priority to EP97940270A priority patent/EP0875030A2/en
Priority to JP10515453A priority patent/JP2000501539A/en
Publication of WO1998013763A2 publication Critical patent/WO1998013763A2/en
Publication of WO1998013763A3 publication Critical patent/WO1998013763A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A multi-port cache memory is disclosed. The multi-port cache operates in a microprocessor system, and includes multiple memory banks and multiple ports for enabling accesses to the banks. Conflict detection circuitry detects simultaneous addressing of a first memory bank through a first port and a second port, and stalls microprocessor operations for a predetermined number of clock cycles in response to the detection of simultaneous addressing. Conflict resolution circuitry allows access to the first bank through the first port during the stall, and allows access through the second port after the stall is complete. Generally, the conflict resolution circuitry allows access through ports that are attempting to access the first memory bank in order of ascending priority during successive clock cycles while the microprocessor is stalled. One or more of the ports attempting to access the first bank may be allowed access before or after the time the microprocessor is stalled. Each bank is single-ported. The banks have non overlapping address spaces, and are addressed so that words within a cache block are distributed among multiple banks.
PCT/IB1997/001146 1996-09-25 1997-09-23 Multiport cache memory with address conflict detection WO1998013763A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019980703828A KR19990071554A (en) 1996-09-25 1997-09-23 Multi-port cache memory with address conflict detection
EP97940270A EP0875030A2 (en) 1996-09-25 1997-09-23 Multi-port cache memory with address conflict detection
JP10515453A JP2000501539A (en) 1996-09-25 1997-09-23 Multi-port cache memory with address conflict detection

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71960996A 1996-09-25 1996-09-25
US08/719,609 1996-09-25

Publications (2)

Publication Number Publication Date
WO1998013763A2 WO1998013763A2 (en) 1998-04-02
WO1998013763A3 true WO1998013763A3 (en) 1998-06-04

Family

ID=24890679

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1997/001146 WO1998013763A2 (en) 1996-09-25 1997-09-23 Multiport cache memory with address conflict detection

Country Status (4)

Country Link
EP (1) EP0875030A2 (en)
JP (1) JP2000501539A (en)
KR (1) KR19990071554A (en)
WO (1) WO1998013763A2 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19809640A1 (en) * 1998-03-06 1999-09-09 Pact Inf Tech Gmbh Speed-optimized cache system
US6557078B1 (en) * 2000-02-21 2003-04-29 Hewlett Packard Development Company, L.P. Cache chain structure to implement high bandwidth low latency cache memory subsystem
US6539457B1 (en) * 2000-02-21 2003-03-25 Hewlett-Packard Company Cache address conflict mechanism without store buffers
US6606684B1 (en) 2000-03-31 2003-08-12 Intel Corporation Multi-tiered memory bank having different data buffer sizes with a programmable bank select
US6446181B1 (en) 2000-03-31 2002-09-03 Intel Corporation System having a configurable cache/SRAM memory
US7073026B2 (en) * 2002-11-26 2006-07-04 Advanced Micro Devices, Inc. Microprocessor including cache memory supporting multiple accesses per cycle
US7769950B2 (en) * 2004-03-24 2010-08-03 Qualcomm Incorporated Cached memory system and cache controller for embedded digital signal processor
US7613065B2 (en) 2005-09-29 2009-11-03 Hynix Semiconductor, Inc. Multi-port memory device
KR100780621B1 (en) * 2005-09-29 2007-11-29 주식회사 하이닉스반도체 Multi port memory device
KR100754359B1 (en) * 2006-03-29 2007-09-03 엠텍비젼 주식회사 Multi-port memory device including plurality of shared blocks
KR101635395B1 (en) 2010-03-10 2016-07-01 삼성전자주식회사 Multi port data cache device and Method for controlling multi port data cache device
KR101788245B1 (en) 2011-02-25 2017-11-16 삼성전자주식회사 Multi-port cache memory apparatus and method for operating multi-port cache memory apparatus
CN102622192B (en) * 2012-02-27 2014-11-19 北京理工大学 Weak correlation multiport parallel store controller
US9171594B2 (en) * 2012-07-19 2015-10-27 Arm Limited Handling collisions between accesses in multiport memories
KR102346629B1 (en) * 2014-12-05 2022-01-03 삼성전자주식회사 Method and apparatus for controlling access for memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5056002A (en) * 1987-02-09 1991-10-08 Nec Corporation Cache memory for use with multiprocessor systems
US5274790A (en) * 1990-04-30 1993-12-28 Nec Corporation Cache memory apparatus having a plurality of accessibility ports
US5276850A (en) * 1988-12-27 1994-01-04 Kabushiki Kaisha Toshiba Information processing apparatus with cache memory and a processor which generates a data block address and a plurality of data subblock addresses simultaneously
US5434989A (en) * 1991-02-19 1995-07-18 Matsushita Electric Industrial Co., Ltd. Cache memory for efficient access with address selectors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5056002A (en) * 1987-02-09 1991-10-08 Nec Corporation Cache memory for use with multiprocessor systems
US5276850A (en) * 1988-12-27 1994-01-04 Kabushiki Kaisha Toshiba Information processing apparatus with cache memory and a processor which generates a data block address and a plurality of data subblock addresses simultaneously
US5274790A (en) * 1990-04-30 1993-12-28 Nec Corporation Cache memory apparatus having a plurality of accessibility ports
US5434989A (en) * 1991-02-19 1995-07-18 Matsushita Electric Industrial Co., Ltd. Cache memory for efficient access with address selectors

Also Published As

Publication number Publication date
JP2000501539A (en) 2000-02-08
KR19990071554A (en) 1999-09-27
WO1998013763A2 (en) 1998-04-02
EP0875030A2 (en) 1998-11-04

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