WO1998005122A1

WO1998005122A1 - Multiplexer circuit

Info

Publication number: WO1998005122A1
Application number: PCT/IB1997/000696
Authority: WO
Inventors: Gerard Francis Harkin
Original assignee: Philips Electronics N.V.; Philips Norden Ab
Priority date: 1996-07-27
Filing date: 1997-06-13
Publication date: 1998-02-05
Also published as: GB9615836D0

Abstract

A multiplexer circuit comprises a plurality of switching circuits (32), each switching circuit selectively coupling an input (16) to a common output (34). The input is preferably a column of pixels of an image sensor array. Each switching circuit (32) comprises at least three series connected diode members SCD1 to SCD3 coupled between an associated pair of signal conductors (48, 50). The common output (34) is coupled to the point of connection of the first and second diode members SCD1, SCD2 and the column (16) of pixels is coupled to the point of connection of the second and third diode members SCD2, SCD3. The switching circuit is operable in a first mode in which the three diode members SCD1 to SCD3 are each forward biased and a current measured at the terminal (34) represents the current flowing to the input of the switching circuit (32), and a second mode in which at least the second diode member SCD2 is reverse biased and the input is isolated from the output. The switching circuit is diode-based, enabling integration with a diode based image sensor array, and can be implemented with a small number of components, occupying a small area around the edge of the array.

Description

DESCRIPTION

MULTIPLEXER CIRCUIT

This invention relates to the addressing of arrays of electrical elements, and particularly concerns a multiplexer circuit for reading the signals from elements of such an array The array of device elements are particularly, but not exclusively, formed with thin film circuitry and are arranged in rows and columns, the columns having column multiplexer switches The device elements may be image sensor elements of a large area image sensor

It is known to provide row or column multiplexers for addressing or reading an array of electronic devices, for example an array of image sensor pixels Such multiplexer circuits generally comprise a plurality of switches, each switch selectively coupling a device, for example a column of pixels of an image senor array, to a common terminal If the multiplexer circuit can be formed on the array, the common terminal then constitutes an output of the array As a result, an individual output is no longer required for each column of pixels Various types of switch are available which may be used to form multiplexer circuits One type of switch uses a diode bridge having four diodes, the four connection points around the bridge defining an input, output and two control terminals The control terminals enable the four diodes to be switched between forward bias, when the input is linked to the output, and reverse bias, when the output is isolated from the input US 4 150 256 (e g Figure 3 thereof) discloses a multiplexer circuit comprising an array of switches, each switch comprising such a diode bridge having four diodes which are selectively forward biased or reversed biased by the application of control voltages to two control terminals The diode bridge switch is conventionally used as a voltage switching device and additional components are required for coupling the control voltages to the two control terminals As a result, each switch requires a large number of components, which may occupy a significant area around the array of device elements

The present invention seeks to provide a multiplexer circuit for an array of electrical devices, using diode based switches which may be integrated onto the substrate of the array of electronic devices, the switches of the multiplexer circuit being used to switch a current from the input to the output

According to the present invention, there is provided a multiplexer circuit comprising a plurality of switching circuits, each switching circuit selectively coupling a respective input to a common output, the multiplexer circuit including a charge measurement device connected to the common output, each switching circuit comprising at least three series connected diode members coupled between an associated pair of signal conductors, the common output being coupled to the point of connection of the first and second diode members and the respective input to the switch being coupled to the point of connection of the second and third diode members, the switching circuit being operable in a first mode in which the three diode members are each forward biased and a current at the output represents the current flowing to the input of the switching circuit, and a second mode in which at least the second diode member is reverse biased and the input is isolated from the output

Each diode member may comprise a single diode or a plurality of series connected diodes In its simplest form, the switching circuit of the invention may be constructed with only three series-connected diodes Effectively, one diode is connected between the input and the output of the switch, and the polarity of this diode determines whether a signal at the input gives rise to an associated signal at the output of the switching circuit The switching circuit is diode-based, enabling integration with a diode-based image sensor array, and can be implemented with a small number of components, thereby occupying a small area around the edge of such an image sensor array

A problem which arises in image sensors is interference between pixels in a column (vertical cross-talk) This arises because currents are produced by illuminated pixels, and these currents may flow into the associated column When the associated column multiplexer switch is turned off, there is no path along which these currents may dissipate and they accordingly alter the charge on the distributed column capacitance to create voltage biases on the other pixels of other rows in the column.

When the multiplexer circuit of the invention is to be applied to an image sensor, comprising an array of image sensing elements arranged in rows and columns, a clamping switch is preferably coupled to the respective column conductor for clamping the potential of the column conductor when the switching circuit is turned off

The clamping arrangement may comprise first and second clamping diode members coupled between the respective input of the switching circuit and the pair of signal conductors, the clamping diode members being forward biased in the second mode of operation of the switching circuit The clamping diode members may comprise one or more series-connected diodes

When the switching circuit is turned off, any current produced in the respective column and which is allowed to flow to the column conductor may be transferred to the signal conductors by the diodes of the clamping switch In the case of an image sensor, this means that a current produced by a pixel, for example in a selected row, and which is in a column having the multiplexer switch turned off, will flow to the voltage lines instead of causing a bias on the other pixels of the column

When this clamping arrangement is used, the signal conductors comprise switching signal conductors, the signals applied to the switching signal conductors determining the mode of operation of the switching circuit The three diode members are each reverse biased in the second mode of operation, and the clamping diodes are then forward biased

The clamping arrangement may alternatively comprise a clamping diode or diodes coupled between the respective input of the switching circuit and a clamping signal conductor, the clamping diode or diodes being forward biased in the second mode of operation of the switching circuit

With this type of clamping arrangement, the signal applied to the clamping signal conductor determines whether the clamping arrangement is on or off The clamping signal conductor may itself determine the mode of operation of the switching circuit as a whole In this case, the associated pair of signal conductors may be shared by each switching circuit This enables the number of control lines for the circuit to be reduced Furthermore, the first diode member for each switching circuit may be shared by each switching circuit, because the pair of signal conductors are not unique to each switching circuit This enables a reduction in the number of diodes required to fabricate the multiplexer circuit

A multiplexer according to the invention may comprise one or more groups of inputs, each group having an associated multiplexer circuit of the invention The invention also provides an image sensor comprising a plurality of rows and columns of image sensing pixels, signals from the columns being supplied to a multiplexer of the invention

These and other features of the present invention, and their advantages are illustrated specifically in the embodiments of the invention now to be described, by way of example, with reference to the accompanying drawings in which,

Figure 1 is a diagram to explain the operation of an image sensor pixel Figure 2 is a simplified circuit diagram of part of an image sensor device in accordance with the present invention, and having a column multiplexer, Figure 3 is a circuit diagram of one multiplexer switch of the multiplexer used in the circuit of Figure 2,

Figure 4 is an equivalent circuit for explaining the operation of part of the multiplexer switch of Figure 3,

Figure 5 is a circuit diagram of an alternative multiplexer switch for the multiplexer of Figure 2, and

Figure 6 is an alternative design of column multiplexer circuit based on the switch of Figure 5

Figure 1 shows an example of four pixels of a known charge storage device in the form of an image sensor 10 Although only four pixels 12 are shown, the image sensor 10 will comprise a two dimensional matrix of rows and columns of pixels with associated row 14 and column 16 conductors

Each pixel 12 comprises a photosensitive diode PD and a switching diode SD coupled in series between the associated row conductor 14 and column conductor 16 In the example shown, the switching diode SD and photodiode PD are arranged with the cathodes coupled together, although they may be connected oppositely A capacitor C is shown coupled across the photosensitive diode PD This capacitor C may be the parasitic capacitance of the photosensitive diode PD or may be an additional capacitor added to increase the dynamic range of the image sensor 100 Light incident upon a photodiode will generate a minority carrier current in the photodiode as shown by arrow 18

This current may be read out either by directly measuring the photodiode current produced while the switching diode is forward biased, or the photodiode current may be allowed to discharge the capacitance C during a so-called integration period, the level of illumination being determined by the current required to subsequently recharge the capacitor In either case, the current is measured using charge sensitive amplifiers 20 coupled to the column conductors Alternative systems may be employed for measuring the charge resulting from the photodiode current For example, the charge measurement device may convert the capacitor recharging current into a proportional voltage signal for subsequent measurement The term "charge measurement device" in the description and claims should be interpreted accordingly

A known problem with image sensor arrays is that since the row driver circuit and column reading circuit are not integrated onto the substrate of the image sensor array, interconnections must be provided between each row R and the row driver circuit, and between each column C and the column reading circuit Multiplexer circuits are therefore required which may be integrated onto the substrate of the image sensor so as to reduce the number of connections to the substrate

Figure 2 shows an image sensor using a column multiplexer circuit, in accordance with the invention

The image sensor 100 shown in Figure 2 comprises an array 10 of image sensor pixels 12 corresponding to those shown in Figure 1 For the purposes of clarity, the capacitances associated with the photodiodes have not been shown in Figure 2 A row driver circuit 30 is provided for producing Itne- scan pulses which are applied sequentially to the row conductors 14, to sequentially address the rows R of the array As explained with reference to Figure 1 , these line-scan pulses serve to forward bias the switching diodes SD of the addressed row

The columns C are arranged in groups, such as group C1 to C3 and group C4 to C6 Each such group has a respective common terminal 34 The column conductor 16 for each column is connected to an associated multiplexer switching circuit 32 which couples the column conductor 16 to the common terminal 34 In this way the switching circuits 32 transmit the signal from a selected column conductor 16 through to the common terminal 34 Thus, the photo-generated signal from the photodiode PD of a selected row is transmitted through the forward biased switching diode SD to the column conductor and is read via the respective column multiplexer switching circuit 32 The switching circuits 32 together form column multiplexer 33 A respective charge sensitive amplifier 20 is connected to each common terminal 34 to read the photo-generated signal in known manner Each common terminal 34 can be considered to be associated with its own multiplexer circuit, which circuits together form the complete column multiplexer In the appended claims, the term "multiplexer circuit" represents a combination of switching circuits associated with an individual common terminal One or more such multiplexer circuits may form the complete column multiplexer

To read the complete array, the row pulses may sequentially scan the rows three times (for the circuit of Figure 2) In a first scan, the signals from columns C1 , C4, C7 of each row may be supplied to the respective common terminal by the respective multiplexer circuit In the second scan, the signals from columns C2, C5, C8 are supplied to the respective common terminal 34, and in the third scan, the signals from columns C3, C6, C9 are measured After a row of pixels has been addressed (and some of those pixels discharged or recharged during signal reading) it may be necessary to reset the row so that each pixel is then subjected to integration periods of equal duration Resetting a row of pixels basically involves applying a read-out voltage to all column conductors

Of course, the number of columns associated with each amplifier will determine the number of control lines and the multiplexing ratio of the circuit The multiplexing ratio is the ratio of the number of column conductors to the number of readout amplifier channels, and therefore equates to the number of columns associated with each common terminal A higher multiplexing ratio gives a more efficient design since it reduces the number of output terminals of the array, but the number of control lines which are required (and which also require terminal connections) must also be taken into consideration

As explained, the column multiplexer 33 and image sensor array are formed on the same substrate, using the same thin film circuitry The charge sensitive amplifiers 20 may be formed as monolithic silicon integrated circuits separate from the device substrate on which the array 100 and column multiplexer switching circuits 32 are formed Thus, the common terminals 34 may be the output terminals of the device substrate Similarly, the row driver circuit 30 may be formed as a monolithic silicon integrated circuit, so that the connections between the row driver circuit 30 and the row conductors 14 may also be connection terminals of the device substrate It may also be possible to form at least part of the row driver circuit 30 and/or charge-sensitive amplifiers 20 in thin film circuitry, which may therefore be formed on the same device substrate as the array 100

The switching circuits 32 are shown only schematically in Figure 2 and Figure 3 shows the circuit diagram for each multiplexer switching circuit 32 in a first embodiment

The switching circuit 32 comprises switching signal conductors 48, 50 which are used to control the operation of the switch This switching circuit 32 5 has a switching circuit portion, comprising three diodes SCD1 , SCD2, SCD3 connected in series between the switching signal conductors 48, 50 The switching circuit also has a clamping portion comprising diodes CD1 and CD2, which will be explained below

The input to the switching circuit comprises a column conductor 16 of the ι o array shown in Figure 2, and this input is connected between the second and third switching circuit diodes SCD2, SCD3 The output of the switching circuit

32 is connected to the point of connection of the first and second switching circuit diodes SCD1 , SCD2

The switching signal conductors 48, 50 may be controlled in two modes i s For the first mode of operation, conductor 48 has a higher potential than conductor 50 such that the three switching circuit diodes are forward biased and a current flows between the switching signal conductors 48, 50 In this case the switching circuit is effectively turned on, and an input current supplied from the column conductor 16 gives rise to a representative (but not equal) 20 output current to the common terminal 34 This current is then measured by the charge sensitive amplifier 20

As shown in Figure 3, the charge sensitive amplifier comprises an integrating circuit which has the effect of holding the common terminal 34 to a potential of 2 5 volts 25 The operation of the switching circuit shown in Figure 3 will now be explained with reference to Figure 4, which is a simplified circuit representing the switching circuit portion of the circuit shown in Figure 3

Figure 4 assumes that the switching circuit is in the ON condition, and accordingly a voltage of +5 Volts has been applied to the conductor 48, and a 30 voltage of -2 5 Volts has been applied to the conductor 50 The voltage drops across the diodes SCD1 , SCD2, SCD3 are sufficiently high to forward bias the diodes, and the diodes operate in the linear portion of their forward bias l-V characteristics. In other words, these diodes can be represented by resistors, as shown in Figure 4.

Assuming the diodes can be represented by equal value resistors, and if no current flows from the column conductor 16 then

«1 ^=I*2 ⁼ *3 ^{( 1 )}

Consequently, there is a 2.5 Volt drop across each diode No current flows to the output 34

If, alternatively, an input current i_co( is to be sampled, to provide an output current i_out, then referring to Figure 4 the following equations hold'

'3 = *2 ⁺ ϊcol " '1 ^{+ l}col ^{" l}out ^{( 3 )}

Of course, ι, is constant because a constant voltage drop is present across diode SCD1

Given that the voltage drop across diodes SCD1 is 2.5 Volts, and the voltage drop across SCD2 and SCD3 is 5 Volts, summing voltages gives

(<1 ^{+ l}col ^{~ R}SCD3 ⁺ ( ^{~ l}ouι) ^RSCD2 = ^{2 R}SCD1 ^{( 4 )}

\^RSCD2 ^{+ R}SCD3 2.R_SCDj) ^RSCD3 (5) ^l°^ul P + P ¹ P + P ^{< o/} ^ΛSCD2 ^ΛSCD3 ^Λ5CD2 "SCD3

The gain of the circuit is given by

From the gam equation (6), it is clear that if the diodes can be represented by equal resistances, then the gam of the circuit is 0 5 Of course

the gain of the circuit may be increased if the resistance of diode SCD3 is increased relatively to the resistance of diode SCD2.

The analysis above shows the input-output response of the switching circuit 32. It has been assumed that the diodes are operated in the linear portion of their current-voltage characteristic. However, the diodes could equally be operated in the exponential region of their current-voltage characteristic, although with the effect that the resistances RSCD2 and RSCD3 in equation 5 can no longer be considered as constants with respect to the column current, and the gain can therefore no longer be considered as independent of the column current. This may not be a problem, if appropriate interpretation of the output current to the column or terminal 34 is provided. However, to obtain a predictable linear gain, it is preferred to operate the diodes in the linear region.

Returning to Figure 3, the switching circuit 32 also includes a clamping section which comprises first and second clamping diodes CD1 , CD2 connected in series between the switching signal conductors 48, 50, and having opposite polarity to the switching circuit diodes SCD1 to SCD3. The column conductor 16 is connected between the clamping diodes CD1 , CD2 as shown. The clamping diodes CD1 , CD2 constitute a switch for clamping the potential of the column conductor 16 when the switching circuit 32 is in the OFF condition.

The multiplexer switching circuit 32 is switched between the ON and OFF conditions by voltage pulses applied to the switching signal conductors 48, 50. In the ON condition described above, the clamping diodes CD1 , CD2 are reversed biased and play no part in determining the response of the switch 32. However, when the switching circuit is turned off, the clamping diodes CD1 , CD2 play a part in the operation of the switching circuit 32. The OFF condition of the switch may be achieved, for example, by pulsing the signal conductor 48 to -2 Volts and pulsing the signal conductor 50 to +8 Volts. This has the effect of reverse biasing of all of the switching diodes SCD1 to SCD3, and forward biasing the clamping diodes CD1 and CD2

With these voltage levels, and assuming the clamping diodes CD1 and

CD2 have equal on resistances, the clamping diodes clamp the column conductor 16 to a constant potential of 3 Volts This clamping voltage is preferably selected to correspond to the row voltage as will be explained in the following

The clamping effect can best be understood by considering the device elements (image sensor pixels) of the various rows which are coupled to the respective column conductor 16 Thus, taking as an example the multiplexer switching circuit 32 associated with column C1 in Figure 2, the pixels of row R1 may be addressed by a positive voltage scanning pulse on the associated row conductor 14 In this case the switching diode SD of row R1 column C1 is forward biased and the switching diodes of all the other rows R2, R3 etc in column C1 are reverse biased Although the switching diode SD of row R1 is forward biased, the image signal of the associated pixel is not read out by the charge sensitive amplifier 20 because the associated switching circuit 32 is turned off Although the switching diodes SD of the other rows R2, R3 of column C1 are reverse biased, there is still a small leakage current through these diodes In the clamping state of the diodes CD1 , CD2, currents resulting from the image signal of the pixel in row R1 and column C1 , and the leakage currents through the switching diodes of the other rows in column C1 are drained safely away via the forward biased clamping diodes CD1 and CD2

In the absence of the forward biased clamping diodes CD1 , CD2 these currents could cause a potential of the column conductor 16 to vary, and so could change the bias conditions in the non addressed rows R2, R3 of the respective column When these pixels in the non addressed rows R2 R3 are later addressed, a false signal, not representative of the image illumination incident on these pixels, could have been read out as a result of these changed biased conditions This undesirable effect is avoided by the provision of the clamping portion of each of the switching circuits 32

The clamping portion therefore provides a sink for leakage currents and for the photodiode current of a pixel in the selected row, and also holds the potential of the column conductor (the input) at a substantially constant value This constant potential may correspond to the row voltage There may, of course, be provided a different number of diodes between the column conductor 16 and each switching signal conductor 48, 50 This may be desired to alter the control voltage levels It may, in any case, be desirable to use series connected groups of diodes instead of single diodes, so that the total current flowing through the switch is reduced Obviously the current dissipation of the switch and the number of diodes required are both taken into consideration when designing the multiplexer switching circuits

The clamping voltage level (3 Volts) and the voltage level at which the column conductor is held during signal read-out (0 Volts) are selected to ensure correct operation of each pixel For example, it is necessary to ensure that, when switching from the column clamping potential (3 Volts) to the column readout potential (0 Volts), the row voltage is sufficient to forward bias the switching diode SD of the pixel being read out

Other forms of clamping arrangement may be considered provided they introduce a current sink for draining current from the column conductor 16, and hold the column conductor 16 at a desired substantially constant potential Figure 5 shows an alternative arrangement for the switching circuit 32 which employs a different clamping arrangement

As shown, the switching circuit portion again comprises three series- connected diodes between the conducting lines 48, 50 This portion of the circuit operates in the same way as the corresponding elements in the circuit of Figure 3 Thus, when the signals on the conductors 48, 50 are selected to forward bias the switching circuit diodes, then the output current is representative of the current flowing from the column conductor 16, and when the switching circuit diodes are reversed biased, no current flows to the output

A single clamping diode CD3 couples the column conductor 16 to a further conducting line 52 The voltage to be applied to the conducting line 52 is selected such that the clamping diode CD3 is reverse biased when the switching circuit 32 is turned on so that it plays no part in determining the output of the switching circuit 32 For example, when the switching circuit 32 is turned on, a potential of 5 Volts may be applied to conducting line 48, a potential of -2 5 Volts may be applied to conducting line 50 and -2 5 Volts may be applied to the further conducting line 52 Thus, clamping diode CD3 remains reverse biased This is achieved if the line 52 has a voltage of 0 volts or less.

During the OFF condition of the switching circuit, the clamping diode CD3 is arranged to be forward biased, and this is achieved by applying a voltage to the further conducting line 52 which is higher than the potential at the point of connection N of diodes SCD2 and SCD3 For example, a potential of 2.5 Volts may be applied to conductor 48, a potential of 0 Volts may be applied to conductor 50 and a potential of 5 Volts may be applied to the further conductor 52 In this case, diode SCD1 is turned off, because the cathode and anode are held at 2 5 Volts, the connection point N is held at 2 5 Volts by the diodes CD3 and SCD3, and consequently the diode SCD2 is also turned off The potential of the column conductor is clamped to 2 5V, and no current flows to the common terminal 34 The clamping diode CD3 in association with the diode SCD3 again provides a sink for current flowing down the column conductor 16, and clamps the potential of the column conductor, preferably to approximately the row voltage

The switching circuits of Figures 3 and 5 may be applied to the image sensor array shown in Figure 2 In the example shown, groups of three switching circuits 32 each share a common output 34 Therefore, for the charge sensitive amplifier 20 to read the signal from an individual column, only one of the three switching circuits 32 must be in the ON condition For this purpose, each switching circuit 32 requires separate conducting lines 48, 50 as shown However, the conducting lines may be shared between the switching circuits 32 associated with different charge sensitive amplifiers 20 This is also shown in Figure 2 When the switching circuit of Figure 5 is to be employed each switching circuit 32 requires three control lines, instead of the two shown in Figure 2

An advantage of the switching circuits of Figures 3 and 5 is that the switching circuits 32 are actively turned off, namely the diodes SCD1 and SCD2 are each reverse biased when the switch is turned off In the switching circuit of Figure 3, all three switching circuit diodes SDCD1 to SCD3 are turned off during clamping This reduces any continuous currents flowing tn the switching circuits when they are turned off This constraint does, however, require the multiplexer 33 to have a large number of control terminals to enable each switching circuit 32 to be actively turned on or off A further embodiment of the invention enables an additional reduction in the number of diodes required to implement the multiplexer circuit, and also reduces the number of control lines which must supply the multiplexer circuit 33 As shown in Figure 6, each column C1 , C2, C3 is associated with a switching circuit corresponding to that shown in Figure 5 Thus, each column is associated with three series connected switching circuit diodes SCD1 to SCD3 and a clamping diode CD3 The switching circuit diode SCD1 connected between the column terminal 34 and the conducting line 48 is shared between each of the switching circuits 32 thereby reducing the overall number of diodes in the multiplexer However, the voltage applied to the conductor 48 can not be selected individually for each switching circuit 32 In other words it is not possible to actively turn off individual switching circuits using the conductors 48,50 Instead in the circuit of Figure 6, the conducting lines 48 50 have constant voltages applied to them, for example a voltage of 5 Volts is applied to conducting line 48 and a voltage of -2 5 Volts is applied to conducting line 50 As will be explained in the following, only one pair of switching circuit diodes SCD2 SCD3 are both forward biased at any one time As a result, the voltage levels above ensure that the output terminal 34 is driven to 2 5 Volts so that the switching circuits 32, 32₂ 32₃ are matched with the charge sensitive amplifier 20, which holds the common terminal 34 to 2 5 Volts The signals applied to the additional conducting lines 52 effect the switching on or off of the switching circuit 32, 32₂, or 32₃ of the individual columns For example, if the additional conducting line 52, of column C1 is driven to a high voltage value, for example 7 5 Volts, then the clamping diode CD3, conducts and the conducting line 16, will be held at 2 5 Volts by the diode pair CD3, and SCD3, As in the embodiment of Figure 5, this causes diode SCD2, to turn off, so that the switching circuit 32, is isolated from the common terminal 34 The skilled addressee will appreciate that only the one conducting pair of diodes SCD2 and SCD3 will interact with the diode SCD1 and supply an output to the common terminal 34 Consequently, the diode characteristics can easily be calculated to achieve the desired matching of the common terminal voltage defined by the three diodes SCD1 to SCD3 and the voltage applied to the common terminal 34 by the charge sensitive amplifier 20

It is possible for all of the switching circuits 32 associated with the columns to be turned off, and no signal from the columns 16 will be supplied to the charge sensitive 20 However, for reading out an individual column, one of the switching circuits 32 must be in the ON condition For example, if the switching circuit associated with column C2 is turned on then the voltage level applied to the additional conducting line 52₂ will be such as to reverse bias the clamping diode CD3₂ For example, a voltage of 0 Volts (or lower) may be applied to the additional conductor 52₂ so that the three diodes of the switching circuit associated with column C2 each conduct and the current from the column conductor 16₂ causes an associated flow of charge to the charge sensitive amplifier 20 in the manner described with reference to Figures 3 and 4

During the operation of the multiplexer shown in Figure 6, the switching circuit of only one column associated with a charge sensitive amplifier 20 is switched on at any one time, so that individual column signals can be read out The circuit shown in Figure 6 may represent the combination of the three switching circuits 32 shown in Figure 2 associated with columns C1 to C3 However, each switching circuit 32 only requires a single control line for controlling the potential of the additional conductor 52 Of course the conductors 52 may be shared between the switching circuits 32 associated with different charge sensitive amplifiers 20

The circuit of Figure 6 enables the number of diodes required to fabricate the multiplexer circuit 33 to be reduced, and also reduces the required number of control lines However, even when a switching circuit is turned off and the signal from the associated column conductors 16 is not being transferred to the charge sensitive amplifier 20, a constant current still flows in the switching circuit 32 For example, if the switching circuit 32, associated with column C1 is turned off as described above, the diodes SCD3, and CD3, are connected in series and are conducting between voltage sources 52, and 50 Thus, a diode of the switching portion of the circuit remains in a conductive state, in contrast with the circuit of Figure 3 (where only the clamping circuit is operative in the off condition of the switch) This is also the case in the circuit of Figure 5, upon which the combined circuit of Figure 6 is based

In each of the circuits described above, it is desirable for the potential at which the amplifier holds the common terminal to be matched with the potential which the voltage divider defined by the switching circuit diodes SCD1 to SCD3 seeks to apply to the common terminal If these two voltages are not matched, a current must flow to or from the amplifier causing an error in the output signal One source of this error will be a voltage input offset of the amplifier 20 A suitable compensation scheme may be employed to cancel this offset The response of the circuit will also be improved if the amplifier has a high open loop gain, if the supply lines are matched and if the diode characteristics can be matched These possibilities will all be apparent to those skilled in the art It may be necessary to limit the total currents flowing within the complete multiplexer 33 through appropriate choice of the diode characteristics and number of diodes Thus although in the circuits described the minimum number of diodes has been employed, it may be desirable to replace individual diodes in some situations with two or more diodes in series This increases the impedances and thereby reduces the currents flowing within each switching circuit From reading the present disclosure, other modifications and variations will be apparent to persons skilled in the art Such modifications and variations may involve equivalent features and other features which are already known in the art and which may be used instead of or in addition to features already disclosed herein Although claims have been formulated in this Application to particular combinations of features, it should be understood that the scope of the disclosure of the present application includes any and every novel feature or any novel combination of features disclosed herein either explicitly or implicitly and any generalisation thereof, whether or not it relates to the same invention as presently claimed in any Claim and whether or not it mitigates any or all of the same technical problems as does the present invention The Applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during prosecution of the present application or of any further application derived therefrom

Claims

1 A multiplexer circuit comprising a plurality of switching circuits each switching circuit selectively coupling a respective input to a common output, the multiplexer circuit including a charge measurement device connected to the common output, each switching circuit comprising at least three series connected diode members coupled between an associated pair of signal conductors, the common output being coupled to the point of connection of the first and second diode members and the respective input to the switch being coupled to the point of connection of the second and third diode members, the switching circuit being operable in a first mode in which the three diode members are each forward biased and a current at the output represents the current flowing to the input of the switching circuit, and a second mode in which at least the second diode member is reverse biased and the input is isolated from the output

2 A multiplexer circuit as claimed in claim 1 , further comprising a clamping arrangement comprising first and second clamping diode members coupled between the respective input of the switching circuit and the pair of signal conductors, the clamping diode members being forward biased in the second mode of operation of the switching circuit

3 A multiplexer circuit as claimed in claim 1 or 2, wherein the signal conductors comprise switching signal conductors the signals applied to the switching signal conductors determining the mode of operation of the switching circuit, and wherein the three diode members are each reverse biased in the second mode of operation

4 A multiplexer circuit as claimed in claim 1 , further comprising a clamping arrangement comprising a clamping diode member coupled between the respective input of the switching circuit and a clamping signal conductor the clamping diode member being forward biased in the second mode of operation of the switching circuit

5 A multiplexer circuit as claimed in claim 4, wherein the signal applied to the clamping signal conductor determines the mode of operation of the switching circuit, the associated pair of signal conductors being shared by each switching circuit

6 A multiplexer circuit as claimed in claim 5, wherein the first diode member for each switching circuit is shared by each switching circuit

7 A multiplexer circuit as claimed in claim any preceding claim wherein the respective input comprises a column of an array of image sensing elements

8 A multiplexer circuit as claimed in any preceding claim wherein each diode member of the switching circuit comprises a single diode or a plurality of series-connected diodes and wherein each clamping diode member comprises a single diode or a plurality of series-connected diodes

9 A multiplexer comprising one or more groups of inputs, each group having an associated multiplexer circuit in accordance with any preceding claim

10 An image sensor comprising a plurality of rows and columns of image sensing pixels, signals from the columns being supplied to a multiplexer as claimed in claim 9