WO1997046959B1 - Hardware and software development in computer systems having multiple discrete components - Google Patents
Hardware and software development in computer systems having multiple discrete componentsInfo
- Publication number
- WO1997046959B1 WO1997046959B1 PCT/US1997/009290 US9709290W WO9746959B1 WO 1997046959 B1 WO1997046959 B1 WO 1997046959B1 US 9709290 W US9709290 W US 9709290W WO 9746959 B1 WO9746959 B1 WO 9746959B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- interfaces
- hdl
- component
- internal
- recited
- Prior art date
Links
- 230000000875 corresponding Effects 0.000 claims abstract 6
- 230000002093 peripheral Effects 0.000 claims 26
- 230000001755 vocal Effects 0.000 claims 1
Abstract
A computer system includes a plurality of discrete computer components and an integrated circuit that interfaces between the discrete computer components. The integrated circuit has internal hardware interfaces corresponding to respective discrete computer components. The internal hardware interfaces are selected from a limited number of available pre-defined internal hardware interfaces for general kinds of computer components. The internal hardware interfaces are accessible only within the integrated circuit. The integrated circuit further includes component-specific hardware interfaces for connecting the individual discrete components to the selected pre-defined internal HDL interfaces. The component-specific hardware interfaces are designed individually for the different discrete computer components to interface the discrete components to the internal hardware interfaces. A development system is disclosed for use during development of such a computer system. The development system includes interconnections that allow functions to be easily moved from the integrated circuit to a system CPU.
Claims
1. A development system comprising: a programmable component interface having a plurality of configurable signal lines; a plurality of peripheral modules, each peripheral module being connected to a set of the configurable signal lines; the programmable component interface having internal hardware interfaces corresponding to respective peripheral modules, the internal hardware interfaces being accessible only within the integrated circuits; the programmable component interface further including interconnection logic between the internal hardware interfaces; the programmable component interface further including component-specific hardware interfaces for configuring the sets of configurable signal lines to which the peripheral modules are connected, the component-specific hardware interfaces connecting the peripheral modules to the internal hardware interfaces; the component-specific hardware interfaces being designed individually for the different peripheral modules to interface the peripheral modules to the internal hardware interfaces.
2. A development system as recited in claim 1 , wherein the programmable component interface is a programmable gate array.
3. A development system as recited in claim 1, wherein the peripheral modules are removable and replaceable.
4. A development system as recited in claim 1 , wherein the configurable signal lines of each set are unique to that set.
5. A development system as recited in claim 1 , wherein the configurable signal lines of each set are unique to that set, and wherein all of the peripheral modules are also connected to a common group of signal lines.
6. A development system as recited in claim 1 , wherein the internal hardware interfaces are selected from a limited number of available pre-defined internal hardware interfaces for general kinds of computer components.
7. A development system as recited in claim 1 , further comprising a CPU module, the CPU module having a CPU, wherein the CPU module has connections to all of the sets of configurable signal lines.
8. A development system as recited in claim 1, further comprising a CPU module, wherein: the CPU module has a CPU; the CPU module has connections to all of the configurable signals lines of the programmable component interface; and the CPU can be connected on the CPU module to any of the configurable signal lines of the programmable component interface.
9. A development system as recited in claim 1 , further comprising a CPU module, wherein: the configurable signal lines of each set are unique to that set; all of the peripheral modules are also connected to a common group of signal lines; the CPU module has a CPU; the CPU module has connections to all of the sets of configurable signal lines and to the common group of signal lines; and the CPU can be connected on the CPU module to any of the configurable signal lines of the sets and of the common group.
10. A development system comprising: a programmable component interface having a plurality of configurable signal lines; a plurality of peripheral modules; each peripheral module being connected to a set of the configurable signal lines, wherein the configurable signal lines of each set are unique to that set; all of the peripheral modules being connected to a common group of signal lines; the programmable component interface having internal hardware interfaces corresponding to respective peripheral modules, the internal hardware interfaces being accessible only within the integrated circuits, wherein the internal hardware interfaces are selected from a limited number of available pre-defined internal hardware interfaces for general kinds of computer components; the programmable component interface further including interconnection logic between the internal hardware interfaces; the programmable component interface further including component-specific hardware interfaces for configuring the sets of configurable signal lines to which the peripheral modules are connected, the component-specific hardware interfaces connecting the peripheral modules to the internal hardware interfaces; the component-specific hardware interfaces being designed individually for the different peripheral modules to interface the peripheral modules to the internal hardware interfaces; a CPU module having a CPU; wherein the CPU module has connections to all of the sets of configurable signal lines and to the common group of signal lines, and wherein the CPU can be connected on the CPU module to any of the configurable signal lines of the sets and of the common group.
11. A development system comprising: a logic module having a programmable component interface, the programmable component interface having a plurality of configurable interface lines; a plurality of peripheral electrical connectors for connection to peripheral modules, wherein a set of the configurable interface lines is accessible through the peripheral electrical connectors by each of the peripheral modules; one or more CPU electrical connectors for connection to a CPU module, wherein the sets of configurable interface lines are accessible through the one or more CPU electrical connectors, and wherein a CPU on the CPU module can be connected to any lines of the sets of interface lines to control such interface lines in place of the programmable component interface.
12. A development system as recited in claim 11 , wherein the programmable component interface is a gate array.
13. A development system as recited in claim 11, wherein the configurable signal lines of each set are unique to that set.
14. A development system as recited in claim 11, wherein the configurable signal lines of each set are unique to that set and wherein a common group of the configurable signal lines is accessible through the peripheral electrical connectors by the peripheral modules.
15. A development system as recited in claim 1 1 , wherein: the configurable signal lines of each set are unique to that set; a common group of the configurable signal lines is accessible through the peripheral electrical connectors by the peripheral modules; and the CPU on the CPU module can be connected to any lines of the common group.
16. In a computer system, a method of designing component interface hardware between a plurality of discrete computer components comprising the following steps: selecting pre-defined internal HDL interfaces for respective discrete computer components, each pre-defined internal HDL interface being selected from a limited number of available pre-defined internal HDL interfaces for general kinds of computer components, the pre-defined internal HDL interfaces being accessible only within an integrated circuit; designing component-specific HDL interfaces for connecting the individual discrete components to the selected pre-defined internal HDL interfaces, the component- specific HDL interfaces defining (a) external interface signals for connection to the discrete components, and (b) internal interface signals for connection to the selected pre-defined internal HDL interfaces.
17. A method as recited in claim 16, the selected pre-defined internal HDL interfaces specifying connections to the component-specific HDL interfaces in terms of constants that can be set by a designer after selecting the pre-defined internal HDL interfaces, the method further comprising a step of setting the constants in accordance with desired connections between the component-specific HDL interfaces and the selected pre-defined internal HDL interfaces, the steps of designing the component-specific HDL interfaces and of setting the constants being performed contemporaneous ly .
18. A method as recited in claim 16, the selected pre-defined internal HDL interfaces having addresses that are specified in terms of constants that can be set by a designer after selecting the pre-defined internal HDL interfaces, the method further comprising a step of setting the constants in accordance with desired addresses of the internal HDL interfaces contemporaneously with designing the component-specific HDL interfaces.
19. A method as recited in claim 16, at least one of the selected predefined internal HDL interfaces specifying a DMA buffer size in terms of a constant that can be set by a designer after selecting the pre-defined internal HDL interface, the method further comprising a step of setting the constant depending on a desired size for a DMA buffer contemporaneously with designing the component-specific HDL interfaces.
20. A method as recited in claim 16, at least one of the selected predefined internal HDL interfaces specifying a hardware feature in terms of a constant that can be set by a designer after selecting the pre-defined internal HDL interface, the method further comprising a step of setting the constant depending on requirements of the plurality of discrete computer components contemporaneously with designing the component-specific HDL interfaces.
21. A method as recited in claim 16, at least one of the selected predefined internal HDL interfaces defining a multi-bit signal having a width that can be set by a designer after selecting the pre-defined internal HDL interface, the method further comprising a step of setting the width of the multi-bit signal depending on requirements of the plurality of discrete computer components contemporaneously with designing the component-specific HDL interfaces.
22. Component interface hardware designed in accordance with the steps of claim 16.
23. In a computer system, a method of designing component interface hardware between a plurality of discrete computer components comprising the following steps: selecting pre-defined internal HDL interfaces for respective discrete computer components, each pre-defined internal HDL interface being selected from a limited number of available pre-defined internal HDL interfaces for general kinds of computer components, the pre-defined internal HDL interfaces being accessible only within an integrated circuit, the pre-defined internal HDL interfaces specifying certain hardware elements in terms of constants that can be set by a designer after selecting the pre-defined internal HDL interfaces; designing component-specific HDL interfaces for connecting the individual discrete components to the selected pre-defined internal HDL interfaces; setting the constants depending on requirements of the respective discrete computer components; compiling the selected pre-defined internal HDL interfaces and the designed component-specific HDL interfaces to create a hardware configuration file.
24. A method as recited in claim 23, the step of setting the constants comprising a step of specifying a size of a DMA buffer.
25. A method as recited in claim 23, the step of setting the constants comprising a step of specifying addresses of the pre-defined internal HDL interfaces.
26. A method as recited in claim 23, the step of setting the constants comprising a step of specifying connections between the pre-defined internal HDL interfaces and the component-specific HDL interfaces.
27. A method as recited in claim 23, the step of setting the constants comprising a step of specifying widths of multi-bit signals defined by the pre-defined internal HDL interfaces.
28. A method as recited in claim 23, the step of setting the constants comprising a step of specifying widths of data channels defined by the pre-defined internal HDL interfaces.
29. Component interface hardware designed in accordance with the steps of claim 23.
30. In a computer system, a method of integrating a plurality of discrete computer components comprising the following steps: designing a limited number of available pre-defined internal HDL interfaces for general kinds of computer components, the pre-defined internal HDL interfaces being accessible only within an integrated circuit; selecting pre-defined internal HDL interfaces for respective discrete computer components from the limited number of available pre-defined internal HDL interfaces; designing component-specific HDL interfaces for connecting the individual discrete components to the selected pre-defined internal HDL interfaces, the component-specific HDL interfaces defining (a) external interface signals for connection to the discrete components, and (b) internal interface signals for connection to the selected pre-defined internal HDL interfaces; configuring component interface hardware based on the selected pre-defined internal HDL interfaces and the designed component-specific HDL interfaces.
31. A method as recited in claim 30, wherein the step of designing the limited number of available pre-defined internal HDL interfaces includes designing such interfaces for CPU and memory component kinds.
32. A method as recited in claim 30, wherein the step of designing the limited number of available pre-defined internal HDL interfaces includes designing such interfaces for CPU, memory, and register component kinds.
33. A method as recited in claim 30, wherein the step of designing the limited number of available pre-defined internal HDL interfaces includes designing such interfaces for CPU, memory, register, and master component kinds.
34. A method as recited in claim 30, wherein the step of designing the limited number of available pre-defined internal HDL interfaces includes designing such interfaces in a verbal hardware description language that can be converted to different physical designs that utilize alternative hardware components.
35. A method as recited in claim 30, wherein the configuring step comprises converting the selected pre-defined internal HDL interfaces and the component-specific HDL interfaces to an actual physical design for an integrated circuit. o
36. A method as recited in claim 30, wherein the configuring step comprises converting the selected pre-defined internal HDL interfaces and the component-specific HDL interfaces to an actual physical design for a programmable single-chip gate array.
37. A method as recited in claim 30, wherein the step of designing the limited number of available pre-defined internal HDL interfaces comprises: defining a multi-bit signal in a particular one of the pre-defined internal HDL interfaces; defining a width for the multi-bit signal in terms of a constant associated with the particular pre-defined internal HDL interfaces that can be set by a designer after selecting the particular pre-defined internal HDL interfaces.
38. A method as recited in claim 30, further comprising: defining a multi-bit signal in a particular one of the pre-defined internal HDL interfaces; defining a width constant that is associated with the pre-defined internal HDL interface to specify a width for the multi-bit signal; assigning a value to the width constant to specify a width for the multi-bit signal contemporaneously with designing the component-specific HDL interfaces.
39. A method as recited in claim 30, wherein the step of designing the limited number of available pre-defined internal HDL interfaces comprises: specifying a feature within a particular one of the pre-defined internal HDL interfaces in terms of a constant that can be set contemporaneously with designing the component-specific HDL interfaces. 56
40. A computer system comprising: a plurality of discrete computer components; an integrated circuit that interfaces between the discrete computer components; the integrated circuit having internal hardware interfaces corresponding to respective discrete computer components, the internal hardware interfaces being accessible only within the integrated circuit, the internal hardware interfaces being selected from a limited number of available pre-defined internal hardware interfaces for general kinds of computer components; the integrated circuit further including interconnection logic between the internal hardware interfaces; the integrated circuit further including component-specific hardware interfaces for connecting the individual discrete components to the selected pre-defined internal hardware interfaces, the component-specific hardware interfaces having (a) external interface signals connected to the discrete components, and (b) internal interface signals connected to the internal hardware interfaces; the component-specific hardware interfaces being designed individually for the different discrete computer components to interface the discrete components to the internal hardware interfaces.
41. A computer system as recited in claim 40, wherein the discrete computer components include a CPU and memory.
42. A computer system as recited in claim 40, wherein the discrete computer components include a CPU and memory, the limited number of available pre-defined internal interfaces including such interfaces for CPU component kinds and for memory component kinds.
43. A computer system as recited in claim 40, wherein the discrete computer components include a CPU, memory, and other components, the limited number of available pre-defined internal hardware interfaces including such interfaces for CPUs, memory, and register component kinds.
44. A computer system as recited in claim 40, wherein the discrete computer components include a CPU, memory, and other components, the limited number of available pre-defined internal hardware interfaces including such interfaces for CPUs, memory, register, and master component kinds.
45. A computer system as recited in claim 40, the internal hardware interfaces and the component-specific hardware interfaces being responsive to a common clock signal for data transfers between the internal hardware interfaces and the component-specific hardware interfaces.
46. A component interface between a plurality of discrete computer components, comprising: an integrated circuit; internal hardware interfaces corresponding to respective discrete computer components, the general hardware interfaces being accessible only within the integrated circuit, the internal hardware interfaces being selected from a limited number of available pre-defined internal hardware interfaces for general kinds of computer components; interconnection logic within the integrated circuit between the pre-defined internal hardware interfaces; component-specific hardware interfaces corresponding to respective discrete computer components, the component-specific hardware interfaces having (a) external interface signals for connection to the discrete computer components, and (b) internal interface signals connected to the internal hardware interfaces; the component-specific hardware interfaces being designed individually for the different discrete computer components to interface the discrete components to the internal hardware interfaces.
47. A component interface as recited in claim 46, the limited number of available pre-defined internal hardware interfaces including such interfaces for CPUs and memory.
48. A component interface as recited in claim 46, the limited number of available pre-defined internal hardware interfaces including such interfaces for CPUs, memory, and register component kinds.
49. A component interface as recited in claim 46, the limited number of available pre-defined internal hardware interfaces including such interfaces for CPUs, memory, register, and master component kinds.
50. A component interface as recited in claim 46, the internal hardware interfaces and the component-specific hardware interfaces being responsive to a common clock signal for data transfers between the internal hardware interfaces and the component-specific hardware interfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU32222/97A AU3222297A (en) | 1996-06-03 | 1997-05-28 | Hardware and software development in computer systems having multiple discrete components |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/659,084 US6058263A (en) | 1996-06-03 | 1996-06-03 | Interface hardware design using internal and external interfaces |
| US08/659,084 | 1996-06-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1997046959A1 WO1997046959A1 (en) | 1997-12-11 |
| WO1997046959B1 true WO1997046959B1 (en) | 1998-02-05 |
Family
ID=24643964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1997/009290 WO1997046959A1 (en) | 1996-06-03 | 1997-05-28 | Hardware and software development in computer systems having multiple discrete components |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6058263A (en) |
| AU (1) | AU3222297A (en) |
| WO (1) | WO1997046959A1 (en) |
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1996
- 1996-06-03 US US08/659,084 patent/US6058263A/en not_active Expired - Lifetime
-
1997
- 1997-05-28 AU AU32222/97A patent/AU3222297A/en not_active Abandoned
- 1997-05-28 WO PCT/US1997/009290 patent/WO1997046959A1/en active Application Filing
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