WO1997041594A1 - Multilayer solder/barrier attach for semiconductor chip - Google Patents
Multilayer solder/barrier attach for semiconductor chip Download PDFInfo
- Publication number
- WO1997041594A1 WO1997041594A1 PCT/US1997/007155 US9707155W WO9741594A1 WO 1997041594 A1 WO1997041594 A1 WO 1997041594A1 US 9707155 W US9707155 W US 9707155W WO 9741594 A1 WO9741594 A1 WO 9741594A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- solder
- attach
- layer
- layers
- electroplating
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13157—Cobalt [Co] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13164—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13169—Platinum [Pt] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13176—Ruthenium [Ru] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01044—Ruthenium [Ru]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0215—Metallic fillers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/1025—Metallic discs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/0415—Small preforms other than balls, e.g. discs, cylinders or pillars
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- This invention relates to structures and methods of forming an electrical, thermal or mechanical attachment between bodies which have different thermal coefficients of expansion
- This invention relates particularly to structures and methods of forming an electrical or thermal attachment between a semiconductor chip or package and a printed circuit board or other substrate
- PCBs printed circuit boards
- solder bumps or balls For example, in "flip-chip” bonding an array of solder bumps is formed on the front side of the chip The chip is then inverted and the solder bumps are heated (reflowed) to form a connection with pads on the PCB
- This structure provides a direct electrical connection which reduces noise and parasitics and increases speed as compared with, for example, the use of bonding wires to connect the chip and the PCB
- flip-chip bonding allows a better use ofthe available real estate on the PCB and eliminates the need for a separate chip package
- a ball grid array consisting of solder balls can be used to connect pads on an "interposer" placed between a semiconductor chip and a PCB with pads on the PCB
- solder bumps employed in flip-chip bonding and ball grid arrays are typically 125- 200 mm in diameter and are frequently formed by electroplating or evaporation
- a silicon chip has a thermal coefficient of expansion ( ⁇ ) of 2 6 x IO "6 in/in/°C while a PCB, for example, has an ⁇ of about 16 x IO '6 in/in/°C
- a C4 solder bump attach bonded to a copper substrate will last only about 100 thermal cycles (-60°C to 150°C).
- a connection between a first body such as a semiconductor chip and a second body such as a PCB is formed by a multilayer structure or stack which includes solder layers interleaved with barrier layers
- the solder layers are made sufficiently thin that a grain boundary sliding form of deformation occurs when the first and second bodies thermally expand or contract at different rates
- Grain boundary sliding predominates when the solder is finely grained and is distinguishable from matrix deformation, which occurs when the grains of solder are relatively large.
- Grain boundary sliding is damage-free and reversible, whereas matrix deformation is irreversible. Matrix deformation permanently damages the granular structure of the solder and ultimately impairs the integrity of the electrical connection
- solder layers thin creates a thin granular structure and promotes grain boundary sliding
- thinness ofthe solder layers restrains grain growth during thermal cycling, resulting in a stable fine-grained structure
- the solder layers are less than 50 mm thick and there are at least three solder layers in the stack
- the solder layers are separated by barrier layers which can include one or more layers or sublayers of Ni, Cu, Co, Pd, Pt or Ru
- barrier layers can include one or more layers or sublayers of Ni, Cu, Co, Pd, Pt or Ru
- the stack of solder and barrier layers is fabricated by electroplating Small sizes and shapes ofthe connections can be defined using photolithographic processes The applicability of this invention extends far beyond the formation of an array of electrical connections between the respective pads on semiconductor chips (or interposers) and PCBs.
- This invention can also be used, for example, as a means of attaching a broader area of a semiconductor chip to a heat sink
- the use of this invention provides dramatically increased thermal lifetimes
- Replacing a conventional solder bump with a stack containing three solder layers increases the estimated lifetime of the connection from 100 to 2500 thermal cycles. If the number of solder layers is increased to five, the estimated lifetime increases to 5000 thermal cycles or more
- Figs IA and IB illustrate top and side views, respectively, of an array of attach bumps in accordance with this invention
- Fig. IC illustrates a detailed view of one of the attach bumps
- Fig. 2A illustrates a side view of an attach bump containing three solder layers before reflow.
- Fig 2B illustrates a side view ofthe attach bump of Fig 2A after reflow.
- Fig. 3 illustrates a graph ofthe shear force versus strain rate for matrix deformation and for grain boundary sliding deformation in thick and thin solder layers
- Fig 4 illustrates a graph of the strain rate corresponding to the "knee" (shown in Fig 3) as a function of the thickness of the solder layer
- Fig. 5 illustrates a graph of the lifetime of a multilayer attach (in thermal cycles) as a function of the number of solder layers in the stack for solder layers of various thickness
- Fig. 6 is a detailed side view of an attach bump of this invention containing three solder layers.
- Fig 7 is a detailed side view of an attach bump of this invention containing two solder layers.
- Fig. 8 is a side view of an embodiment containing multilayer attach bumps in series with conventional solder balls
- Figs. IA and IB are top and side views, respectively, of a semiconductor chip 10 which contains an array of multilayer attach bumps 12 in accordance with this invention
- Fig I C is a detailed view of one of the attach bumps 12, which includes a solder layer 13, a Ni/Cu barrier layer 14 and a solder layer 15.
- Solder layer 15 is in electrical contact with a metal bus
- bump 12 contains two solder layers and an intervening barrier layer.
- Figs. 2A and 2B show an attach bump 21 containing three solder layers that is formed on a pad 202 of a semiconductor chip 20.
- Attach bump 21 includes solder layers 204, 208, 212 and intervening copper layers 206, 210. In Fig. 2 A, attach bump 21 has not yet been
- Fig. 2B shows attach bump 21 after it has been bonded to pad 214 by reflowing the solder layers 204, 208, 212. Also, as is apparent from Fig. 2B, pad 214 has been displaced laterally with respect to pad 202 as a result of differential thermal expansion between chip 20 and substrate 22. The lateral displacement of solder layers 204, 208, 212 is also apparent.
- Each of the solder layers in attach bumps 12 and 21 are preferably less than 50 mm thick. Keeping the solder layers below a thickness of 50 ⁇ m insures that the grains in the solder are small and that the predominant form of deformation as the chip and substrate are displaced laterally by temperature variations is grain boundary sliding deformation rather than matrix deformation.
- Fig. 3 illustrates a graph showing the lateral shear force applied to the solder as a function ofthe rate of deformation (strain rate).
- Curve 30 shows the force vs. strain rate for matrix deformation.
- Curve 31 shows the force vs. strain rate for grain boundary sliding deformation when the layer is relatively thick (150 ⁇ m), and curve 32 shows the force vs strain rate for grain boundary sliding deformation when the solder layer is relatively thin (50
- a “knee” for the "thick” solder layer indicated at 33 represents the intersection of curves 30 and 31, and a “knee” for the "thin” solder layer indicated at 34 represents the intersection of curves 30 and 32.
- a thin solder layer cools more rapidly than a thick solder layer, resulting in a higher grain boundary density which shifts the knee to higher strain rates
- a differential thermal expansion which produces a shear force of Fj 125 results in a strain rate of Ai from grain boundary sliding deformation in a thin solder layer and a strain rate of A 2 from matrix deformation. Since the intersection with curve 32 is below the knee 34, A 2 is almost two orders of magnitude below Aj. Thus the predominant form of deformation in a thin solder layer is grain boundary sliding. In contrast, with a thick solder layer the point at which force Fi intersects curve 3 1 (dashed line) yields a strain rate of A 3 for 130 grain boundary sliding deformation. The strain rate for matrix deformation remains at A 2 since the relationship of strain rate and force for matrix deformation is independent ofthe thickness ofthe solder layer Since the intersection with curve 31 is above knee 33, A 2 is somewhat greater than Ai, and matrix deformation predominates
- the grains in a thin solder layer are much smaller than those in a thick solder layer, and 150 this explains the predominance of grain boundary sliding deformation in the thin layer Grain boundary sliding deformation is essentially "damage free" In contrast, matrix deformation generates voids, cracking and ultimate fracture from the dislocation climb process Moreover, the smaller grains in the thin solder layer recrystahze into small grains during thermal cycling Grain growth is inhibited Thus the thin solder layer insures that the grains are small initially 155 and insures that the small grain size is maintained thereby promoting a lower damage rate
- Fig 4 illustrates a graph showing the experimentally determined location of the "knee" as a function ofthe thickness ofthe solder layer As indicated, the knee shifts upward by 2 to 3 orders of magnitude as the layer thickness decreases from about 200 ⁇ m to about 75 ⁇ m
- Fig 5 is a graph showing the lifetime of an attach bump as a function of both the 160 thickness of the solder layers and the number of solder layers in the stack The lifetime is represented as the number of thermal cycles (-40°C to 140°C) at which failure occurs For the 175 ⁇ m thick layer attach, the lifetime increases only linearly with the number of layers in the attach, increasing only from 50 to 200 thermal cycles (for a four-layer attach).
- the multilayer structure of this invention is fabricated by electroplating a succession of solder and barrier layers.
- the locations ofthe attach bumps can be defined using 170 conventional photolithographic techniques Fig. IC, for example, shows a photoresist layer 18 (dashed lines) which is used as a mask to define the location of attach bump 12. It may be necessary also to etch an opening in a passivation layer to expose the metal bus or other metal layer to which the attach bump is to be connected.
- a multilayer laminate of solder and barrier layers can be plated initially and then etched to form the desired attach 175 bumps.
- a three solder layer attach bump 60 is formed on a silicon die 61, which is typically part of a silicon wafer Initially a TiW or TiCr adhesion/barrier layer 62 is sputtered onto the surface of silicon chip 61 Layer 62 can be in the range of 100-500 nm thick. This is followed by sputtering a 500 nm thick copper seed layer 63 180 This completes the preliminary processing of the silicon chip 61 Next a 2 ⁇ m copper layer 64 is electroplated using a sulfate solution This is followed by electroplating a 2 ⁇ m nickel layer 65 (high tin content solder) and another 2 ⁇ m copper layer 66, which is also electroplated using a sulfate solution
- solder layer 67 is electroplated using an acid solution (e g , 185 sulfonic acid). 60/40 solder is preferred because it exhibits the grain boundary sliding mode of deformation for fine grained structures.
- a 1 ⁇ m thick copper strike or adhesion layer 68 is electroplated using a copper cyanide solution before the next copper layer is plated.
- a copper layer 64A, a nickel layer 65A and a copper layer 66A are electroplated Layers 64A-66A are similar to layers 64- 190 66
- a third solder layer is then formed by electroplating layers 64B-67B which are similar to layers 64-67, respectively
- solder layers 67, 67A and 67B are then heated to a temperature in the range of 220°C to reflow the solder Normally, no sidewalls or other mechanical restraints are needed to confine or support the solder during reflow This produces a fine-grained solder and improves the intermetallic bonding between the solder and adjacent layers
- silicon chip 61 is diced from other chips on the wafer Chip 61 is loaded in a flip-chip bonder and aligned with a metal substrate interconnect 69, which could be a metal pad Conventional tests are then performed to verify the electrical and mechanical integrity ofthe connection between silicon chip 61 and metal substrate interconnect 69.
- layers 64-66 and 68, 64A-66A and 68A, and 64B, 66B are barrier layers.
- the barrier layers include copper and nickel layers, but in other embodiments one or more members ofthe group consisting of Co, Pd, Pt and Ru can be used in the barrier layers in addition to or substitution for the copper and nickel layers
- Attach bump 60 shown in Fig 6 has an estimated lifetime of 2500 thermal cycles
- Fig 7 shows a two-solder-layer attach bump 70 including a TiW or TiCr layer 72 and a copper seed layer 73 which are electroplated on a silicon chip 71
- Layers 72 and 73 are similar to layers 62 and 63 shown in Fig 6
- layers 74-77 are similar to layers 74A-77A and correspond to layers 64-67 shown in Fig 6
- the electroplated structure is reflow bonded to a metalized substrate such as metal pad 69
- the electroplated structure can be bonded to a leadframe or heat sink
- the multilayer attach has an estimated lifetime of 750 thermal cycles
- An attach bump in accordance with this invention can be used in other situations such as the one shown in Fig 8
- a ceramic chip carrier 81 is connected to metal pads 82 on a PCB 83 via conventional solder ball joints 84 in series with five-layer attach bumps 85
- the solder layers in attach bumps 85 are 50 ⁇ m thick and are separated by copper or nickel barrier layers Whereas a single solder layer 150-250 ⁇ m thick has an experimental lifetime of only 50 thermal cycles the five-layer attach bumps 85 have a calculated lifetime of at least 5000 thermal cycles
- a multilayer laminate structure containing solder and barrier layers can also be used to attach a chip to, for example, a heat sink
- a single thick solder layer e g , 100 ⁇ m
- the thermal lifetime increases by a factor of two. Reducing the thickness to 25 ⁇ m increases the thermal lifetime by a factor of 4-5 As described above, it is the predominance of grain boundary sliding deformation in thin solder layers that accounts for this four- or fivefold improvement in lifetime.
- the operating strain rate is equal to ⁇ x ( l ⁇ chip dimension/h) x ⁇ T/ ⁇ t, where ⁇ is the difference in the thermal coefficient of expansion between the chip and the substrate, h is the height of the solder joint, and ⁇ T/ ⁇ t is the maximum temperature rate of change.
- the damage rate i.e., the maximum matrix strain rate in a thermal cycle
- the damage rate decreases by a power of 3 as the number of solder layers increases
- Multilayer attaches in accordance with this invention can also be used for attaching semiconductor chips to a substrate in chip-on-glass (COG) flat panel displays. This permits a
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU29278/97A AU2927897A (en) | 1996-04-29 | 1997-04-29 | Multilayer solder/barrier attach for semiconductor chip |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US1643096P | 1996-04-29 | 1996-04-29 | |
US60/016,430 | 1996-04-29 | ||
US84558297A | 1997-04-25 | 1997-04-25 | |
US845,582 | 1997-04-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997041594A1 true WO1997041594A1 (en) | 1997-11-06 |
Family
ID=26688587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/007155 WO1997041594A1 (en) | 1996-04-29 | 1997-04-29 | Multilayer solder/barrier attach for semiconductor chip |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU2927897A (en) |
WO (1) | WO1997041594A1 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0921716A1 (en) * | 1997-12-04 | 1999-06-09 | Ford Global Technologies, Inc. | Reinforced solder joints for printed circuit boards |
US6893799B2 (en) | 2003-03-06 | 2005-05-17 | International Business Machines Corporation | Dual-solder flip-chip solder bump |
US6897123B2 (en) | 2001-03-05 | 2005-05-24 | Agityne Corporation | Bonding of parts with dissimilar thermal expansion coefficients |
US8348139B2 (en) | 2010-03-09 | 2013-01-08 | Indium Corporation | Composite solder alloy preform |
WO2013016276A3 (en) * | 2011-07-26 | 2013-04-11 | Fujitsu Limited | Hybrid interconnect technology |
WO2013147808A1 (en) * | 2012-03-29 | 2013-10-03 | Intel Corporation | Functional material systems and processes for package-level interconnects |
IT201800009071A1 (en) * | 2018-10-01 | 2020-04-01 | Rise Tech Srl | Realization of multi-component structures through dynamic menisci |
WO2021103489A1 (en) * | 2019-11-29 | 2021-06-03 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
DE102012216546B4 (en) | 2012-09-17 | 2023-01-19 | Infineon Technologies Ag | METHOD OF SOLDERING A SEMICONDUCTOR CHIP TO A CARRIER |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1987000686A1 (en) * | 1985-07-16 | 1987-01-29 | Nippon Telegraph And Telephone Corporation | Connection terminals between substrates and method of producing the same |
US5130779A (en) * | 1990-06-19 | 1992-07-14 | International Business Machines Corporation | Solder mass having conductive encapsulating arrangement |
JPH0684916A (en) * | 1992-08-31 | 1994-03-25 | Tanaka Kikinzoku Kogyo Kk | Multilayer bump |
US5449955A (en) * | 1994-04-01 | 1995-09-12 | At&T Corp. | Film circuit metal system for use with bumped IC packages |
-
1997
- 1997-04-29 AU AU29278/97A patent/AU2927897A/en not_active Abandoned
- 1997-04-29 WO PCT/US1997/007155 patent/WO1997041594A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1987000686A1 (en) * | 1985-07-16 | 1987-01-29 | Nippon Telegraph And Telephone Corporation | Connection terminals between substrates and method of producing the same |
US5130779A (en) * | 1990-06-19 | 1992-07-14 | International Business Machines Corporation | Solder mass having conductive encapsulating arrangement |
JPH0684916A (en) * | 1992-08-31 | 1994-03-25 | Tanaka Kikinzoku Kogyo Kk | Multilayer bump |
US5449955A (en) * | 1994-04-01 | 1995-09-12 | At&T Corp. | Film circuit metal system for use with bumped IC packages |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0921716A1 (en) * | 1997-12-04 | 1999-06-09 | Ford Global Technologies, Inc. | Reinforced solder joints for printed circuit boards |
US6897123B2 (en) | 2001-03-05 | 2005-05-24 | Agityne Corporation | Bonding of parts with dissimilar thermal expansion coefficients |
US6893799B2 (en) | 2003-03-06 | 2005-05-17 | International Business Machines Corporation | Dual-solder flip-chip solder bump |
US8348139B2 (en) | 2010-03-09 | 2013-01-08 | Indium Corporation | Composite solder alloy preform |
JP2014527294A (en) * | 2011-07-26 | 2014-10-09 | 富士通株式会社 | Composite interconnect technology |
WO2013016276A3 (en) * | 2011-07-26 | 2013-04-11 | Fujitsu Limited | Hybrid interconnect technology |
US8633592B2 (en) | 2011-07-26 | 2014-01-21 | Cisco Technology, Inc. | Hybrid interconnect technology |
CN103548028A (en) * | 2011-07-26 | 2014-01-29 | 富士通株式会社 | Hybrid interconnect technology |
US9024453B2 (en) | 2012-03-29 | 2015-05-05 | Intel Corporation | Functional material systems and processes for package-level interconnects |
US20140225265A1 (en) * | 2012-03-29 | 2014-08-14 | Rajen S. Sidhu | Functional material systems and processes for package-level interconnects |
WO2013147808A1 (en) * | 2012-03-29 | 2013-10-03 | Intel Corporation | Functional material systems and processes for package-level interconnects |
DE102012216546B4 (en) | 2012-09-17 | 2023-01-19 | Infineon Technologies Ag | METHOD OF SOLDERING A SEMICONDUCTOR CHIP TO A CARRIER |
IT201800009071A1 (en) * | 2018-10-01 | 2020-04-01 | Rise Tech Srl | Realization of multi-component structures through dynamic menisci |
WO2020070635A1 (en) * | 2018-10-01 | 2020-04-09 | Rise Technology S.R.L. | Making multi-component structures with dynamic menisci |
CN113166963A (en) * | 2018-10-01 | 2021-07-23 | Rise技术有限责任公司 | Making multicomponent structures by dynamic meniscus |
US11795562B2 (en) | 2018-10-01 | 2023-10-24 | Rise Technology S.R.L. | Making multi-component structures using dynamic menisci |
WO2021103489A1 (en) * | 2019-11-29 | 2021-06-03 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
US20220115352A1 (en) * | 2019-11-29 | 2022-04-14 | Changxin Memory Technologies, Inc. | Semiconductor Structure And Manufacturing Method Thereof |
EP3940772A4 (en) * | 2019-11-29 | 2022-07-13 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method therefor |
US11855032B2 (en) | 2019-11-29 | 2023-12-26 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
AU2927897A (en) | 1997-11-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6333563B1 (en) | Electrical interconnection package and method thereof | |
US7314817B2 (en) | Microelectronic device interconnects | |
US5542174A (en) | Method and apparatus for forming solder balls and solder columns | |
US6696757B2 (en) | Contact structure for reliable metallic interconnection | |
US5912505A (en) | Semiconductor package and semiconductor device | |
US6118179A (en) | Semiconductor component with external contact polymer support member and method of fabrication | |
US7745736B2 (en) | Interconnecting substrate and semiconductor device | |
US6864165B1 (en) | Method of fabricating integrated electronic chip with an interconnect device | |
US6919642B2 (en) | Method for bonding IC chips to substrates incorporating dummy bumps and non-conductive adhesive and structures formed | |
JP3262497B2 (en) | Chip mounted circuit card structure | |
US5956606A (en) | Method for bumping and packaging semiconductor die | |
US7081405B2 (en) | Package module for an IC device and method of forming the same | |
US20060201997A1 (en) | Fine pad pitch organic circuit board with plating solder and method for fabricating the same | |
US20020171152A1 (en) | Flip-chip-type semiconductor device and manufacturing method thereof | |
JP5208500B2 (en) | Assembling method and assembly produced by this method | |
US20080119029A1 (en) | Wafer scale thin film package | |
US8394672B2 (en) | Method of manufacturing and assembling semiconductor chips with offset pads | |
US20030102156A1 (en) | Ball grid array package | |
EP0908951B1 (en) | Improved air isolated crossovers | |
US6392291B1 (en) | Semiconductor component having selected terminal contacts with multiple electrical paths | |
EP0852395A3 (en) | Method of multiplexed joining of solder bumps to a substrate during assembly of an integrated circuit package | |
WO1997041594A1 (en) | Multilayer solder/barrier attach for semiconductor chip | |
US6559388B1 (en) | Strain relief for substrates having a low coefficient of thermal expansion | |
US20040217482A1 (en) | Structure and method for low-stress concentration solder bumps | |
CN102473591A (en) | Interconnect assemblies and methods of making and using same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG UZ VN YU AM AZ BY KG KZ MD RU TJ TM |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
NENP | Non-entry into the national phase |
Ref country code: JP Ref document number: 97539147 Format of ref document f/p: F |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
NENP | Non-entry into the national phase |
Ref country code: CA |
|
122 | Ep: pct application non-entry in european phase |