WO1997039477A1 - Formation de carbure de silicium de type p par implantation ionique et carbure de silicium de type p - Google Patents

Formation de carbure de silicium de type p par implantation ionique et carbure de silicium de type p Download PDF

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Publication number
WO1997039477A1
WO1997039477A1 PCT/US1997/006116 US9706116W WO9739477A1 WO 1997039477 A1 WO1997039477 A1 WO 1997039477A1 US 9706116 W US9706116 W US 9706116W WO 9739477 A1 WO9739477 A1 WO 9739477A1
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Prior art keywords
silicon carbide
implanted
room temperature
semiconductor
sic semiconductor
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PCT/US1997/006116
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English (en)
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Jian H. Zhao
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Rutgers, The State University
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Priority to AU24589/97A priority Critical patent/AU2458997A/en
Publication of WO1997039477A1 publication Critical patent/WO1997039477A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
    • C30B31/20—Doping by irradiation with electromagnetic waves or by particle radiation
    • C30B31/22—Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide

Definitions

  • the present invention relates to novel and improved methods of forming novel p-type silicon carbide with high uniformity, reproducibility, and crystal and electrical quality.
  • Semiconductors are materials generally defined as having electrical conductivities somewhere between the high conductivity characteristics of metals and the low conductivity characteristics of insulators. Since the invention of the transistor, the development of electrical devices based on semiconductors has revolutionized the electronics industry.
  • GaAs gallium arsenide
  • InP indium phosphide
  • silicon carbide Another material which has generated much interest, but for which limited success in producing practical crystals and devices has been achieved, is silicon carbide (SiC).
  • SiC silicon carbide
  • silicon carbide remains stable at temperatures approaching 2800°C. Fundamentally, this means that silicon carbide can exist as a solid at extremely high temperatures at which silicon and silicon based electronic devices would not only be useless, but would also be completely destroyed.
  • silicon carbide has a relatively wide band gap, (i.e. the energy difference between its valence and conduction bands), of approximately 2.2 electron volts (eV) (beta) or 3.0 (eV) (6H - alpha). This is a rather large gap in comparison to that of silicon (1.1 eV) and means that electrons will have less tendency to move from the valence band to the conduction band solely on the basis of thermal excitation. In practical terms, this allows for silicon carbide-based devices to operate at higher temperatures than the equivalent silicon-based devices.
  • silicon carbide has a high thermal conductivity, a low dielectric constant, a high breakdown electric field, and a high saturated electron drift velocity. These characteristics mean that, at high electric field levels, devices made from silicon carbide can perform at higher speeds than devices made from any of die other conventional semiconductor materials. Because of these inherent characteristics, silicon carbide has been a principal and perennial candidate material for applications having high temperature, high power, and high speed requirements.
  • Electrons are one of the fundamental subatomic particles carrying negative charge, while "holes" represent an energy level position within an atom where an electron could be placed, but for some reason is temporarily or permanently absent. Because holes are left behind when electrons move, holes can also be thought of as moving from place to place and as carrying a positive charge.
  • silicon carbide both the silicon atoms and the carbon atoms have the same number of valence electrons.
  • the greater conductivity results from one of two phenomena: Using nitrogen, for example, which has five valence electrons, the presence of nitrogen atoms in a silicon carbide crystal provides a number of extra electrons which would not be present in a purer silicon carbide crystal. These extra electrons can be encouraged to move from the mtrogen atoms to empty electron positions in the silicon or carbon atoms, resulting in a flow of current. Conversely, using aluminum, which has three valence electrons, the presence of the aluminum atoms in the silicon carbide crystal provides available electron positions into which other electrons can move from the silicon or carbon atoms, and thereby carry current by the movement of "holes" .
  • doping By doping a semiconductor material such as silicon carbide wim either atoms with more valence electrons such as nitrogen (n-type doping) or fewer valence electrons, such as aluminum (p-type doping), a semiconductor material can result which has certain specific electrical characteristics, and tiirough which current can be made to flow under particular controlled conditions. Such materials can be fabricated into devices of many types, common examples of which are diodes, capacitors, junction transistors, and field effect transistors, all of which in turn can be built into circuits and more complicated devices.
  • an appropriate semiconductor material must by available, often in the form of a single crystal or a monocrystalline thin film; second, the ability must exist to dope the semiconductor material in the desired manner; and third, proper techniques must be developed for forming devices from the doped materials. Accordingly, much interest, research, publication activity, and indeed patent literature, has been directed at producing silicon carbide, doping it, and manufacturing devices from it. In spite of this high level of attention, commercial devices formed from silicon carbide have to date failed to move beyond the literature or the research lab into the commercial marketplace.
  • ions of the dopant atoms are formed by any appropriate method, for example by application of a strong enough field to strip one or more electrons from each dopant atom.
  • the ions are then accelerated, typically through a mass spectrometer to further separate and accelerate the desired dopant atoms, and finally directed into a target material (usually a single crystal or monocrystalline thin film) at energies typically between about 50 and about 300 kilo electron volts (KeV).
  • a target material usually a single crystal or monocrystalline thin film
  • the dopant ions may not be in positions at which electrons and holes can be transferred, i.e. they are not yet "electrically activated.”
  • a great deal of damage to the target crystal results.
  • atoms in the crystal lattice are dislodged from their proper positions to a greater or lesser extent.
  • such damaged crystals often do not have the electrical properties required for useful semiconductor devices. Accordingly, various attempts and techniques have been developed for dealing with the damage done during implantation.
  • a first technique is to heat or anneal the doped substrate material following implantation.
  • This heating step when followed by an appropriate rate of cooling, should theoretically encourage the atoms in the crystal lattice, most of which are atoms of the semiconductor, to recrystallize in an orderly fashion.
  • This process repairs the damage to the semiconductor crystal lattice and allows the dopant atoms to position themselves for electrical activation.
  • Other researchers have attempted to raise the temperature of the target during implantation, an example of which is U.S. Pat. No. 3,293,084 to McCaldin (Dec. 20, 1966), which discusses ion implantation of silicon, germanium, silicon, and germanium alloys with sodium, potassium, rubidium, or cesium as the doping atom.
  • analytical tools such as transmission electron microscopy (TEM) and deep level transient spectroscopy (DLTS) were unavailable and the residual defects formed under these conditions remained undiscovered.
  • TEM transmission electron microscopy
  • DLTS deep level transient spectroscopy
  • a further aspect of the invention provides novel p-type silicon carbide having activation efficiencies of 3%, 10%, 20%, 30%, 40%, or 50% or more. Still higher activation efficiencies, desirably above about 80% and most desirably above about 90%, are achievable.
  • a further aspect of the invention provide the p-type silicon carbide with hole mobility greater than 1, cm /V sec at room temperature, and more preferably with higher hole mobility, i.e., above about 5; above about 10, above about 20, above about 40, above about 80 and most desirably 160 cm /V sec at room temperature.
  • Yet another aspect of the invention provides the p-type silicon carbide with hole concentration greater than IO 16 /cm 3 at room temperature, and more
  • the most preferred p-doped SiC materials according to the invention combine all of the desirable attributes, and provide high hole concentration, high hole mobility and high activation efficiency as aforesaid.
  • One aspect of the present invention uses ion implantation to create a large amount of vacancies favorable to acceptor activation in the silicon carbide lattice before p-type acceptor ion implantation is performed.
  • carbon ion implantation will create a large amount of silicon vacancies (i.e., vacancies at sites which would be occupied by silicon) and aluminum or boron ions can be used for p-type acceptor ion implantation.
  • a desired method of producing a p-doped region of silicon carbide suitable for semiconductor electronic devices comprises the following steps: a) directing a first ion beam onto a silicon carbide substrate to create vacancies favorable to acceptor activation; b) directing a second ion beam onto said silicon carbide substrate, said second ion beam consisting of p-type acceptor atoms and having an atomic concentration per cubic centimeter in about the same range as the atomic concentration per cubic centimeter of said first ion beam, to form an implanted silicon carbide structure; and c) annealing said implanted silicon carbide structure in an inert gas or vacuum environment at about between 1000°C to 1700°C.
  • the first ion implantation beam is carbon and the second ion implantation beam consists of aluminum or boron.
  • the implanted silicon carbide structure is annealed in a high purity silicon carbide crucible or other non-contaminating compartment, filled with silicon carbide powder.
  • the implanted silicon carbide structure is disposed in intimate contact with another silicon carbide structure.
  • a silicon carbide crystal may overly the surface of the implanted silicon carbide during the annealing step.
  • the ion implantation steps can be performed at temperatures ranging from between about -200° C to 1500° C, including room temperature.
  • temperatures ranging from between about -200° C to 1500° C, including room temperature.
  • conducting one or, most preferably, both of the ion implantation stages at elevated temperatures desirably above about 300°C; more desirably above about 450 °C and most desirably at about 600 °C or more, results in a doped crystal with enhanced properties, including enhanced hole mobility. This indicates that the degree of damage to the crystal structure occurring during implantation is reduced by conducting the implantation at elevated temperatures.
  • the ion implantation stages can be conducted at about room temperature or slightly above room temperature, such as at about 100°C to about 300°C, which provides less enhancement of the properties than implantation at higher temperatures.
  • the annealing temperature may be between about 1000°C and about 1600°C, such as between about 1400°C and 1500°C, but more preferably the annealing temperature is between about 1550°C and 1700°C, most preferably around 1650°C.
  • Fig. 1 is a cross-sectional illustration of the first critical step of implantation of ions to create vacancies favorable to acceptor activation, in this case C, into either n or p type SiC mounted on a temperature-controlled sample holder.
  • Fig. 2 shows the second step of co-implantation of p-type acceptor atoms, in this case Al or B, having a similar atomic concentration per cubic centimeter to that of C.
  • the Al or B ions are implanted into the same region which was implanted by C and may be performed at similar or different temperatures.
  • the annealing temperature and time depend on the dose and depth and can be from 1,000° C to over 1600° C and last from a few seconds to a few hours.
  • Figure 3(a) shows the typical current-voltage relations for C and Al co-implanted 6H-SiC and Al implanted 6H-SiC measured using the transmission line model (TLM) structure shown in Fig.3(b) wherein ohmic contacts are formed on the implanted and annealed surface with various spacings between the metal contacts.
  • Figure 4 shows the resistance between each pair of the ohmic contacts plotted as a function of the spacing between the ohmic contacts for 6H-SiC implanted by Al only at 600°C.
  • the sheet resistance and resistivity of the implanted SiC are determined by the intercept (8.4 k-ohm in this illustration) and the slope (615 ohm/cm in this illustration).
  • Figure 5 shows the resistance between each pair of the ohmic contacts plotted as a function of the spacing between the ohmic contacts for 6H-SiC implanted by C then Al at room temperature.
  • the sheet resistance and resistivity of the implanted SiC are determined by the intercept (0.3 k- ohm in this illustration) and the slope (100 ohm/cm in this illustration).
  • Figure 6 is a diagrammatic sectional view depicting an annealing chamber and silicon carbide wafers utilized. BEST MODE OF CARRYING OUT INVENTION
  • a 6H-SiC sample with 10 micron epilayer of n 1 x IO 16 cm "3 on heavily doped n-type 6H-SiC substrate (off-axis, 3.5° ⁇ _ 0.5° off ⁇ 0001 ⁇ toward ⁇ 1120> , purchased from Cree Research, Inc., Durham, N.C.) was used as a starting wafer.
  • the sample was cut into two pieces of equal size. One of them was used as a control sample, i.e., implanted by Al only, and is referred to here as No. 5.
  • the other piece, referred to here as No. 6, was first implanted with C and then Al according to the technique of the present invention using a Veeco implantor.
  • Sample No.5 was implanted by Al-27 ions at 600° C using multiple doses and energies of 5.00 x 10 15 cm '2 at 196keV, 1.96 x 10 15 cm '2 at 118 keV, 1.00 x IO 15 cm “2 at 118keV, 1.00 x 10 15 cm “2 at 74 keV, and 4.95 x IO 14 cm “2 at 50keV. 600°C implantation was used because at lower implantation temperatures, too much damage may be generated in the substrate and the Al activation efficiency may be too low to be measured reliably.
  • Sample No. 6 was first implanted by C-12 at room temperature to create Si vacancies and the desired damage level so that the Al atoms, which will be implanted next, can more easily fill the Si vacancies that are created.
  • the doses and energies for the C-12 implantation were 3.18 x IO 15 cm “2 at 122keV, 1.75 x IO 15 cm “2 at 75keV, 1.31 x 10 15 cm “2 at 43keV, and 9.21 x IO 14 cm 2 at 20keV.
  • Al-27 at room temperature The Al-27 multiple doses and energies used were identical to the ones used for sample No. 5 for ease of comparison between the samples.
  • the uniformly implanted profile had a depth of 2,200
  • the implanted samples are then placed into a high purity graphite compartment filled with high purity SiC powder and loaded into a high temperature furnace which is pumped to IO "3 Torr and annealed for 30 minutes at 1,500°C.
  • Transmission Line Model measurement (TLM) pattern as shown in Fig. 3(b) are then fabricated onto the implanted surface for electrical evaluation by using standard photolithography techniques.
  • the metal used for the contact is Al and is deposited onto SiC by e-beam evaporation at a base pressure of 4 x 10 " Torr.
  • the stripe length is 150 microns and the width is 60 microns.
  • the Al contacts were then annealed at 950°C for 5 minutes in Ar ambient.
  • Fig. 3(a) shows a typical I-V characteristics between the patterns separated by 20 microns for samples No. 5 and No. 6. It shows that even for room temperature implantation, the C plus Al co-implantation technique of this invention results in a dramatically reduced resistance in comparison to just Al implantation done at 600°C .
  • the sheet resistance Rg is determined to be 92.3 k-ohm/square for sample No. 5 and 15k-ohm/square for sample No. 6.
  • the specific contact resistivity c is found to be 4.3 x 10 " ohm-cm for sample No. 5 and 3.4 x IO "4 ohm-cm 2 for sample No.6.
  • the C co- implantation technique of this method dramatically reduces the specific contact resistivity by a factor of 252.
  • the resistivity of implanted material is equal to
  • This mobility value is consistent with those reported values for Al- doped 6H-SiC grown by CVD as summarized in the article "SiC devices: physics and numerical simulation" by M.Ruff et al. in IEEE Trans, on
  • the annealing steps desirably are perfo ⁇ ned using a physical arrangement as shown in Fig. 6.
  • the annealing apparatus includes a base 10 and lid 12, both formed from silicon carbide or graphite, which cooperatively define an enclosed chamber.
  • Base 10 defines an inner compartment 14, a partition wall 16 surrounding inner compartment 14; an outer compartment 18 surrounding the inner compartment and an outer wall 20 surrounding outer compartment 18.
  • the outer wall defines a shoulder 22 higher than the top of partition wall 16. Lid 12 rests on shoulder 22 and covers both compartments, but does not seal the compartments from one another.
  • the implanted SiC wafers 24 are stacked within inner compartment 14 together with unimplanted, high-purity sacrificial SiC wafers 26 so that each implanted wafer 24 is closely covered by a surface of a sacrificial wafer 26.
  • the wafers are stacked in alternating order, so that each implanted wafer lies between two sacrificial wafers, but this is not essential.
  • the implanted surface of each implanted wafer should be in contact with another high-purity sacrificial SiC wafer.
  • the contacting surfaces are flat so that the contacting surfaces are intimately engaged with one another.
  • each implanted wafer may be in contact with the implanted surface of another implanted wafer, so that the bottom surface of each implanted wafer acts as a sacrificial surface for the neighboring wafer.
  • the outer compartment 18 is filled with a high-purity sacrificial SiC powder 30.
  • the powdered SiC may be replaced by other forms of SiC having relatively large surface area as, for example, whiskers or fibers of SiC, or a rough-surfaced SiC article.
  • the total exposed surface area of the sacrificial SiC powder and sacrificial SiC wafer surfaces exposed within the enclosed chamber is greater than the surface area of the implanted wafer surfaces.
  • EXAMPLE 2 A 6H-SiC sample that has the same epilayer structure and doping concentration as the starting wafer discussed in Example 1, , was used for this experiment to compare the hole mobilities in sample implanted at 600C and room temperature with the same does of C and Al at die same energies. The starting SiC sample was cut into two pieces.
  • the first pieces was implanted at 600C and the second piece was implanted at room temperature, both with multiple doses and energies of lxlO 16 cm “2 at 196 keV, 4xl0 15 cm '2 at 115 keV, 2.3xl0 15 cm '2 at 65 keV for Al and 6.3xl0 15 cm “2 at 122 keV, 3.4xl0 15 cm “2 at 80 keV, 2.6xl0 15 cm “2 at 52 keV, and 1.9xl0 15 cm “2 at 30 keV for C.
  • C-12 ions were implanted first followed by Al-27. The uniformly implanted profile had a depth of around 2.200 Angstroms.
  • the samples were annealed in apparatus as shown in Fig. 6.
  • the implanted samples were covered first by high quality p-type 6H-SiC wafers and then loaded into the high purity graphite inner compartment 14 with the outer compartment IB filled with high purity SiC powder.
  • the rest of the experimental procedure is the same as that described in Example 1.

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Abstract

L'invention concerne l'implantation ionique de carbure de silicium (SiC) à l'aide de quantités à peu près égales d'ions de type C et d'un accepteur de type p, tel que A1 ou B, afing de créer des semi-conducteurs au silicium monocristallin de SiC dopé de type p présentant une grande uniformité, une reproductibilité, des propriétés propres au cristal et des propriétés électriques. De plus, grâce à ce procédé, des connexions conductrices excellentes peuvent être formées sur la couche de SiC dopé p. Ce procédé d'implanation permet de créer et de fabriquer à la fois des composants SiC discrets et des composants de circuits intégrés.
PCT/US1997/006116 1996-04-16 1997-04-14 Formation de carbure de silicium de type p par implantation ionique et carbure de silicium de type p WO1997039477A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU24589/97A AU2458997A (en) 1996-04-16 1997-04-14 P-type silicon carbide formation by ion implantation and p-type silicon carbide

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US63286696A 1996-04-16 1996-04-16
US08/632,866 1996-04-16

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999044225A1 (fr) * 1998-02-27 1999-09-02 Daimlerchrysler Ag Procede pour produire un composant microelectronique a semiconducteur
EP2117036A1 (fr) * 2007-12-12 2009-11-11 Sumitomo Electric Industries, Ltd. Dispositif semi-conducteur et son procédé de fabrication
JP2010239152A (ja) * 2010-06-23 2010-10-21 Mitsubishi Electric Corp 炭化珪素半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5318915A (en) * 1993-01-25 1994-06-07 North Carolina State University At Raleigh Method for forming a p-n junction in silicon carbide

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5318915A (en) * 1993-01-25 1994-06-07 North Carolina State University At Raleigh Method for forming a p-n junction in silicon carbide

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
J. APPLN. PHYS., Vol. 77, No. 6, 3/95, RAO et al., "Al and B Ion-Implantations in 6H- and 3C-SiC", pp. 2479-2485. *
JOURNAL OF ELECTRONIC MATERIALS, Vol. 25, No. 1, 1996, RAO et al., "Al, Al/C and Al/Si Implantations in 6H-SiC", pp. 75-80. *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999044225A1 (fr) * 1998-02-27 1999-09-02 Daimlerchrysler Ag Procede pour produire un composant microelectronique a semiconducteur
US6383902B1 (en) 1998-02-27 2002-05-07 Daimlerchrysler Ag Method for producing a microelectronic semiconductor component
EP2117036A1 (fr) * 2007-12-12 2009-11-11 Sumitomo Electric Industries, Ltd. Dispositif semi-conducteur et son procédé de fabrication
EP2117036A4 (fr) * 2007-12-12 2012-02-08 Sumitomo Electric Industries Dispositif semi-conducteur et son procédé de fabrication
US8697555B2 (en) 2007-12-12 2014-04-15 Sumitomo Electric Industries, Ltd. Method of producing semiconductor device and semiconductor device
JP2010239152A (ja) * 2010-06-23 2010-10-21 Mitsubishi Electric Corp 炭化珪素半導体装置

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