WO1997024651B1

WO1997024651B1 - Lns-based computer processor and method of use thereof

Info

Publication number: WO1997024651B1
Application number: PCT/US1996/019011
Authority: WO
Filing date: 1996-11-27
Publication date: 1997-08-07

Abstract

An LNS-based computer processor is provided for performing high-speed calculations that involve special function values. Special functions include transcendental and hyperbolic functions. The computer processor includes a decoder (11), a memory circuit (12) for storing a plurality of special function signals, a log converter (14), at least one processing element (16), and an inverse-log converter (18).

Claims

AMENDED CLAIMS

[received b\ the International Bureau on 19 Ma\ 1 97 (19 05 97), original claims 4-6 and 8-10 amended, remaining claims unchanged (3 pages)]

the at least one log signal and the at least one special function log signal; performing an inverse-logarithmic conversion on the plurality of term signals to generate a plurality of inverse-log signals; and summing the plurality of inverse-log signals to generate the output signal.

3. A computer processor, which comprises: a decoder for decoding an input signal to generate a memory address; a memory circuit for storing a plurality of special function signals, the memory circuit outputting a corresponding special function signal in response to the memory address; a log converter for performing a logarithmic conversion on the corresponding special function signal to generate a log signal; a processing element for generating a term signal by performing at least one arithmetic operation involving the log signal; and an inverse-log converter for performing an inverse- logarithmic conversion on the term signal to generate an inverse- log signal.

4. The computer processor of claim 3, further comprising: an accumulator circuit for summing the inverse-log signal and at least one other signal representing a numeric value to produce an output signal.

5. The computer processor of claim 3, further comprising: a delay circuit, operatively coupled to the log converter, for allowing an input signal to bypass the decoder and the memory circuit.

6. The computer processor of claim 3, wherein the log converter comprises : a log memory for storing a plurality of log parameters and a plurality of second-order log parameters, the log memory providing as output ones of the log parameters and a second-order log parameter which correspond to the special function signal; and log arithmetic means, operatively coupled to the log memory, for generating the log signal by performing arithmetic operations involving the special function signal, the ones of the log parameters, and the second-order log parameter,- wherein the plurality of log parameters are calculated using a least squares method to estimate a logarithmic function over a domain of special function signals.

7. A computer processor, which comprises: a plurality of memory circuits for storing a plurality of special function signals; a de-multiplexer for selectively providing a first transmission path between an input bus and a particular memory circuit of the plurality of memory circuits; a multiplexer for selectively providing a second transmission path between a data bus and the particular memory circuit; wherein a data signal is receivable by the input bus and transmittable to the particular memory circuit via the first transmission path according to an address signal associated with the data signal, the particular memory circuit producing a corresponding special function signal in response to the data signal, the corresponding special function signal being transmittable to the data bus via the second transmission path; a log converter, operatively couple to the data bus, for performing a logarithmic conversion on the corresponding special function signal to generate a log signal; a processing element for generating a term signal by performing at least one arithmetic operation involving the log signal; and an inverse-log converter for performing an inverse- logarithmic conversion on the term signal to generate an inverse- log signal.

8. The computer processor of claim 7, wherein each of the plurality of memory circuits stores the plurality of special function signals associated with a respective special function.

9. The computer processor of claim 7, wherein the corresponding special function signal represents a value of a transcendental function or a hyperbolic function.

10. The computer processor of claim 7, further comprising: a delay circuit, operatively coupled to the de-multiplexer and the multiplexer, for allowing the data signal to bypass the plurality of memory circuits.

STATEMENT UNDER ARΗCLE 19

Claims 4-6 and 8-10 have been amended to correct typographical errors.