WO1997004396A1

WO1997004396A1 - A computer bus-based digital video decompression system

Info

Publication number: WO1997004396A1
Application number: PCT/US1996/011838
Authority: WO
Inventors: Richard H. Thompson
Original assignee: Stb Systems, Inc.
Priority date: 1995-07-17
Filing date: 1996-07-16
Publication date: 1997-02-06

Abstract

The invention is a computer monitor controller circuit (20) which decompresses compressed video data in real time for display on a VGA monitor (32). The system minimizes demand on the computer CPU (12) so that the CPU (12) is free to service other functions while the video data is decompressed, processed and displayed. The disclosed embodiment utilizes the MPEG compression/decompression standard and a PCI bus-based system.

Description

A COMPUTER BUS BASED DIGITAL VIDEO DECOMPRESSION SYSTEM

FIELD OF THE INVENTION

This invention relates personal computer bus architecture compatible circuitry. More specifically the invention relates to computer monitor controllers/accelerators.

BACKGROUND

Although television sets and VGA monitors appear similar, they accept different forms of information. Television sets display video signals which are in a composite video formate. On the other hand, the most common type of personal computer monitors is a VGA (video graphics adaptor) monitor. VGA monitors display video signals in a RGB (red green blue) data format. Currently, TV tuner cards are available for personal computers through which television programming can be viewed on a VGA monitor on a personal computer. These tuner boards receive a modulated audio/video signal that is split by the tuner into an analog audio signal and a composite video signal. The audio signals are sent to internal or external speakers. The composite video signal is sent to a composite video decoder which converts the composite video signal into YUV (digital luminance and chromonance) data. The YUV data is sent to a VGA controller which controls the conversion ofthe YUV data into RGB data which the VGA monitor can display. These modulated television signals discussed above are analog signals.

Technology is also available for the digital audio/video signals. Part of this technology includes compression/decompression ofthe digital data in order to enable higher speed transmission ofthe digital audio/video signals. Currently these systems comprise of a

decoder box that receives the compressed digital signal, decompresses these digital

signal and splits it into a digital audio signal and a digital video signal. The video signal is then converted into a composite video signal which is sent to a television set. Meanwhile, the digital audio signal is typically either: (1) converted into an analog signal which is sent to a television's speakers which further convert the analog signal into sound, or (2) sent to a separate stereo system that accepts a digital audio signal which converts the signal into sound.

Currently, to view a digital video on a VGA monitor, the output of a digital decoder box can be input into a tuner card so that the digital video signal can be viewed on a VGA monitor of a personal computer.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description taken in conjunction with the accompanying figures are provided to convey an understanding ofthe invention to persons reasonably skilled in the art necessary to make and use the invention.

FIG. 1 Figure 1 is a simple block diagram showing the architecture of major components of a computer digital video system.

FIG.2 Figure 2 is a block diagram showing the components ofthe computer digital video system in greater detail. FIG.3 Figure 3 is a block diagram showing in greater detail the input and output signals to and from the state logic device (SLD) in performing the write to the audio and/or video buffers. FIG. 4 Figure 4 is a block diagram showing in greater detail the inputs to the

SLD to generate an interrupt output to the VGA.

FIG. 5 Figure 5 is a block diagram showing in greater detail the inputs and

outputs to and from the SLD in managing the decompressor's accessing of data from the audio and video buffers and from the VGA memory bus.

FIG. 6 Figure 6 is a state logic diagram showing the relationships of states by

which the SLD manages the transmittal of data to the decompressor from the audio and video buffers and the VGA memory bus.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 illustrates how the present invention fits into a personal computer bus architecture (PC) environment. The backbone ofthe personal computer is the PC bus 10. A suitable bus would be the PCI bus architecture developed by Intel in conjunction with others. However, any bus with sufficient data bandwidth to handle the transmission rate

ofthe chosen data compression algorithm would be suitable. For the compression algorithm, MPEG-II, discussed below, a suitable bandwidth would allow transmission

rates of 15 Mbits/sec.(megabits/second). A larger bandwidth would allow for greater resolution and quality of output. The PC central processing unit (CPU) 12 is bidirectionally connected to the PC bus 10. A suitable computer would have an Intel 486 - 33 MHz (megahertz) or better CPU. Of course, comparable or better CPU's (such as an Intel Pentium or a Motorola/IBM Power PC processor would also be suitable. In the embodiment ofthe invention disclosed herein, the PC CPU 12 is the PC bus 10 master. As the bus master, the software that drives the hardware runs on the PC CPU 12. Therefore, the PC CPU, ultimately, controls all ofthe other components ofthe system as far as the system is concemed. If another appendage to the PC bus 10 acts as the bus master, it is the PC CPU 10 that cedes this authority to the other appendage's driver. Also either unidirectionally or bidirectionally connected to the PC bus 10 is a digital audio/video data source 14. Many different data sources 14 are possible. Suitable data sources 14 include, but are not limited to: a hard drive, CD-ROM drive, tape drive or some other type of drive. Other suitable data sources 14 include network cards, or communications or modem cards such as satellite cards, RF cable cards, and fiber optic cable cards. These sources may even be incorporated on the CPU system motherboard (not shown). The suitability ofthe various possible data sources 14 depends on the access speed or transmission speed ofthe source 14. The speed required depends on the compression/decompression scheme/algorithm used. Typically, the higher the quality or resolution of desired final output, the greater the amount of data that must be compressed transmitted or accessed and then processed. Currently the standards for audio/video compression are MPEG-I and MPEG-II. The transmission/access speeds required for such systems are 1.5 Mbits/sec. and 15 Mbits/sec. respectively. Currently available 6X CD-ROM drives have an access rate of approximately 7 Mbits/sec. making it suitable for MPEG-I data rates, but too slow for real time MPEG-II data rates. In the embodiment ofthe invention shown in the figures the invention is assembled on a board 20 which can be plugged into a personal computer's mother board (not shown). The VGA accelerator/video insert board 20 is bidirectionally connected to the PC bus 10. The board 20 may be a single board or a combination of stand alone or daughter and grand-daughter boards. The invention may also be incorporated, in whole or in part, directly on the motherboard ofthe PC (not shown). The board 20 includes a PC monitor controller 22 and a digital audio/video decompression section 24. Since most PC monitors are VGA monitors, a suitable PC monitor controller 22 would be the Brooktree BTV2115 MediaStream Controller which offers high performance graphical user interphase (GUI) acceleration and delivers resolutions consistent with currently available VGA monitors. Other monitor controllers

are available and other monitor controllers would be suitable. The monitor controller may interchangeably be called a "VGA controller" herein. The selected VGA controller

22 must be able to interface with the PC CPU 12 across the PC bus 10. Preferable the

VGA controller 22 will have VGA driver software which runs on the PC CPU 12 using

operating systems (OS) such as Windows or Windows NT from Microsoft, OS/2 Warp

from IBM, the Macintosh OS from Apple or most other OS's.

The VGA controller 22 is bidirectionally connected to a VGA memory bus 26. The VGA memory bus 26 is bidirectionally connected to the VGA memory 28. The specifications ofthe VGA memory 28 required is determined by the VGA controller 22 selected. The VGA controller 22 selected above requires 2 MB of 60 ns (nanosecond)

VGA memory 28. For the preferred embodiment ofthe present invention a suitable amount of VGA memory is 2 MEGs (megabytes). More specifically, in the preferred embodiment the inventors have used four (4) 256 K x 16 VRAM (video random access memory) chips. This configuration of VGA memory was made because its compatible

with the selected VGA controller. Many sources of suitable VRAM memory are available. The VGA memory 28 is connected to a digital to analog converter (D/A or DAC) 30 which converts digital data into an analog signal which controls the VGA monitor 32 to display the desired output (not shown) from the PC CPU 12. In other embodiments the DAC may be connected directly to the VGA controller 22 or could be incorporated, in whole or in part, in the VGA controller 22. In normal graphics accelerator card operation ofthe present invention, the VGA controller 22 receives instructions and data from the PC CPU 12 via the PC bus 10. The

VGA controller 22 sends graphic display data to the VGA memory 28 via the VGA memory bus 26. The DAC 30 converts the digital information into analog information

which controls the electron guns (not shown) ofthe VGA monitor 32.

FIG. 1 also illustrates that a digital audio/video (A/V) section 24 ofthe board 20 is bidirectionally connected to the VGA memory bus 26. The digital A/V section 24 of the board 20 is connected to the VGA controller 22 and to an audio digital to analog

(D/A or DAC) converter 34. The audio DAC 34 is connected to speakers 36 which convert the analog audio signal into a sound signal.

In operation, the PC CPU 12 obtains/receives compressed digital audio/video data from the data source 14 directly or indirectly through system memory (not shown). The PC CPU 12 then places the data on the VGA memory bus 26 (through the VGA controller 22) where it is made available to the digital audio/video decompression section 24 of the board 20. In this embodiment, the PC CPU 12 is the PC bus 10 master.

In altemative embodiments either the VGA controller or the data source 14 can be the bus 10 master. Whichever device acts as the bus master is responsible for getting the data on the VGA memory bus 26. The decompression section 24 decodes and then decompresses the audio/video data into separate YUV data and digital audio data. Additionally, in alternative embodiments the digital audio/video data may already have been received as separate signals or may be decoded by a transport sfream decoder (not shown) before the data is placed on the VGA memory bus. The YUV data is sent to the VGA controller 22. The VGA controller 22 converts (and scales) the YUV data into a RGB signal which is written (via the VGA data bus 26) to the VGA memory 28. The graphics DAC 30 converts the RGB data in the VGA memory 28 to an analog signal which is useful to the electron guns (not shown) in the VGA monitor 32. FIG 2 is also a block diagram ofthe architecture ofthe present invention in greater detail. Specifically, major components ofthe digital audio/video decompression section 24 are shown. The decompression section 24 supports and includes a digital audio/video decompressor 40. Since the current standard for high resolution video

compression is MPEG-II (MPEG is an acronym for "Moving Pictures Experts Group"),

a suitable digital audio/video decompressor 40 would be the SGS-Thomson Sti3520 real¬ time video decompression processor which supports both MPEG-I and MPEG-II standards. However, a MPEG-I only decompressor would also be suitable if lower

resolution lower quality output is acceptable for the application. Additionally, other

decompression algorithms may also be suitable with some modification ofthe preferred embodiment ofthe invention without departing from the spirit ofthe invention. The decompressor 40 receives the compressed data from the VGA memory bus 26 through a video buffer 42 and an audio buffer 44 which are each connected to both the VGA memory bus 26 and the decompressor 40. For the audio buffer, 25 ns (nanosecond) rate

1 KB FIFO (first in first out) memory is suitable. For the video buffer, a 25 ns 4 KB

FIFO is suitable. In the preferred embodiment four (4) 1 KB 8 bit wide FIFO memory is used instead of a single 4 KB chip to increase the effective write speed to the buffers 42 and 44.

In operation the video buffer 42 and the audio buffer 44 act as reservoirs of data for feeding data to the decompressor 40. A state logic device (SLD) 50 is bidirectionally connected to the VGA memory bus 26 to manage access to the decompressor from the PC CPU 12 through the VGA controller 22 and the VGA memory bus 26. The SLD 50 ensures that the video and audio buffers 42 and 44 do not remain empty. The SLD is also connected to the VGA controller 22 to send interrupt signals to the VGA controller 22. The interrupt signal is passed to the operating software which tells the VGA controller 22 to look at the control signals on the VGA memory bus 26 or in a buffer (not shown) or a register (not shown) in the SLD 50. In an altemative embodiment, multiple interrupts to the VGA controller 22 may be used if they are available. The SLD is also bidirectionally connected to the digital decompressor 40 to manage the interrupts and

requests. A suitable SLD is the XILINX XC7354 which is a programmable logic device (PLD) used to implement the logic necessary to manage the operational needs ofthe decompressor 40. In the embodiment shown, the SLD 50 is a synchronous state machine which generates the handshaking signals to inteφhase the VGA 24 controller 22 and the decompressor 40 through the video and audio buffers 42 and 44 and a data transceiver (not shown in Figure 2) for accessing the decompressor's 40 registers (not shown) without passing through the video or audio buffers 42 and 44.

The SLD's 50 control logic can be divided into three major parts: (1) the VGA memory write interface, (2) the decompressor 40 buffer read interface and (3) the VGA controller 24 interrupt register.

The VGA memory interface decodes access to the video and audio buffers 42 and 44 from the VGA controller 40. It does this by controlling the writing of information through the VGA memory bus 26 to the video and audio buffers 42 and 44. For the SLD logic and VGA memory (in this case VRAM) selected, the following input signals are available:

1. CAS3 System VGA Memory CAS (Column Address Strobe) 2. RAS2 System VGA Memory RAS (Row Address Strobe) 3rd MB

3. RAS3 System VGA Memory RAS 4th MB

4. DSF System VGA Memory special function enable

These inputs to the SLD are used to generate the following outputs used to manage the writing of data to the video and audio buffers 42 and 44: 1. FIFO WCLK Video and audio buffer write clocks

2. VFIFOWEN Video buffer write enable

3. AFIFOWEN Audio buffer write enable The source and destination of these inputs and outputs is illustrated in Fig.3.

The VFIFOWEN and/or AFIFOWEN outputs allow the compressed data to be written to

separate video and audio buffers 42 and 44 through the PC bus 10, the VGA controller

22 and the VGA memory bus 26. See Fig. 2. The VGA controller maps the video data

5 to what appears to the VGA controller 22 to be the 3rd MEG block of VGA memory

which is actually the video buffer 42. Likewise the VGA controller maps the audio data to what appears to it to be the 4th MEG block of VGA memory which is actually the audio buffer 44. The CAS and DSF signals are latched on the falling edge of RAS3 and used to distinguish a valid data write cycle to the audio and/or video buffers 44 and 42

10 from other types of cycles - such as a refresh cycle. Two (2) write enables, VFIFOWEN and AFIFOWEN, are output for the video and audio buffers 44 and 42 using RAS2 as

the qualifier for video and RAS3 for the Audio decode. A common write clock FIFO WCLK is output writing to both the video or audio buffers 42 and 44.

Given the desired available inputs and the desired output functions generating the

15 logical relationships between the two is within the skills of a reasonably skilled

practitioner of digital logic design.

FIG. 4 illustrates the inputs and outputs which are part ofthe VGA controller interrupt part ofthe confrol logic. The VGA controller interrupt part ofthe SLD logic interrupts the VGA controller 22 so that it can control obtaining and transferring video

20 and audio and other types of data to the decompressor 40. In the preferred embodiment disclosed, the foUowing input signals are used:

» 1. AUDIRQ Decompressor audio interrupt request

2. VIDIRQ Decompressor video interrupt request

« 3. VIDFIFOE Video buffer empty signal

25 4. AUDFIFOE Audio buffer empty signal

These inputs are used to generate the following outputs:

1. IRQOUT Interrupt request to system 2. RDATA (0..3) VGA memory data bits 0 to 3

3. REGBUFEN Extemal data buffer enable

For the embodiment shown, the SLD 50 generates a single interrupt output

(IRQOUT)which is sent directly to the VGA controller 22 for multiple situations which

require an interruption. When the VGA controller is interrupted, it looks (through the

VGA memory bus 26) for the RDATA (0...3) output which are held in a register (not shown) in the SLD to determine the nature/cause ofthe interrupt. ((0..3) represents multiple signals identified as 0 through 3.) From the RDATA signal, the driver software determines what action to take. In the preferred embodiment the driver software is run on the PC CPU 12. All SLD register accesses are done through data transceiver 41 enabled by the signal REGBUFEN. When REGBUFEN is enabled, data is transferred

from the UGA memory bus 26 directly to decompressor 40 through the data transceiver. Many suitable data transceivers are available.

Given the desired available inputs and the desired output functions generating the logical relationships between the two is within the skills of a reasonably skilled practitioner of digital logic design.

FIG. 5 illustrates the inputs and outputs which are used by and generated by the SLD 50 in the decompressor buffer read interface part ofthe state logic. The following inputs are used by the SLD 50:

1 1.. C CLLOOCCKK Decompressor system 55MHz clock 2. CDREQ Decompressor video data request 3. AUDREQ Decompressor audio data request 4. VIDFIFOE Video buffer empty indicator 5. AUDFIFOE Audio buffer empty indicator 66.. M MDDAATTAA((1155....2277)) VGA memory bits for decoding of decompressor registers (15..27 represents particular eolations for data on the BGA memory bus.)

7. ROM WE VGA memory write strobe 8. TRG RD VGA memory read strobe

These inputs are used by the SLD 50 to generate the following outputs: 1. MPEGR W Read/Write strobe for Sti3520

2. AUDREGS Decompressor audio register select

3. VIDREGS Decompressor video register select

4. AUDSTRB Decompressor audio compressed data strobe

5. CDSTRB Decompressor video compressed data strobe

6. VFIFOEN(x) Video buffer output enables 0 to 3

7. AFIFOEN Audio buffer output enable

8. ARDCLK Audio buffer read clock

9. VRDCLK(x) Video buffer read clock 0 to 3

The video and audio data is read from their respective buffers 42 and 44 in the absence of system control. The two criteria for allowing transfers to occur are that: (1) the buffer

is not empty (VIDFIFOE and AUDFIFOE) and (2) the decompressor is requesting data

(CDREQ and AUDREQ). Accesses to the decompressor's intemal registers (not shown)

or the extemal interrupt register (not shown) will always be granted higher priority than transfer of either audio or video compressed data. These interruption states are identified in FIG. 6 as CREGR and CREGW.

FIG. 6 is a state diagram illustrating the operation ofthe decompressor read

(from audio and/or video buffer) part ofthe confrol logic. The initial state is IDLEO.

From IDLEO, if: (1) no register access is being run by other parts ofthe state logic , (2) if the audio buffer 44 is not empty (AUDFIFOE), and (3) the decompressor 40 is requesting audio data (AUDREQ) then the next state will be ACDl - initiating the transfer of audio data from the audio buffer 44 to the decompressor 40. If not, then the next state is EDLE1.

From IDLE 1, if (1) no register access is pending, (2) if the video buffer 22 is not empty (VIDFIFOE) and the decompressor 40 is requesting video data (CDREQ) then the next state will be VCD1- initiating the fransfer of compressed video data from the video buffer 42 to the decompressor 40.

An audio data transfer occurs in states ACDl through ACD3. Upon entering ACDl the audio buffer 44 read clock (ARDCLK) is strobed, and the buffer output enable

(AFIFOEN) is activated. In ACD2 and ACD3 the buffer output enable (AFIFOEN) is still enabled and the buffer line AUDSTRB is activated. Upon leaving ACD3 the next state is IDLE1. Upon emptying, the audio buffer 44 will cause the SLD to generate an interrupt (IRQOUT) to the VGA controller 22 indicating the need for more data.

A video data fransfer occurs in states VCDl through VCD3. Upon entering VCD 1 the video buffer 42 read clock (VRDCLK(x) where x = BYTECOUNT) is sfrobed and the buffer output enable is activated. In states VCD2 and VCD3, the buffer output enable remains active and the decompressor CDSTRB line is activated. Each time through this sequence only one byte ofthe multibyte wide video buffer is read. The enabled byte is determined by an intemal counter called BYTECOUNT. Upon leaving state VCD3 to state IDLE 2, BYTECOUNT is incremented and then the sequence proceeds to state IDLE3. In IDLE3 the value of BYTECOUNT is checked, and if it is not 0, then the sequence goes back to state VCDl for another byte transfer. The value range of BYTECOUNT is determined by the byte width ofthe video buffer 42. In another embodiment ofthe invention, the byte count and intermediate idle state configuration could also be incoφorated into the audio data transfer state logic, if the audio data is designed to have multibyte wide audio buffers. The puφose ofthe intermediate idle state and BYTECOUNT incrementor is to give the state logic an opportunity to interrupt the transfer of multibyte data to address higher priority tasks such as register read and writes (CREQR & CREGW). If BYTECOUNT is 0 then the next state is IDLEO. Upon emptying, the video buffer 42 will generate an interrupt

(IRQOUT) to the system indicating the need for more data.

A read or write of one ofthe decompressor 40 intemal registers may happen asynchronously to the emptying ofthe audio and video buffers 44 and 42. The states CREGR and CREGW are entered from either ofthe four IDLE states. This state logic design is intended to be consistent with treating these operations with higher priority than the transfer of audio or video data. Given the state diagram, identification of input and output signals, and the written description therewith, it is with the ability of a reasonably skilled practitioner to create the logic equations and configure the state logic device.

Returning to FIG. 2, after the decompressor 40 reads the compressed data it decodes the data into YUV video data and digital audio data. In order to accomplish this

task, the particular decompressor chip selected in the disclosed embodiment requires buffer memory (not shown). The amount and speed ofthe buffer memory is determined by the requirements ofthe particular decompressor selected. The decompressor 40 is

connected to a YUV data bus 60. Through this connection the decompressor outputs the YUV data to the YUV data bus 60. The decompressor 40 also outputs a digital audio data stream to an audio DAC 88. The DAC 88, in turn, outputs an analog audio signal.

The YUV data bus 60 is also connected to the VGA controller 22 making YUV data available to the VGA controller 22.

A composite video encoder 68 is also connected to the YUV bus 60. The composite video encoder 68 is capable of converting the YUV data into a composite

video signal.

The board can also receive extemal modulated audio/video input 70 through a tuner 72. The tuner 72 splits the modulated audio video input into a composite video signal and an analog audio signal. The composite video signal from tuner 72 is input into the composite video decoder 66 which converts it to YUV data and places it on the

YUV data bus 60. This data is then available to the VGA controller 22 for display on the

VGA monitor.

The board can also receive a composite video and corresponding analog audio

signal. Composite video includes standard composite video and s-video or other video signal configurations. The composite video signal is converted into YUV data by the composite video decoder 66 and placed on the YUV data bus 60. The extemal anεiog audio signal associated with the extemal composite video signal and the analog audio signal from DAC 88 and the analog audio signal from the tuner 72 are connected to an audio MUX 85 which selects which analog signal will be passed on as the audio output

82. Similarly the extemal composite video, and the composite video from the tuner, and the composite video from the composite video encoder 68 are all connected to a video

MUX 84 which selects which analog signal will be passed on as the composite video output 86 for use with a conventional television or video tape player/recorder.

The software driver ofthe VGA controller board serves as the MUX select for both the video MUX 84 and the audio MUX 85 which determines which MUX input will be passed through the MUX to the output ofthe board 20.

Although the present invention has been described with reference to a specific embodiment, further modifications and improvements will occur to those skilled in the art. For example, in other embodiments ofthe invention, different state logic schemes could be implemented or a micro controller could perform the interrupt management function ofthe SLD disclosed herein.

In yet other embodiments it is possible to use a single buffer for both audio and video rather than separate buffers.

Another example of other embodiments relates to the analog circuit components discussed herein. Although an audio digital to analog devices is typically shown and discussed in the present description ofthe preferred embodiment, this is not a necessary element ofthe board 20 in some cases it may be desirable to have the audio signal converted on the same board, in some cases it might be desirable to have the audio signal converted on a separate board, and in some cases it might be desirable to have the audio signal converted in a completely separate box such as a hi-fi stereo. Typically, it is more desirable to have as much ofthe analog circuitry removed from the digital circuitry. This is because ofthe negative effect the proximity ofthe digital circuit has on the noise ratio ofthe analog signal. It is to be understood therefore, that the invention encompasses all such modifications that do not depart from the spirit and scope ofthe invention as defined in the appended claims.

Claims

We Claim:

1. A computer monitor controller comprising of an electronic bus connected to :

a) a data source; and b) a computer monitor controller which is fiirther connected to a b) video decompression section.

2. A computer monitor controller of claim 1 wherein the elecfronic buss is further connected to a CPU.

3. A computer monitor controller of claim 1 wherein the video decompression section further comprises of a decompression microprocessor.

4. A computer monitor controller of claim 3 wherein the video decompression section further comprises of an decompression microprocessor interrupt control manager.

5. A computer monitor of claim 4 wherein the decompression microprocessor interrupt control manager further comprises of a state logic device.

6. A computer monitor controller of claim 3 wherein the video decompression section further comprises of a plurality of audio/video buffers to act as a reservoir for data being feed into the decompression microprocessor.