WO1996041379A1 - Wafer-scale integrated-circuit systems and method of manufacture - Google Patents

Wafer-scale integrated-circuit systems and method of manufacture Download PDF

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Publication number
WO1996041379A1
WO1996041379A1 PCT/US1996/010005 US9610005W WO9641379A1 WO 1996041379 A1 WO1996041379 A1 WO 1996041379A1 US 9610005 W US9610005 W US 9610005W WO 9641379 A1 WO9641379 A1 WO 9641379A1
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WO
WIPO (PCT)
Prior art keywords
integrated
circuit unit
wafer
circuit
memory
Prior art date
Application number
PCT/US1996/010005
Other languages
French (fr)
Inventor
Christophe R. Tretz
Robert C. White
Original Assignee
The Trustees Of Columbia University In The City Of New York
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Trustees Of Columbia University In The City Of New York filed Critical The Trustees Of Columbia University In The City Of New York
Publication of WO1996041379A1 publication Critical patent/WO1996041379A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Definitions

  • the present invention relates generally to semi ⁇ conductor wafer-scale integrated circuits and, more particularly, to a wafer-scale integrated circuit design and layout technique. 5
  • the following published items are representative of proposed wafer-scale integration (WSI) for memory systems:
  • Tazunoki discloses forming a plurality of circuits on a single wafer and describes a technique for interconnecting the circuits.
  • the patent discloses a wafer-scale memory
  • the multiplexer can be configured to form a linear array of cells that achieves a fixed known delay time from function logic to function logic of the cells.
  • U.S. Patent No. 5,214,657 issued May 25, 1993 to Farnworth et al. discloses a semiconductor wafer having a plurality of integrated circuit memory sections which are separated from one another by areas called "street areas". Error detection and correction circuitry is provided within the street areas to detect and correct circuit errors generated within the discrete memory sections.
  • U.S. Patent No. 5,126,828 issued June 30, 1992 to Hatta et al. discloses making cut-outs centrally and/or peripherally to a wafer to allow for an increase in the number of bonding pads for interconnections along the periphery of the wafer. The increase in bonding facilitates communication between circuitry on the wafer and external outside circuitry.
  • U.S. Patent No. 4,038,648 issued July 26, 1977 to Chesley discloses a self-configurable circuit structure for achieving wafer-scale integration. Additionally, a circuit structure is disclosed which accomplishes wafer-scale integration by using dynamic circuit intercoupling capable of subsequent reconfiguration of the intercoupling structure when malfunctions are detected.
  • Preferred integrated-circuit design and layout in a WSI-system or -assembly is such that an integrated- 35 circuit portion having greater yield sensitivity, e.g., the central processor unit (CPU) of a single-chip microcomputer, is disposed in a central region of the semiconductor wafer substrate. Less yield-sensitive units or blocks, e.g., memory arrays are disposed in a peripheral region complementary to the central region. In this fashion, favorable yield can be achieved in the manufacture of high-performance WSI-systems.
  • an integrated- 35 circuit portion having greater yield sensitivity e.g., the central processor unit (CPU) of a single-chip microcomputer
  • Fig. l is a top-view schematic of a single-chip computer in accordance with a preferred embodiment of the invention.
  • the single-chip computer of Fig. 1 has a mostly random-logic CPU 11, several RAM arrays 12 coupled to the microprocessor 11, and several I/O drivers 13 connected to the RAM arrays 12 or/and to the CPU 11, all on a common semiconductor wafer substrate 10.
  • Other or further functional components may be included, such as fuses, for example.
  • the substrate wafer has a size or diameter in a range from 2 to 5 inches.
  • integrated-circuit feature size or design rule is in a range from 0.8 to 2 micrometers approxi- mately.
  • satisfactory yield may be realized with design rules down to approximately 0.35 micrometer.
  • Resulting integrated-circuit assemblies can operate with a power supply in a range from 3 to 5 volts. In operation, such assemblies have desirably low heat dissipation.
  • the microprocessor 11 is disposed centrally on the wafer substrate, occupying an area of approximately 4 cm 2 .
  • the memory arrays 12 are disposed surrounding the microprocessor 11. Each memory array occupies an area of approximately 4 cm 2 and may have up to 64 Mbits of storage capacity. Thus, with 8 memory arrays, the wafer assembly may have a total capacity of 512 Mbits.
  • the I/O drivers 13 are also disposed peripherally, surrounding the memory arrays 12 as shown.
  • VLSI very large scale integrated
  • CMOS complementary metal oxide semiconductor
  • the invention is predicated on the observation that most defects, and especially those affecting pattern processing, tend to be near the periphery of the wafer substrate.
  • most defects, and especially those affecting pattern processing tend to be near the periphery of the wafer substrate.
  • the amount of on-chip fast memory may be so large so as to reduce the amount of cache or external extended memory that is needed.
  • overall execution speed and throughput are enhanced as most or all system/operating software can be held in local memory.
  • Yield sensitivity of an integrated-circuit unit in a system may be understood as directly related to the likelihood of operational failure of the unit due to material defects, and indirectly related to the number of similar units which can substitute in performing its function in the system.
  • a CPU is more yield sensitive than a memory array, and especially so if the CPU is coupled to several memory arrays.
  • memory arrays are less critical also in view of their lesser complexity.
  • a memory array may include redundant cells which, upon suitable address remapping, can be used as substitutes for defective cells, thereby compensating for defects.
  • Testing of a CPU and of surrounding memory units may involve physical contacting with external probes, of contact pads included for this purpose. Since surface area is not at a premium in a wafer-scale assembly, inclusion of a large number of such pads is practicable. More typically, a number of approximately 20 to 30 pads may be sufficient per assembly.
  • Testing may also involve the use of software loaded into the assembly via its input pads. Such software may be designed for testing of the CPU, as well as of memory units connected to the CPU. Test results may be read out at the output pads of the assembly, for example.
  • Reconfiguring may involve physically breaking connections to deficient portions of a memory unit or to a deficient memory unit in its entirety. This typically involves the use of a laser pulse for severing a metallic connection, e.g., in a fuse unit.
  • reconfiguring typically involves software modifications, e.g., for customary logical memory addresses to be translated into appropriate physical addresses of usable memory units and memory cells. Such translation may then be carried out for each store/fetch memory operation in device use.
  • wafer-scale integrated-circuit systems promise to find use, e.g., in high-speed, low-power multimedia processing and communications systems.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

With the density of defects which affect device yield being less near the center of a semiconductor wafer (10) than near the periphery, increased yield can be realized in wafer-scale integrated (WSI) circuit manufacture upon placing a more yield-sensitive functional unit at the center of the wafer (10). For example, in a single-chip computer a control processor unit (11) can be integrated with memory arrays (12) surrounding the central processor unit (11).

Description

Description
Wafer-Scale Integrated-Circuit Systems And Method Of Manufacture
Background of the Invention
The present invention relates generally to semi¬ conductor wafer-scale integrated circuits and, more particularly, to a wafer-scale integrated circuit design and layout technique. 5 The following published items are representative of proposed wafer-scale integration (WSI) for memory systems:
U.S. Patent No. 5,309,011, issued May 3, 1994 to Tazunoki et al. discloses a packaging technique for
10 wafer-scale integrated memory devices, in which multiple wafers having memory circuits are stacked in a spaced-apart manner and fastened to a pillar passing through the center portion of each wafer. The patent also discloses the use of additional connecting pillars
15 in the peripheral areas of the wafers. In another embodiment, Tazunoki discloses forming a plurality of circuits on a single wafer and describes a technique for interconnecting the circuits. In still another embodiment, the patent discloses a wafer-scale memory
20 arrangement where the central portion of the wafer is filled with memory blocks of substantially the same size and the remaining portion filled with smaller peripheral memory blocks to act as redundant memory to be substituted for any defective central portion memory « 25 blocks. , U.S. Patent No. 5,287,472, issued February 15, t 1994 to Horst discloses an apparatus for constructing a memory system in a linear array wafer-scale integrated circuit configuration. The memory system contains a
30 plurality of individual, substantially identically formed memory cells each connected to a neighboring cell by a multiplexer. The multiplexer can be configured to form a linear array of cells that achieves a fixed known delay time from function logic to function logic of the cells.
U.S. Patent No. 5,214,657, issued May 25, 1993 to Farnworth et al. discloses a semiconductor wafer having a plurality of integrated circuit memory sections which are separated from one another by areas called "street areas". Error detection and correction circuitry is provided within the street areas to detect and correct circuit errors generated within the discrete memory sections.
U.S. Patent No. 5,126,828 issued June 30, 1992 to Hatta et al. discloses making cut-outs centrally and/or peripherally to a wafer to allow for an increase in the number of bonding pads for interconnections along the periphery of the wafer. The increase in bonding facilitates communication between circuitry on the wafer and external outside circuitry.
U.S. Patent No. 4,038,648 issued July 26, 1977 to Chesley discloses a self-configurable circuit structure for achieving wafer-scale integration. Additionally, a circuit structure is disclosed which accomplishes wafer-scale integration by using dynamic circuit intercoupling capable of subsequent reconfiguration of the intercoupling structure when malfunctions are detected.
In the manufacture of semiconductor integrated circuits, yield is adversely affected by the presence of microscopic defects at a semiconductor wafer surface, as such defects can result in localized electrical device failure. The following published articles report on related quantitative studies: F. J. Meyer et al. , "Modeling Defect Spatial
Distribution," IEEE Transactions on Computers. Vol. 38, No. 4, April 1989 discloses a center-satellite model for describing the distribution of defects on wafers. The article sets aside the theory that defects are randomly distributed on the wafer and suggests a model 5 of defect clustering or scattering to be used to predict wafer yields.
P. Schvan et al., "Detectivity and Yield Analysis and VLSI and WSI," Proceedings of the IEEE International Conference on Computer Design, pp. 89-92,
10 1986 discloses a methodology to predict the yield of VLSI (very large scale integration) and WSI circuits. The methodology in the article is based on electrical failure densities measured using standard test circuits and circuit sensitivity obtained by analyzing the
15 circuit layout. A methodology for predicting defects is discussed.
Since concern with defects is particularly acute in WSI, it is understandable that WSI has been proposed for memory devices, designed to have multiple memory
20 arrays with the same structure, and each array having regular internal structure. Such design and internal structure can provide for a large measure of redun¬ dancy, as electrical connections can be established or broken for defective arrays to be bypassed in favor of
25 better arrays, and as address remapping can be used to bypass defective portions within an array.
Where there is no regular pattern, as, e.g., in the case of a central processor unit (CPU) , such techniques are not applicable, so that yield in
30 manufacture may be expected to be unacceptably low when a CPU is to be included in WSI.
I
Summary of the Invention
Preferred integrated-circuit design and layout in a WSI-system or -assembly is such that an integrated- 35 circuit portion having greater yield sensitivity, e.g., the central processor unit (CPU) of a single-chip microcomputer, is disposed in a central region of the semiconductor wafer substrate. Less yield-sensitive units or blocks, e.g., memory arrays are disposed in a peripheral region complementary to the central region. In this fashion, favorable yield can be achieved in the manufacture of high-performance WSI-systems.
Brief Description of the Drawing
Fig. l is a top-view schematic of a single-chip computer in accordance with a preferred embodiment of the invention.
Detailed Description
The single-chip computer of Fig. 1 has a mostly random-logic CPU 11, several RAM arrays 12 coupled to the microprocessor 11, and several I/O drivers 13 connected to the RAM arrays 12 or/and to the CPU 11, all on a common semiconductor wafer substrate 10. Other or further functional components may be included, such as fuses, for example. Advantageously, the substrate wafer has a size or diameter in a range from 2 to 5 inches.
Preferably, for high over-all yield in current practice, integrated-circuit feature size or design rule is in a range from 0.8 to 2 micrometers approxi- mately. Foreseeably, satisfactory yield may be realized with design rules down to approximately 0.35 micrometer. Resulting integrated-circuit assemblies can operate with a power supply in a range from 3 to 5 volts. In operation, such assemblies have desirably low heat dissipation.
The microprocessor 11 is disposed centrally on the wafer substrate, occupying an area of approximately 4 cm2. The memory arrays 12 are disposed surrounding the microprocessor 11. Each memory array occupies an area of approximately 4 cm2 and may have up to 64 Mbits of storage capacity. Thus, with 8 memory arrays, the wafer assembly may have a total capacity of 512 Mbits. The I/O drivers 13 are also disposed peripherally, surrounding the memory arrays 12 as shown.
Various known fabrication processes for very large scale integrated (VLSI) circuits may be used to fabricate a WSI-circuit in accordance with the present invention. Preferred fabrication processes are those used for complementary metal oxide semiconductor (CMOS) circuits. Such processes are well known, for silicon as well as for compound-semiconductor substrates.
The invention is predicated on the observation that most defects, and especially those affecting pattern processing, tend to be near the periphery of the wafer substrate. In the present case, with a CPU- area free of defects, even if two thirds of the surrounding memory is defective, more than 170 Mbits of on-chip memory remains available. In this exemplary configuration, the amount of on-chip fast memory may be so large so as to reduce the amount of cache or external extended memory that is needed. Also, overall execution speed and throughput are enhanced as most or all system/operating software can be held in local memory.
Yield sensitivity of an integrated-circuit unit in a system may be understood as directly related to the likelihood of operational failure of the unit due to material defects, and indirectly related to the number of similar units which can substitute in performing its function in the system. Thus, a CPU is more yield sensitive than a memory array, and especially so if the CPU is coupled to several memory arrays.
As compared with logic/arithmetic processor units, memory arrays are less critical also in view of their lesser complexity. And a memory array may include redundant cells which, upon suitable address remapping, can be used as substitutes for defective cells, thereby compensating for defects.
Once a device of the invention has been made, it typically will be subjected to functional testing and, depending on test results, to functional reconfiguring.
Testing of a CPU and of surrounding memory units may involve physical contacting with external probes, of contact pads included for this purpose. Since surface area is not at a premium in a wafer-scale assembly, inclusion of a large number of such pads is practicable. More typically, a number of approximately 20 to 30 pads may be sufficient per assembly.
Testing may also involve the use of software loaded into the assembly via its input pads. Such software may be designed for testing of the CPU, as well as of memory units connected to the CPU. Test results may be read out at the output pads of the assembly, for example. Reconfiguring may involve physically breaking connections to deficient portions of a memory unit or to a deficient memory unit in its entirety. This typically involves the use of a laser pulse for severing a metallic connection, e.g., in a fuse unit. Also, reconfiguring typically involves software modifications, e.g., for customary logical memory addresses to be translated into appropriate physical addresses of usable memory units and memory cells. Such translation may then be carried out for each store/fetch memory operation in device use.
Other than as computers for data processing, wafer-scale integrated-circuit systems promise to find use, e.g., in high-speed, low-power multimedia processing and communications systems.

Claims

Claims
l. A method for making a wafer-scale integrated- circuit system comprising first and second interconnected integrated-circuit units on a common semiconductor wafer substrate, the first integrated-circuit unit being more yield-sensitive than the second integrated-circuit unit, the method comprising a step of forming a pattern at a major surface of the semiconductor wafer substrate, wherein the first integrated-circuit unit is formed in a first, central region of the semiconductor wafer substrate, and the second integrated-circuit unit is formed in a second, peripheral region of the semiconductor wafer substrate.
2. The method of claim 1, wherein the first integrated-circuit unit comprises a logic/arithmetic unit.
3. The method of claim 1, wherein the second integrated-circuit unit comprises a memory array.
4. The method of claim 3, wherein the second integrated-circuit unit comprises a plurality of memory arrays.
5. The method of claim 1, wherein the second integrated-circuit unit comprises an I/O driver unit.
6. The method of claim 1, wherein the semiconductor wafer substrate has a diameter of at least 2 inches.
The method of claim l, wherein the pattern is formed with feature size in a range from 0.35 to 2 micrometers.
A wafer-scale integrated-circuit system comprising interconnected first and second integrated-circuit units on a common semiconductor wafer substrate, the first integrated-circuit unit being more yield-sensitive than the second integrated-circuit unit, wherein the first integrated-circuit unit is disposed in a first, central region of the semiconductor wafer substrate, and the second integrated-circuit unit is disposed in a second, peripheral region of the semiconductor wafer substrate.
9. The system of claim 8, wherein the first integrated-circuit unit comprises a logic/arithmetic unit.
10. The system of claim 8, wherein the second integrated-circuit unit comprises a memory array.
11. The system of claim 10, wherein the second integrated-circuit unit comprises a plurality of memory arrays.
12. The system of claim 8, wherein the second integrated-circuit unit comprises an I/O driver unit.
13. The system of claim 8, wherein the semiconductor wafer substrate has a diameter of at least 2 inches.
14. The system of claim 8, wherein integrated-circuit feature size is in a range from 0.35 to 2 micrometers.
PCT/US1996/010005 1995-06-07 1996-06-07 Wafer-scale integrated-circuit systems and method of manufacture WO1996041379A1 (en)

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US47895795A 1995-06-07 1995-06-07
US08/478,957 1995-06-07

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1094467A2 (en) * 1999-10-19 2001-04-25 Motorola, Inc. Processing equipment with embedded MRAMS including dual read ports

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JPH04130656A (en) * 1990-09-20 1992-05-01 Mitsubishi Electric Corp Semiconductor integrated circuit
US5300796A (en) * 1988-06-29 1994-04-05 Hitachi, Ltd. Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells
US5386129A (en) * 1991-09-13 1995-01-31 Nec Corporation Power supply system of semiconductor chip for optimizing impedances of power supply sub-systems associated with outside and inside function blocks
US5410161A (en) * 1991-07-12 1995-04-25 Nec Corporation Semiconductor device equipped with characteristic checking element

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US5300796A (en) * 1988-06-29 1994-04-05 Hitachi, Ltd. Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells
JPH04130656A (en) * 1990-09-20 1992-05-01 Mitsubishi Electric Corp Semiconductor integrated circuit
US5410161A (en) * 1991-07-12 1995-04-25 Nec Corporation Semiconductor device equipped with characteristic checking element
US5386129A (en) * 1991-09-13 1995-01-31 Nec Corporation Power supply system of semiconductor chip for optimizing impedances of power supply sub-systems associated with outside and inside function blocks

Non-Patent Citations (1)

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Title
W.R. RUNYAN and K.E. BEAN, "Semiconductor Integrated Circuit Processing Technology", ADDISON WESLEY, 1990, page 593 and page 637. *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1094467A2 (en) * 1999-10-19 2001-04-25 Motorola, Inc. Processing equipment with embedded MRAMS including dual read ports
EP1094467A3 (en) * 1999-10-19 2001-05-30 Motorola, Inc. Processing equipment with embedded MRAMS including dual read ports
JP2001175641A (en) * 1999-10-19 2001-06-29 Motorola Inc Embedded mram including dual read port
SG90176A1 (en) * 1999-10-19 2002-07-23 Motorola Inc Embedded mrams including dual read ports
US6609174B1 (en) 1999-10-19 2003-08-19 Motorola, Inc. Embedded MRAMs including dual read ports
KR100751841B1 (en) * 1999-10-19 2007-08-24 모토로라 인코포레이티드 Processing equipment with embedded mram and method of fabricating data processing equipment

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