WO1996033495A1

WO1996033495A1 - On-chip capacitor

Info

Publication number: WO1996033495A1
Application number: PCT/EP1995/001457
Authority: WO
Inventors: Dieter Wendel; Erich Klink; Otto Torreiter; W. Van Der Hoeven
Original assignee: International Business Machines Corporation
Priority date: 1995-04-18
Filing date: 1995-04-18
Publication date: 1996-10-24
Also published as: JPH09507997A

Abstract

The invention relates to the provision of an on-chip capacitor resulting in improved testability and reliability of the entire chip. The on-chip capacitor according to the invention is realized by a complementary cross-coupled structure which has a flip-flop characteristic. If a leakage current occurs in one of the transistors of the entire circuit structure this will cause the structure to switch into another state so that the leakage current is cut off. Thereby the on-chip capacitor is self-repairing as regards pinholes which develop over time.

Description

D E S C R I P T I O N

ON-CHIP CAPACITOR

The invention concerns an on-chip capacitor and a method of designing an integrated circuit chip to implement an on-chip capacitor.

It is known to use on-chip capacitors especially for high performance microprocessors which require improved stabilization of voltage and ground supply. On-chip capacitors are also used as decoupling capacitors for memory chips.

Due to the high simultaneous switching rates of logic gates, array macros and I/O circuitry a high charge has to be provided within high frequency ranges in state of the art integrated circuit chips. On module capacitances and on card capacitances are limited by their relatively low cut off frequencies - in general less than 200 MHz - which is caused by the high inductance of the voltage and ground path to the chip circuitry. Off-chip capacitors are too far away from the switching elements of an integrated circuit chip to provide the required charge for the switching elements on the chip fast enough. Therefore on-chip capacitors are required.

Three different types of on-chip capacitors are known from the state of the art. The first type is the N-well junction capacitance. The capacitance in this case is provided by the depletion layer capacitance of diffused or implanted areas as for example N-well implantation into P substrate. Thereby the N-well is connected to the power supply (VDD) and the substrate to ground (GND) . IBM Technical Disclosure Bulletin, "Off-Chip Power Supply Decoupling Via N-Well", August 1986, pages 1221 - 1222 by Penoyer describes a technique for utilizing the complementary metal oxide silicon (CMOS) technology N- wells to supply the high on-chip currents of short duration (WI's) from a low impedance on-chip source. The inherently large capacitance between N-well and substrate provides a ready-made on-chip charge source which may be used to sink high current spikes of short duration which appear on a chip power supply bus. However, the achievable capacitance value is limited and the resistance of the connections to the metal VDD bus of the chip image is high. This restricts high frequency applications.

The second type of on-chip capacitors known from the state of the art is to make usage of the metal capacitances of all metal layers which are high frequency capacitances but have only low values. IBM Technical Disclosure Bulletin, "Method of Increasing On Chip VDD Decoupling Capacitance Using a Shielded Micro Strip Structure", January 1992, pages 59 - 60 by Dhong and Kirihata shows a method of increasing on-chip VDD decoupling capacitance using a shielded micro-strip structure. The VDD bus is sandwiched between the grounded substrate and a grounded conductor, forming a shielded micro-strip structure. As a result, a larger VDD decoupling capacitance is obtained for a given surface area than in the method where the VDD bus is placed above a grounded conductor which in turn is above the substrate.

The third type of on-chip capacitors known is the usage of gate capacitances of the gates of CMOS devices. The capacitance is realized by the thinoxide layer which separates the polysilicon layer and the substrate. However, pinholes in the oxide layer which cause DC leakage currents are an unsolved problem of this type of on-chip capacitor. IBM Technical Disclosure Bulletin, "Power Supply Decoupling in Dynamic Random Access Memory (DRAM) Trench Technology", July 1989 by Redman and Thoma shows an example how a power supply decoupling capacitor is used in a dynamic random access memory.

It is therefore an object of the present invention to provide an improved on-chip capacitor and an improved method of designing an integrated circuit chip. This problem is solved by the teaching contained in the characterizing portion of claim 1 or claim 7, respectively.

The on-chip capacitor provided by the teaching of the present invention is advantagoures as compared to prior art on-chip capacitors since it is self-repairing. If a pinhole occurs in one of the complementary cross-coupled structures which causes a leakage current, the cross- coupled structures switch to another state so that the leakage current disappears. For this purpose any circuit arrangement having a flip-flop characteristic may be used.

The control and minimization of leakage currents according to the teaching of the invention also facilitates the testing of a chip. The DC leakage currents are measured during chip-test and the chips having a leakage current above a predefined threshold value are scrabbed after this reliability test. Only very low DC leakage currents are tolerated, i.e. lesser than 100 micro amperes. Since the chip surface covered by prior art on-chip gate capacitances is relatively extended, the chances are high that the threshold for leakage currents is surpassed due to pinholes in the oxide layer of the on-chip capacitor. This makes the testing of the chip difficult.

Apart from the above described testing and quality problem, the reliability issue is also addressed by the teaching of the invention. The background is that any DC leakage current due to pinholes may increase over time and lead to functional failures in the end. If such an increase occurs in one of the cross-coupled structures of the inventive on-chip capacitor this causes to switch the entire structure into a different state so that no voltage drop occurs over the path of the leakage current.

Another advantages of the invention is that spare logic cells can be used for the realization of the on-chip capacitor. To speed up logic fixes and logic changes on- chip spare logic is heavily used especially in large CMOS chips. By means of the spare logic cells corrections can be performed very fast by only a few metal mask changes rather than redesigning the whole chip. In general, only a limited number of the spare logic cells are actually used. According to the method of designing an integrated circuit chip these spare logic cells which are not used are employed to realize the on-chip capacitor. After the design of the functional circuit elements of the chip is finished, the remaining unused spare logic cells are used for the realization of the complementary cross-coupled structures of the on-chip capacitor. Also embedded spare logic clusters of spare logic cells can advantageously be used for this purpose.

In the following one way of carrying out the invention is explained in more detail by reference to the drawing in which

Fig. 1 is a circuit diagram of one of the structures of the on-chip capacitor;

Fig. 2 is a circuit diagram of the two complementary cross-coupled structures; Fig. 3 is an equivalent circuit diagram of a leaky transistor TNA of Fig. 2;

Fig. 4 is a diagram illustrating the voltage potentials in the structure of Fig. 2 over time, developed at power on.

The circuit shown in Fig. 1 is a standard CMOS inverter. The CMOS inverter consists of two transistors 4 and 5. The two transistors 4 and 5 are of different conductivity types. Transistor 4 is a normally on p-type transistor whereas transistor 5 is a normally off n-type transistor. Thereby a complementary structure is realized. If a signal is applied to the input 1 of the inverter, the inverted signal is output at the output 2. The inverter can be build by e.g. a spare logic cell. In a spare logic cell the line 3 of the inverter would be connected by default to ground potential GND. However, in this case the spare logic cell is activated by connecting the line 3 to the power supply VDD.

By the two complementary cross-coupled inverter structures shown in Fig. 2 an on-chip capacitor according to the invention is realized. The capacitor comprises two of the inverters of the type shown in Fig. 1. The first inverter structure comprises the transistors TPA and TNA which correspond to transistors 4 and 5 of Fig. 1 respectively. The second inverting structure comprises the transistors TPB and TNB which correspond to a transistors 4 and 5 of Fig. 1 respectively. Both structures are complementary since the transistors of each structure are of complementary type, i.e. transistor TPA is a p-type transistor and transistor TNA is a n-type transistor; the same applies analogously to the transistors TPB and TNB of the second inverting structure shown in Fig. 2. The two complementary inverting structures are cross-coupled. This is accomplished by connecting the input of the first structure to the output of the second structure and vice versa:

The input la of the first structure is connected via connection 6 to the output 2b of the second structure. The input lb of the second structure is connected via connection 7 to the output 2a of the first structure.

The electronic structure of Fig. 2 corresponds to a flip- flop circuit. This structure has only two stable states. When the power supply VDD is switched on this flip-flop type circuit will switch in one of the two stable states due to slight unsymmetries between the two structures. In the following it is assumed that the power supply VDD is switched on. The leakage at power on time at transistor TNA causes switching into a stable state where the leakage is shorted. This stable state is described as follows:

The transistors TPA and TNB are switched off, the transistors TNA and TPB are switched on, the potential at the node Va between the transistors TPA and TNA equals ground GND potential and the potential Vb between the transistors TPB and TNB equals the potential VDD of the power supply. Thereby an on-chip capacitor is realized between the power supply VDD and ground GND. In this state of the circuit arrangement of Fig. 2 the capacitor is mainly realized by the capacitance of line 7 (potential Va) to VDD and the capacitance of line 6 (potential Vb) to GND. In the following it is assumed that over time a leakage current begins to develop between the gate of the transistor TNA and ground GND.

The potential at the gate of the transistor TNA equals the potential of the power supply VDD, since the transistor TPB is switched on. If a leakage current begins to occur between the gate of the transistor TNA and ground GND this will slightly pull down the potential at the gate of the transistor TNA to ground GND. This decrease in the gate potential does also occur at the gate of the transistor TPA since the two gates are interconnected. The decrease of the gate potential will slightly turn on the transistor TPA. This will slightly pull up the potential at the node Va to the potential of the power supply VDD. This increase of the potential at the node Va does also occur at the gates of the transistors of the second structure i.e. transistors TPB and TNB. The increase of the potential at the gate of the transistor TPB will slightly turn off this transistor whereas the transistor TNB will slightly turn on due to the increase of the potential. This will further decrease the potential at the node Vb and - as a consequence - the potential at the gate of the transistor TNA, where the leakage current occurs. The further decrease of the potential at the gate of transistor TNA will further turn off this transistor and cause an even further decrease of its gate potential due to the positive feedback loop.

The result of the development of a leakage current is that the entire structure of the on-chip capacitor of Fig. 2 switches into a second state. In the second state the transistors TPA and TNB are switched on whereas the transistors TNA and TPB are switched off. The potential at the node Va equals the potential of the power supply VDD whereas the potential of the node Vb equals ground GND in the second state. Since the potential at the gate of the transistor TNA equals the potential at the node Vb, there is no voltage drop between the gate of the transistor TNA and ground GND and the transistor TNA is switched off. This will stop the leakage current which occurred at the transistor TNA when the entire structure of Fig. 2 was in the initial first state. The effective capacitance of the entire structure between the voltage nodes VDD and ground remains the same in both states. Any leakage current due to pinholes occurring in one of the transistors will cause an unsymmetry in the entire circuit structure which will cause the entire structure to switch in a state where the leakage current no longer exists. This is due to the cross coupling of the two inverting structures and the positive feedback of a change of potential in an internal node which is caused by a leakage current.

Instead of the inverting structures of Fig. 2 any other kind of structures can be combined which provides a circuit having a flip-flop characteristic and which does provide for the required positive feedback due to the occurrence of a leakage current. Alternative structures are for example NAND or NOR-gates which are cross- coupled.

Fig. 3 shows the equivalent circuit diagram of the defective transistor TNA of Fig. 2. The leakage current occurring between the gate of the transistor TNA and ground GND is symbolised by the current source JL. The current JL is reduced to zero when the entire structure of the Fig. 2 switches into the second state so that the potential at the node Vb equals ground GND.

Fig. 4 shows the situation which occurs when the power supply VDD of the chip is switched on. The abscissa of the diagram shown in Fig.4 is representative of the time t. The time t is defined to be zero when the power supply VDD is switched on. Before the time t = 0 the power supply VDD is switched off. The ordinate of the diagram shown in Fig. 4 is representative of the potentials at the nodes Va and Vb. The upper curve in the diagram of Fig. 4 is representative of the development of the potential at the node Va and the lower curve in the diagram is representative of the development of the potential at the node Vb. When the power supply VDD is switched on at time t = 0 this will pull up both the potential at nodes Va and Vb. However the potential at node Vb will not build up as quickly as the potential at the node Va due to the leakage current occurring at the transistor TNA. This unsymmetry in the entire structure of Fig. 2 will be amplified by the positive feedback loop provided by the cross-coupling of the two inverting structures. The cross-coupling of the two structures will cause the entire structure at the time t = 1 to switch into the second state. This occurs abruptly when both potentials at nodes Va and Vb have reached a certain value big enough to cause the transistors of the entire structure to be significantly influenced by there respective gate potential. The mechanics of the switching operation is basically the same as described with respect to the situation when a leakage current begins to develop when the power supply VDD is already switched on (cf. the description referring to Fig. 2).

In practice a plurality of the circuits shown in Fig. 2 will be realized on one chip. This results in a plurality of on-chip capacitors connected in parallel. In an equivalent circuit diagram the combination of these on- chip capacitors connected in parallel between power supply VDD and ground GND results in one on-chip capacitor representing the sum of all the capacitances being realized by the plurality of the circuits of the type shown in Fig. 2.

Claims

C A I M S

1. On-chip capacitor comprising at least two complementary cross-coupled structures, said structures switching from a first to a second state in response to a leakage current in one of said structures.

2. On-chip capacitor according to claim 1 charactered in that at least one of said structures being an inverter, NAND or NOR logic gate.

3. On-chip capacitor according to claim 1 or 2 characterized in that said complementary structures are CMOS structures.

4. On-chip capacitor according to anyone of the preceding claims characterized in that said chip is a logic chip, preferably such as a microprocessor, a PLA or a sea of gates, and that said structures are spare logic cells.

5. Integrated circuit chip, such as a microprocessor or a memory chip, having an on-chip capacitor according to anyone of the preceding claims.

6. Computer system comprising an integrated circuit chip according to claim 5.

7. A method of designing an integrated circuit chip having spare logic cells comprising the steps of

a) designing the functional circuit elements of said chip; using otherwise unused spare logic cells for the design of an on-chip capacitor according to anyone of the claims 1 to 4.