WO1996030821A1 - Generateur d'impulsions d'horloge variables - Google Patents

Generateur d'impulsions d'horloge variables Download PDF

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Publication number
WO1996030821A1
WO1996030821A1 PCT/JP1996/000814 JP9600814W WO9630821A1 WO 1996030821 A1 WO1996030821 A1 WO 1996030821A1 JP 9600814 W JP9600814 W JP 9600814W WO 9630821 A1 WO9630821 A1 WO 9630821A1
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WO
WIPO (PCT)
Prior art keywords
unit
clock frequency
clock
act
switching
Prior art date
Application number
PCT/JP1996/000814
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English (en)
Japanese (ja)
Inventor
Yasuki Sasaki
Original Assignee
Yasuki Sasaki
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yasuki Sasaki filed Critical Yasuki Sasaki
Publication of WO1996030821A1 publication Critical patent/WO1996030821A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

Definitions

  • variable clock generation that can dynamically change the operation clock to each processing unit constituting the system according to the operating state of the system is provided.
  • a digital device such as a personal computer includes a plurality of processing units that operate on various clocks.
  • the processing part of an integer operation or a floating-point operation using an internal register is the best clock. It is said that it operates at a frequency, and the word store etc. of the subsequent instruction executed during the arithmetic processing operates at a relatively low clock frequency. This is done or, for example, in a notebook-type personal computer driven by a territory drive, the internal low-speed I / O device (8 Bit mode power) at 1 MHz, system path at 8 MHz, bitmap image output processing, etc.
  • the part that performs heavy processing is 1
  • a digital processing device In a digital processing device, its power supply current increases in proportion to the operating clock frequency (per unit time to the fi component of the power supply circuit inside the device). Charging / discharging frequency For example, if the 1 MHz clock digital processing card is operating with a 5 V 10 O mA power supply, the operating clock When the power is increased to 8 MHz, the power supply quiescent current increases to 800 mA. When the consumption current increases, the heat generated in the portion where the current flows increases, and in some cases, measures for heat dissipation are required. In addition, battery operated devices also have the problem of shortening the continuous usable time of the battery.
  • High-speed clocks Not all places that require high-speed clocks need high-speed clocks, but when do you need high-speed clocks? When it is not clear, always supply the high-speed clock to the high-speed processing section and always supply the low-speed clock to the low-speed processing section.
  • the clock in the low-speed processing part is appropriately stopped.
  • the i-speed processing part can be operated even in the period when the high-speed processing is not required. Since the large power supply current continues to be consumed while receiving the quick cook, it is difficult to effectively suppress the power supply current.
  • the purpose of this invention is to supply power only to the necessary parts only when needed and to reduce power consumption without deteriorating system performance.
  • An object of the present invention is to provide a variable clock generator and a variable clock generation method capable of suppressing a current.
  • the first clock frequency (high-speed clock CLK0) or the second clock frequency (low-speed clock CLK1) must be used.
  • a switching signal (Act) for switching a clock frequency is generated when a predetermined command is input;
  • the first unit (3 1) The first clock frequency (CLK0) is supplied to one of the second units (32) and the first unit.
  • the operation clock to each of the processing units (first and second units) that configure the system according to the operating status of the system (contents of the input command) is dyna- sized.
  • the high-speed clock (CLK0) can be supplied only to the necessary parts when needed (the first operating environment).
  • the power consumption current can be suppressed without lowering the performance of the system.
  • FIG. 1 is a block diagram showing a configuration of a system including a variable clock generator according to one embodiment of the present invention.
  • FIG. 2 is a timing chart illustrating the operation of the embodiment of FIG.
  • FIG. 3 is a block diagram showing a configuration of a system including a variable clock generation device according to another embodiment of the present invention.
  • FIG. 4 is a truth table illustrating the operation of the frequency divider of the embodiment of FIG.
  • FIG. 5 is a timing diagram illustrating the operation of the embodiment of FIG.
  • FIG. 6 shows a variable clock according to still another embodiment of the present invention.
  • FIG. 2 is a block diagram showing a configuration of a system including a generator.
  • FIG. 7 is a flowchart illustrating the operation of the embodiment of FIG. Desired embodiment
  • variable power generation device and a variable power generation method according to an embodiment of the present invention will be described.
  • FIG. 1 shows a configuration of a system including a variable clock generator according to an embodiment of the present invention.
  • FIG. 2 is a timing chart for explaining the operation of this device.
  • the input clock CLK0 is obtained from a system clock generation circuit (not shown).
  • this system clock generation circuit reduces the output of the 32 MHz crystal oscillator and its output. It can be configured with a flip-flop (1Z2 divider) that shapes the waveform into a square wave with a 50% ratio. If this system clock generation circuit is composed of CMOS circuits, the power consumption current of this generation circuit can be very small, so this CMOS clock generation circuit can be used. The oscillation circuit of the generator circuit itself is not stopped.
  • the clock CLK0 of the above system clock generating circuit power is supplied to the highest priority circuit 10 as a timing signal, and the frequency is divided by the frequency dividing circuit. Input to 20.
  • the highest priority circuit 10 Upon receiving a processing start instruction from a main CPU card (not shown), the highest priority circuit 10 executes an internal program at the timing of the clock CLK0. When a predetermined condition (highest priority condition) is satisfied, an active signal Act is generated. If the PU does not need to operate at the maximum speed (for example, waiting for a keyboard input from the user) for a predetermined period of time (for example, 1 minute), a certain highest priority condition is satisfied. The instruction to be satisfied and to reduce the frequency of the system clock is input to the highest priority circuit 10. Then, the highest priority circuit 10 generates the active signal Act (at time ts in FIG. 2).
  • a predetermined condition for example, waiting for a keyboard input from the user
  • a predetermined period of time for example, 1 minute
  • the active signal A ct is input to the frequency divider 20.
  • the frequency divider circuit 20 outputs the signal “During the period during which the active signal Act corresponding to the instruction of decreasing the system clock frequency j is received.
  • the frequency divider circuit 20 Upon receiving the active signal Act (ts), the frequency divider circuit 20 turns on the clock CLK0 at the clock timing of the input clock CLK0. Divided individually, timing shifted by one clock
  • clocks CLK 1 to CLK 3 divided by 1 Z 2 are generated.
  • the low-speed clocks CLK1 to CLK3 obtained in this way are the first operation units 31 to 3 that constitute the operation unit group 30 respectively. It is supplied to the unit 33.
  • the first operating unit 31 to the third operating unit 33 each have a small power consumption current due to the supplied low-speed clocks CLK1 to CLK3. Accordingly, predetermined processing is executed at a necessary and sufficient operation speed.
  • the “highest priority circuit operation” means that the system clock frequency of a specific circuit part is reduced, and there is another circuit that operates with the highest priority. .
  • this particular circuit part Even if it operates with the clock and there is no problem (or it is more advantageous to operate with a high-speed clock because of the operation speed of other circuit parts)
  • the system clock frequency to this specific circuit part is reduced.
  • the clock frequency is lower than the specific circuit part where the clock frequency is lowered. The circuit part that is not determined is given priority in terms of operating performance.
  • the “highest priority condition” here means the first operation unit 31 to the third operation unit 33 irrespective of the operation status of other circuits not shown. It is a good condition to divide the operation clocks CLK1 to CLK3 supplied to the divide-by-2.
  • the operation unit 31 when the operation unit 31 is operating with a clock of 16 MHz, the maximum lms (mi) is required from the start of a certain process until the processing result is obtained. (Received). For a program running on the main CPU, if you request this processing and wait more than 2 ms before obtaining the result, Operation unit 3 1 Power ⁇ Operation at 8 MHz clock will not work. In such a case (waiting for 2 ms), the “highest priority condition” is satisfied, and the highest priority circuit 10 activates the input clock CLK0 by dividing it by 12. Generates the active signal Act.
  • the ⁇ highest priority conditions '' are not fixed contents, but can be changed as appropriate depending on the system configuration and the contents of running programs. It is time to operate the first operation unit 31 to the third operation unit 33 again with the high-speed clock CLK0. --
  • the highest-priority circuit 10 sends the processing end output to the main CPU (not shown).
  • the processing start instruction input the processing start instruction to the highest priority circuit 10 (to reduce the clock and save the operation).
  • the highest-priority circuit 10 determines the “highest-priority condition” according to the content of the instruction.
  • the active signal Act is output.
  • the power supply quiescent current is reduced by reducing the clock frequency.
  • the above embodiment has the following functions and effects.
  • FIG. 3 shows a configuration of a system including a variable clock generation device according to another embodiment of the present invention.
  • the system clock generation circuit power and the input clock CLKO are used as a timing signal as the first and highest priority circuits 101 and the second highest priority circuit.
  • the signal is supplied to a divider circuit 20 while being given to 102.
  • the dividing circuit 20 divides the input clock CLK0 according to the content of the combination of the active signals Act1 and Act2, and generates four types of clocks CLK. 1 to CLK 4 are applied to four operation units 31 to 34, respectively. Each of the operation units 31 to 34 executes its own processing at a speed corresponding to the frequency of the given clock CLK1 to CLK4. .
  • the highest priority circuit 101 executes the internal program at the timing of the clock CLK0, and executes a predetermined operation.
  • the condition (the highest priority condition 1) is satisfied, the active signal Act 1 is generated (time ts 1 in FIG. 5).
  • the highest priority circuit 102 receives the second processing start instruction # 2, and the internal processing is performed at the timing of the clock CLK0.
  • the program is executed, and when a predetermined condition (highest priority condition 2) is satisfied, an active signal Act 2 is generated (time ts 2 in FIG. 5).
  • the active signals Act 1 and Act 2 are input to the frequency divider 20.
  • the frequency divider circuit 20 receives the combination of the active signals Act1 and Act2 corresponding to the instruction of the content "The system clock frequency is reduced.” During a certain period (after ts1 in Fig. 2; the period when the first and second highest priority conditions are satisfied), the circuit enters the highest priority circuit operation.
  • Figure 4 is a truth table showing the relationship between the combination of the active signals Act1 and Act2 and the four types of frequency division operations on clock CLK0. It is. If the combination of the active signals Act 1 and Act 2 determined by the contents of the processing start instructions # 1 and # 2 is 0, 4 types of clocks The division ratios for CLK1 to CLK4 are all ⁇ 1 ”. That is, the frequency of each of the clocks CLK1 to CLK4 is the same as that of the input clock CLK0.
  • each of the clocks CLK1 to CLK4 has a frequency of 1Z2 of the input clock CLK0.
  • the combination of the active signals Act1 and Act2 is 0Z0, so the division ratio is flj
  • the frequency of the clocks CLK1 to CLK4 matches the input clock CLK0.
  • the division ratio is ⁇ 2 ”because the combined force of active signals A ct 1 and A ct 2 is 1 0. Then, the clocks CLK1, CLK2, CLK3, and CLK4 are used, and their frequency changes to 1Z2 of the input clock CLK0 (time tl, t2, t3, t4).
  • the CPU gives the processing start instructions # 1 and # 2 to the highest priority circuits 101 and 102 as appropriate during the execution of the program.
  • Each of the operation units 31 to 34 executes its own processing at a speed corresponding to the frequency of the clock CLK1 to CLK4 that is appropriately changed. Due to the dynamic change (reduction) of the switching frequency, the power dissipation (power consumption) of the operating unit group 30 as a whole can be reduced. it can .
  • the above embodiment has the following functions and effects.
  • the present invention can be applied to a complex system composed of a plurality of units operating in different clocks.
  • FIG. 6 shows a configuration of a system including a variable clock generator according to still another embodiment of the present invention.
  • FIG. 7 is a flowchart for explaining the operation of this device.
  • the instruction code from the CPU (not shown) is input to the instruction decoder 110 inside the highest priority circuit 10.
  • the decoder 110 generates three types of active signals Actl to Act3 in a combination corresponding to the content of the input instruction. These active signals A ctl to Act 3 are connected to the selection circuit 120 composed of a gate array and the like, and to the AND circuit in the frequency dividing circuit 20. It is given to the first input terminals of the gates G 21 to G 23. The clocks before the division are input to the second input terminals of the AND gates G21 to G23 in the frequency dividing circuit 20.
  • the AND gate G 21 connects the input clock CLK 0 to the first frequency dividing circuit 2 only when the active signal Act 1 is at the output level 1 j level.
  • the AND gate G 22 supplies the input clock CLK 0 only when the active signal Act 2 is at the 1 ⁇ j level.
  • the signal is supplied to the second frequency dividing circuit 22, and the AND gate G 2 3 receives the input clock CLK only when the active signal Act 3 is at the 1 j level.
  • 0 is supplied to a third frequency dividing circuit 23.
  • the first to third frequency divider circuits 21 to 23 are selected from the selection circuit 120 ⁇ Divider circuit operation is performed only when 1 J level selection signals SL 1 to SL 3 are received.
  • the level of each of the selection signals SL1 to SL3 is determined by a combination of the active signals Actl to Act3.
  • the result of decoding the instruction input to the decoder 110 (step ST10 in FIG. 7) and the result of the integer operation unit (ALU) 31
  • the instruction is an execution instruction (# 1 in step ST12)
  • a signal SL 1 for setting the frequency division ratio of the frequency dividing circuit 21 to ⁇ 1 J is supplied to the circuit 21 (step ST 14).
  • the integer operation unit 31 operates with the fastest clock CLK 1 ( ⁇ CLK 0).
  • the decoded instruction (the operation speed of the integer operation unit 31 is given the highest priority) is, for example, the data (memory or If a load Z store instruction (to the register) is included and this instruction does not need to be executed at the highest speed, the divider circuit 22 will be driven by the signal SL 2.
  • step ST16 the clock input to the frequency divider circuit 23 is stopped (step ST16), and the floating-point operation unit (FPU) 33 stops operating (this step). In this case, unit 33 consumes very little power.)
  • the decoded instruction at that time (the operation speed of the load store control unit 32 is given the highest priority) is, for example, an integer operation instruction. Therefore, if it is not necessary to execute this instruction at the highest speed, the frequency divider 21 sets the frequency division ratio to “2” by the signal SL1. Step ST20). As a result, the power supply current to the integer operation unit 31 is reduced.
  • the decoded instruction (in which the operation speed of the load / store control unit 32 is given the highest priority), for example, executes a floating-point operation instruction. If this instruction does not need to be executed at the highest speed, the frequency divider 23 is set to the frequency division ratio ⁇ ⁇ 2 by the signal SL3 (step ST2). ST20). As a result, the power supply current to the floating-point arithmetic unit 33 is reduced.
  • step ST10 The result of decoding the instruction input to the decoder 110 (step ST10) and the execution instruction of the floating-point operation unit (FPU) 31
  • the integer operation unit (ALU) 31 stops operating (in this case, And the unit 31 hardly consumes power).
  • the above embodiment has the following functions and effects.
  • a dynamic unit that can operate at the highest clock speed can be specified.
  • the clock of the unit that does not need to operate at the highest speed clock is appropriately reduced, and the operation of the instruction content is completely unnecessary.
  • the clock can be stopped for a unit that does not work (if the error does not occur even if the unit is stopped), then the system as a whole can be stopped. It is possible to effectively reduce the power loss and power consumption of the entire apparatus without substantially reducing the performance. According to this invention, the following effects can be obtained.
  • the operation clock to each processing unit (31 to 33) configuring the system according to the operating status of the system (contents of the input command) is daisy-chained.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Dans un générateur d'impulsions d'horloge destiné à fournir les impulsions d'horloge à une unité (31) fonctionnant au moyen d'une impulsion d'horloge rapide CLK0 ou d'une impulsion d'horloge lente CLK1, et à une unité (32) fonctionnant au moyen de CLK0 ou CLK1, un générateur d'impulsions d'horloge variables de l'invention présente un circuit (10) destiné à générer un signal de commutation Act, lequel commute une fréquence d'impulsions d'horloge lorsqu'une instruction prédéterminée lui est transmise, et un circuit (20) d'alimentation en impulsions d'horloge variables destiné à transmettre CLK0 à l'unité (31) et CLK1 à l'unité (32) dans un premier environnement d'exploitation (fonctionnement du circuit en priorité absolue) déterminé en fonction du contenu de l'instruction et du contenu du signal Act, et à transmettre CLK0 aux deux unités (31 et 32) dans un second environnement d'exploitation (circuit ne fonctionnant pas en priorité absolue) déterminé en fonction du contenu de l'instruction et du contenu du signal Act.
PCT/JP1996/000814 1995-03-31 1996-03-28 Generateur d'impulsions d'horloge variables WO1996030821A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7/75855 1995-03-31
JP7075855A JPH08272479A (ja) 1995-03-31 1995-03-31 可変クロック発生装置

Publications (1)

Publication Number Publication Date
WO1996030821A1 true WO1996030821A1 (fr) 1996-10-03

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WO (1) WO1996030821A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3880310B2 (ja) 2000-12-01 2007-02-14 シャープ株式会社 半導体集積回路
WO2012026025A1 (fr) * 2010-08-26 2012-03-01 ルネサスエレクトロニクス株式会社 Dispositif et système de traitement de données
JP5695895B2 (ja) * 2010-12-16 2015-04-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4914056A (fr) * 1972-05-16 1974-02-07
JPH03286213A (ja) * 1990-03-30 1991-12-17 Matsushita Electric Ind Co Ltd データ処理装置
JPH04153715A (ja) * 1990-10-17 1992-05-27 Nec Corp マイクロコンピュータ
JPH05250062A (ja) * 1992-03-04 1993-09-28 Fujitsu Ltd クロック供給装置
JPH0854955A (ja) * 1994-08-10 1996-02-27 Fujitsu Ltd クロック信号発生回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4914056A (fr) * 1972-05-16 1974-02-07
JPH03286213A (ja) * 1990-03-30 1991-12-17 Matsushita Electric Ind Co Ltd データ処理装置
JPH04153715A (ja) * 1990-10-17 1992-05-27 Nec Corp マイクロコンピュータ
JPH05250062A (ja) * 1992-03-04 1993-09-28 Fujitsu Ltd クロック供給装置
JPH0854955A (ja) * 1994-08-10 1996-02-27 Fujitsu Ltd クロック信号発生回路

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