WO1996029803A1

WO1996029803A1 - Asynchronous expansion bus for a communication network

Info

Publication number: WO1996029803A1
Application number: PCT/US1996/000823
Authority: WO
Inventors: Vadim Tsinker
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1995-03-20
Filing date: 1996-01-23
Publication date: 1996-09-26

Abstract

An expansion bus used in conjunction with ethernet repeaters (24, 124, 224) having at least one source repeater and a plurality of destination repeaters wherein the source repeater transmitting information is in control of the frequency by which information is transmitted such that the transmitted information is done in an asynchronous fashion with respect to the destination repeaters.

Description

ASYNCHRONOUS EXPANSION BUS FOR A COMMUNICATION NETWORK

Field of the Invention

The present invention relates generally to communication networks, and more particularly to a managed asynchronous expansion bus for use with ethernet repeaters.

BACKGROUND OF THE INVENTION

There presently is a need for an asynchronous expansion hub for use with repeater networks. A local area network (LAN) is a specific type of network that can support peer-to-peer communications over distances ranging from a few meters to several kilometers. A specific type of LAN is the ethernet, where information from multiple users travels through the network through repeaters that transmit the information over its ports.

In ethernet networks, information packets are transmitted through the network via repeaters that receive information on one of its ports and retransmit the information to the other ports in the hub. In a typical ethernet network, the number of data lines connected to a single repeater hub can greatly exceed the number of data lines that can be physically placed inside a single repeater chip. Thus, the ability to construct a repeater hub from several repeater chips is necessary. The system bus within a hub is either synchronous or asynchronous in nature. Hubs having a synchronous system bus generally use a single central clock which controls the overall operation of the hub. One problem associated with this type of hub is that a complex clock distribution scheme is required to ensure proper operation of the hub. If the central clock malfunctions, data transfer throughout the hub is adversely affected. If the board containing the central clock breaks or malfunctions, the entire hub will become inactive. Another problem associated with hubs having synchronous buses is that as more repeaters are connected to the hub, the load on the central clock becomes larger, thereby causing the clock signal to become skewed. This skewed clock signal manifests itself into critical timing errors that can cause hub and network malfunction.

A further problem associated with hubs having synchronous buses is propagation delay with respect to the source and destination repeaters that transfer information throughout the hub. The greater the propagation delay through the synchronous bus, the greater the possibility of not meeting the setup and hold time of the system clock. A problem associated with asynchronous hubs is system bus integrity errors occurring when multiple destination repeaters do not extend transmission port activity in response to receiving data packets that are less than the required IEEE 802.3 standard length of 96 bits. This situation occurs when one or more of the destination repeaters fails to recognize a new collision present on the system bus. A collision occurs when more than one repeater requests access to the system bus at the same time. The repeaters that recognize the collision situation extend their transmission activity in response to the collision situation. The repeaters that do not recognize the collision situation do not extend transmission activity. Thus, you have destination repeaters transmitting different responses to the same event (i.e. a collision) which is incorrect.

SUMMARY OF THE INVENTION The present invention solves the aforementioned and related problems associated with data transmission over communication networks. Disclosed herein is an expansion bus for use with ethernet repeaters that provides asynchronous data transmission through a communication hub. The expansion bus consists of means for transmitting information, means coupled to the transmitting means for receiving and re¬ transmitting the information and arbiter means that is coupled to the transmitting means and the receiving means, providing for transmission of the information in an asynchronous manner.

An advantage of the present invention is that a complex clock distribution scheme is not required for proper operation of the network. Another advantage of the present invention is that no central clock board is necessary within the system.

A feature of the present invention is the ability to maintain the system without interruption.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other advantages and features of the present invention will become apparent from the following description of the preferred embodiment, taken in conjunction with the accompanying drawings, where like numbers represent like elements in which:

Figure 1 is schematic block diagram of the asynchronous expansion bus according to the present invention.

Figure 2 is a logic diagram of the expansion bus components according to the present invention.

Figure 3 is a timing diagram depicting normal data transmission of the circuit shown in Figure 2. Figure 4 is a timing diagram depicting a receive/transmit collision on a circuit shown in Figure 2.

Figure 5 is a timing diagram depicting a transmit collision between several repeaters of the network according to the present invention.

Figure 6 is a timing diagram depicting extending data transmission by the source repeater according to the present invention.

Figure 7 is a alternate timing diagram depicting extending data transmission by the source repeater according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Figure 1 illustrates an ethernet hub 10 using the asynchronous expansion bus, according to the present invention. A plurality of repeaters 24, 124 and 224 labelled Repeater l to Repeater N, respectively, are shown where N is a positive integer greater than l. Each of the plurality of repeaters is formed on a single integrated circuit chip. Three repeaters are shown in Figure l, however, it would be readily apparent to one skilled in the art that more than three repeaters can be connected to a expansion bus. The repeaters 24, 124 and 224 are each connected to an arbiter 20 via request lines 30, 37 and 38, respectively, which are asserted (active low) whenever the representative repeater wants to transmit data over the bus. An acknowledge signal on line 39 connects the arbiter 20 to the individual repeaters 24, 124 and 224, and is asserted (active low) to acknowledge a transmission request by one of the repeaters on lines 30, 37 or 38, thereby permitting the requesting (i.e. transmitting) repeater to transmit information and the other (i.e. receiving) repeaters to receive the information. The arbiter 20 is made from an AMD22V10 programmable array logic device (PAL) , manufactured by Advanced Micro Devices, Inc. of Sunnyvale, California also the assignee of the present invention. The operation of a programmable array logic device (PAL) is known to those of ordinary skill in the art and will not be discussed further herein. The repeaters 24, 124 and 224 also are connected to one another and the arbiter 20 via collision line 34.

Also stemming from the repeaters 24, 124 and 224 are a bi-directional DATA line 31, a FRAME line 32, an ECLK line 33 and a JAM line 35. The DATA line 31, FRAME line 32, ECLK line 33, acknowledge line 39 and request lines 30, 37 and 38 comprise the expansion bus of the present invention. The DATA line 31 is used to transmit information over the bus as well as to signal the type of collision within a single repeater in combination with a JAM signal on line 35. Further stemming from the repeaters 24, 124 and 224 are a plurality of bi-directional ports Px, Py and Pz, respectively used to transmit information among the repeaters. For example, repeater 24 has a plurality of ports, Px, numbered 1 to N where N is a positive integer greater than 1. Repeater 1, labelled 24, through repeater N, labelled 224, are substantially identical, and accordingly, only the first repeater 24 will be described in greater detail hereinafter. It is to be understood that the description of the first repeater 24 applies equally to the other repeaters aside from the differences pointed out below.

Also, connected to the expansion bus, is an external controller device 22 which may be used in an alternate embodiment of the present invention, that can transmit information over the bus. When the controller 22 is transmitting information and line 36 is asserted, the expansion bus operating statistics are recorded so that all unique port activity becomes managed. When the information on the bus consists of repeater to repeater communications, the controller 22 is not transmitting and the expansion bus activity is unmanaged wherein each repeater connected to the bus collects management statistics from its own ports. Figure 2 further details the first repeater 24 shown in Figure 1. A data valid signal, which is asserted whenever there is valid data to be sent to the bi-directional line 31 of the repeater 24 is presented as an input to a first tri-state buffer 52 on line 200. Also connected to the first tri-state buffer 52 is the enable transmission to expansion bus signal provided on line 102. The output of the first tri-state buffer is the FRAME data signal on line 32, which is active throughout the entire period of data transmission. A second tri-state buffer 54 has provided at its input a data clock signal on line 202 which is inverted by inverter 60 and transmitted to the second tri-state buffer 54 on line 61. For purposes of illustration, in the most preferred embodiment of the present invention, the data clock signal has a frequency of ten (10) megahertz. In response to the enable transmission to expansion bus signal on line 102 and the inverted data clock signal on line 61, the second tri-state buffer 54 provides the expansion bus data clock on line 33 which is transmitted with the data present on line 31 when the data is valid. The information that is transmitted by the repeater 24 is provided by the output of a third tri-state buffer 56 on line 31. The input to the third tri-state buffer 56 comprise the logic combination of the internal data signal on line 204 connected as one input of an AND gate 86 and the internal transmission collision signal on line 206 inverted by inverter 90, the output of which is provided as the second input to the AND gate 86. The output of the AND gate 86 is provided as a first input to NAND gate 62. The second input to the NAND gate 62 is provided by the internal receive collision signal present on line 208. The output of the NAND gate 62 is provided as the input to the third tri-state buffer 56 on line 63. The second input to the third tri- state buffer 56 is provided by the enable transmission to expansion bus signal on line 102. The internal transmit collision signal on line 206 is also provided as a first input to a second NAND gate 64. The second input to the second NAND gate 64 is provided by the internal receive collision signal on line 208 whose output is provided as the primary input to a fourth tri-state buffer 58 on line 65. The output of the fourth tri-state buffer 58 is the JAM signal, on line 35, which represents incoming activity on more than one of the ports, Px, of the repeater 24 and also signals a receive collision on a single port within the repeater 24.

A request signal, which is asserted whenever the repeater 24 wants to transmit information over the expansion bus, is provided by the output of a NAND gate 66 on line 30. The first input to the NAND gate 66 is provided by a carrier sense signal on line 112 which is asserted whenever there is information present on any of the input ports, Px, of the repeater 24. The second input to the NAND gate 66 is provided by the extended carrier sense signal present on line 110 which is asserted whenever the information to be transmitted on line 31 is not at least 96 bits in length as required by the IEEE 802.3 standard. An acknowledge signal on line 39 is inverted by inverter 88 whose output is presented to a first synchronization latch 40 which synchronizes the acknowledge signal on line 39 to a repeater clock 3 which, preferably has a frequency over a range of at least 9.99 megahertz to 10.01 megahertz, and optimally ten (10) megahertz. The synchronized signal on line 69 is then used as a first input to an AND gate 68 and an AND gate 70. The second input to AND gate 68 is provided by an inverted carrier sense signal present on line 113. The second input to AND gate 70 is provided by the carrier sense signal provided on line 112. The output of the first AND gate 68 is the receive enable from expansion bus signal on line 100. The output of the second AND gate 70, is the enable transmit to expansion bus signal of the repeater 24 on line 102.

The external transmit collision signal on line 104 which notifies the repeater 24 of an external transmit collision condition, defined as more than one of the input ports on different repeaters within the same hub having information on them, is provided by the output of an OR gate 72. The first input to the OR gate 72 is provided by a collision signal on line 34 which is inverted by inverter 116 whose output is provided to a second synchronization latch 42 via line 117, which synchronizes the collision signal on line 117 to the repeater clock 3, whose output is provided as the first input of the OR gate 72 on line 71. The second input to the OR gate 72 is provided by the data signal present on line 31 synchronized to the repeater clock 3 via a third synchronization latch 44 whose output, on line 73, is inverted at inverter 78. The output of inverter 78 is provided as a first input to an AND gate 76 on line 75. The second input to the AND gate 76 is provided by the JAM signal on line 35 synchronized to the repeater clock 3 by a fourth synchronization latch 46, the output of which, on line 77, is the second input to AND gate 76. The output of the AND gate 76 is provided as the second input to OR gate 72.

The external receive collision signal that notifies the repeater 24 of an external receive collision, defined as one input port on another repeater in the same hub 10 having a receive collision, is provided on line 106. The external receive collision signal on line 106 is provided by the output of an AND gate 74. The first input to the AND gate 74 is provided by the collision signal on line 34 inverted by inverter 116 whose output is provided as an input to the second synchronization latch 42. The output of the second synchronization latch 42 is provided as an input to inverter 118. The output of the inverter 118 is provided as the first input to AND gate 74 on line 119. The second input to the AND gate 74 is provided by the synchronized data signal on line 73. The third input to the AND gate 74 is provided by the synchronized JAM signal present on line 77.

When the data present on line 31 is not the required minimum length of 96 bits (per IEEE standard 802.3), the extended carrier sense signal on line 110 is used to extend the request signal present on line 30 to 96 bits. The extended carrier sense signal on line 110 is provided by the logical ORing of the carrier sense signal present on line 112 and a count signal present on line 108 at the OR gate 80. The output of the OR gate 80 is provided as the enable input to a counter 50 on line 81. The output of the OR gate 82 is provided as the clear input of the counter 50 on line 83. The first input to the OR gate 82 is provided by an idle signal on line 111. The second input to the OR gate 82 is provided by a counter reset signal on line 115. The first output of the counter 50, on line 109, signifies that the data on line 31 is the required minimum length. The second output of the counter 50, on line 108, signifies that the data on line 31 is less than the required length. When this occurs, the extended carrier sense signal on line 110 is asserted.

The operation of the asynchronous expansion bus of the present invention will now be discussed with reference to Figures 3-7. For the following discussion, repeater 24 is assumed to be the transmitting repeater with repeaters 124 and 224 operating as receiving repeaters.

Normal transmission of data over the expansion bus is illustrated in Figure 3. When information is present on an input port Px of the repeater 24, a carrier sense signal is asserted on line 112 which activates the counter 50. When the carrier sense signal is asserted, the request signal on line 30 is asserted at time Tl thereby requesting the arbiter 20 for access to the expansion bus. The arbiter 20 responds by sending out an acknowledge signal on line 39 at a subsequent time T2 to all the repeaters connected the expansion hub 10. The repeater 24, that transmitted the request signal, is then placed in a transmit mode and gains control of the expansion bus by asserting its transmit to expansion bus enable signal on line 102. The other repeaters coupled to the hub 10 enter a receive mode for receiving the data transmitted on line 31 by asserting the enable receive from expansion bus signal on line 100. At this point repeater 24 is in complete control of the information transfer over the bus. The data clock signal of repeater 24, on line 202, is toggling to provide clocking information for the data on line 31. The frame signal on line 32 is asserted throughout the period of actual data transmission. After transmission is complete, the repeater 24 releases its request line 30. The arbiter 20, in response to the repeater 24 releasing its request line 30, then de- asserts the acknowledge signal on line 39 signifying completion of the transmission.

When two or more of the input ports of a repeater have information present on them, a collision has occurred with respect to that particular repeater. This situation is discussed below with reference to Figure 4. The carrier sense signal is transmitted on line 112 to both NAND gate 66 and OR gate 80, signifying data present on the input ports Px of the repeater 24. The signal on line 112 also activates the counter 50. With a carrier sense signal present on line 112, the request line 30 is asserted signifying to the arbiter 20 that the repeater 24 wants to transmit data over the expansion bus. This occurs at time T4. The arbiter 20 responds by transmitting the acknowledge signal on line 39 to all the repeaters connected to the hub 10, thus placing the repeater 24 in a transmit mode and giving it control of the expansion bus with the other repeaters being placed in a receive mode. With more than one input port Px having information present, the internal transmission collision signal on line 206 is asserted. Because the repeater 24 is in the transmit mode (line 102 asserted) , the JAM signal on line 35 is asserted at time T6. This notifies the other repeaters connected to the bus that a collision between input ports on a single repeater has occurred. During this time a constant value of 0 is present on line 31. In the case of a receive collision on a single repeater, a constant value of 1 is present on line 31 along with the JAM signal on line 35 being asserted. After the collision situation has ended (information is no longer present on more than one input port) , repeater 24 releases its request signal on line 30 thus causing arbiter 20 to drop the acknowledge signal on line 39.

Figure 5 illustrates the timing of the repeater control signals when handling a transmission collision between several repeaters. This occurs when two more repeaters have incoming activity present on its input ports and request the arbiter 20 for control of the bus before any of the repeaters complete its transmission. As shown in Figure 5, three repeaters assert their request lines request 1, request 2 and request 3 at times T7, T9, and TlO, respectively. After the first repeater (i.e. repeater 24) requests access to the bus by asserting its request line 30, the acknowledge signal is sent out by the arbiter 20 on line 39. When the second repeater (i.e. repeater 124) requests access to the bus by asserting its request line 37 at time T9, the arbiter 20 releases the acknowledge signal on line 39 and the collision signal on line 34 becomes asserted at time T9, indicating a transmit collision between multiple repeaters on the network. Once a collision between multiple repeaters occurs, all repeaters within the hub 10 assert there respective external transmit collision signal on line 104, which notifies the remaining repeater logic of an external transmit collision situation. As the repeaters back off the bus, the arbiter 20 releases the collision signal on line 34 and reasserts the acknowledge signal on line 39 with control of the bus being given to the repeater still requesting the bus. All repeaters connected to the hub 10 remain in a receive collision state or a one port left condition, even though the collision signal on line 34 has been de-asserted, until the last repeater backs off.

The transmission of information can be extended either by the transmitting repeater or the receiving repeater. In the event of the receiving repeater extending the transmission, expansion bus activity ceases as soon as the information packet transmission is complete. This may cause incorrect information being transmitted if the packet is less than the minimum 96 bits in length or if a collision occurs during transmission. For example, if the transmitting repeater enters a transmit collision, it will cause a transmission collision on the expansion bus for as long as this condition lasts on the transmitting repeater. Per IEEE 802.3, all repeater output ports must retransmit at least 96 bits of data. If individual receiving repeaters are allowed to extend retransmission, they may retransmit data differently based on them detecting the arbiter COL glitch during time T13-T12 (Figure 6) , which may be less than the duration of the repeater cycle time. If the arbiter COL glitch during time T13-T12 (Figure 6) is less than 100 ns long, then the synchronization latch 42 (Figure 2) may not latch the condition since the COL signal (Figure 3) is optimally operating at a frequency of 10 megahertz. In the preferred embodiment of the present invention, such situations are prevented by having the transmitting repeaters extend the transmissions over the expansion bus.

Figures 6 and 7 illustrate how having the transmitting repeater extend transmission activity, prevents expansion bus errors.

As shown, repeater 1, repeater 2 and repeater 3 represent the request lines for three transmission repeaters, respectively. Repeater 4 and repeater 5 represent receiving repeaters. At time Til a collision situation is present with respect to repeaters l and 2 because they are requesting control of the expansion bus at the same time. When this occurs a transmit collision signal on line 39 is transmitted by the receiving repeaters, in the manner as discussed above, for as long as the condition lasts on the transmitting repeaters. At time T12 when repeater 2 backs off and no longer requests control of the expansion bus, a receive collision is now present at time T12 which is transmitted over the expansion bus. This is further reflected by destination repeaters 4 and 5. Subsequently, at time T13, when repeater 3 requests control of the bus, a transmit collision signal is again asserted on the bus. This transmit collision signal is extended by the transmitting repeaters 1 and 3 for the required minimum of 96 bits. Notice, that in the preferred embodiment of the present invention, the transmission reflected by the destination repeaters are based on the transmission of the repeaters that issue the request signal. When such repeater has a transmit collision with any of the other repeaters, all of the repeaters connected to the hub 10 reflect the situation due to the collision signal on line 39 being asserted by the arbiter 20. When there is a gap between transmit collisions, the destination repeaters (repeater 4 and repeater 5) will either enter the receive collision (Figure 6) or remain in the transmit collision, as shown in Figure 7, based on the transmitting repeaters. Thus, all the destination repeaters will respond identically to the same event preventing any network errors.

The foregoing description of the preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The asynchronous expansion bus for asynchronously transmitting information over an ethernet network was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

CLAIMSI Claim:

1. An asynchronous expansion network, comprising: means for providing information; bus means for carrying said information; means, coupled to said bus means, for retransmitting said information; and arbiter means, coupled to said bus means, for enabling the transmission of said information, wherein the transmission of said information is performed asynchronously.

2. The asynchronous expansion network of claim 1 further including external controller means, coupled to said transmitting and said receiving means, for managing the operation of said transmitting and said receiving means.

3. The asynchronous expansion network of claim 1, wherein said retransmitting means comprises means for asynchronously retransmitting said information, said retransmitting means including input means for accepting said information and output means for delivering said information.

4. The asynchronous expansion network of claim 1, wherein said arbiter means comprises means for enabling the transmission of information.

5. The asynchronous expansion network of claim 1, wherein said arbiter means comprises means for preventing the transmission of information.

6. The asynchronous expansion network of claim 3, wherein said receiving means comprises means for determining when a collision has occurred between said input means and said output means.

7. The asynchronous expansion network of claim 6, wherein said receiving means further comprises means for disabling information transmission.

8. The asynchronous expansion network of claim 1, wherein said transmitting means further comprises means for disabling transmission.

9. An expansion bus for an ethernet network, comprising: a first repeater operative to transmit information over a communication network; at least one second repeater responsive to said first repeater, said at least one second repeater operative to retransmit said information present on said communication network; and an arbiter, coupled between said first repeater and said at least one second repeater, said arbiter responsive to signals from said first repeater and said at least one second repeater to enable retransmission ^f information from said first and at least one second repeater, wherein said transmission is performed asynchronously.

10. The expansion bus of claim 9, further including an external controller coupled to said first and at least one second repeater, said external controller configured to manage the operation of said asynchronous information transmission between said first and at least one second repeater and said communication network.

11. The expansion bus of claim 9, wherein said first repeater includes a clock having a first frequency.

12. The expansion bus of claim 11, wherein said at least one second repeater includes a second clock having a second phase and frequency different from said first frequency, wherein said transmission of information is performed corresponding to said first frequency.

13. A system for transmitting information over a communication network, comprising: a first repeater operative to transmit information over a bus, said first repeater operating corresponding to a clock having a first frequency and phase; at least one second repeater responsive to said information present on said bus, said at least one second repeater retransmitting said information over said bus, said at least one second repeater operating corresponding to a clock having a second frequency and phase different from said first frequency and phase; and an arbiter in electrical communication with said first repeater and said at least one second repeater, said arbiter operative to enable transmission of information over said bus between said first and at least one second repeater, wherein said information transmission is performed asynchronously.

14. The system of claim 13 further including an external controller coupled to said first repeater, said at least one second repeater and said arbiter, said external controller configured to manage said bus activity.

15. The system of claim 13, wherein said information transmission is performed corresponding to said first clock frequency.

16. The system of claim 13, wherein said arbiter comprises a programmable logic device.

17. The system of claim 16, wherein said arbiter comprises a programmable logic array.

18. The system of claim 13, wherein said first repeater comprises: a plurality of input ports for receiving information; means, coupled to said input ports, for retiming said information corresponding to a first clock frequency; and an output port for transmitting said received information over said bus.

19. The system of claim 13, wherein said at least one second repeater comprises: a plurality of input ports for receiving information; means, coupled to said input ports, for retransmitting said information corresponding to a second clock frequency; and an output port for transmitting said received information over said bus.

20. A circuit for transmitting data over a bus, comprising: input means for accepting a data signal; output means for delivering said data signal; clock means for controlling the frequency said input and output means operates; and means for preventing the transmission of sid data signal.

21. The circuit of claim 20 further including means for counting to provide said data at said input means having a prescribed length.

22. The circuit of claim 20 further including means for indicating when said data signal is valid.

23. The circuit of claim 20 further including means for enabling the transmission of said data signal.

24. A system for transmitting data over a communication link, comprising: a plurality of repeaters operative to transmit data over a bus, said plurality of repeaters including an input operative to accept said data, said plurality of repeaters including an output adaptable to deliver said data; an arbiter coupled to said plurality of repeaters to enable the transmission of said data over said bus in an asynchronous manner; and - 22 - a controller in electrical communication with said arbiter and said plurality of repeaters, said controller operative to manage the activity of said bus.