WO1996013904A1 - Digital-analog converter - Google Patents

Digital-analog converter Download PDF

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Publication number
WO1996013904A1
WO1996013904A1 PCT/EP1995/004248 EP9504248W WO9613904A1 WO 1996013904 A1 WO1996013904 A1 WO 1996013904A1 EP 9504248 W EP9504248 W EP 9504248W WO 9613904 A1 WO9613904 A1 WO 9613904A1
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WO
WIPO (PCT)
Prior art keywords
digital
metal oxide
oxide semiconductor
field effect
transistor
Prior art date
Application number
PCT/EP1995/004248
Other languages
French (fr)
Inventor
Bernard Ginetti
Original Assignee
Vlsi Technology Inc.
Vlsi Technology S.A.R.L.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vlsi Technology Inc., Vlsi Technology S.A.R.L. filed Critical Vlsi Technology Inc.
Publication of WO1996013904A1 publication Critical patent/WO1996013904A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H03M1/682—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits both converters being of the unary decoded type
    • H03M1/685—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits both converters being of the unary decoded type the quantisation value generators of both converters being arranged in a common two-dimensional array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators
    • H03M1/747—Simultaneous conversion using current sources as quantisation value generators with equal currents which are switched by unary decoded digital signals

Definitions

  • the present invention relates to a digital-analog converter.
  • the first solution supplies the smallest and fastest configuration, but a matching to N bits of the current sources is necessary in order to ensure monotonicity.
  • the second solution ensures monotonicity no matter what the matching, but requires a large silicon area, which does not correspond to the actual current sources : even in the case of binary weighted sources, the latter are formed by unit cells in parallel for matching reasons.
  • the supplementary area is due to the logic necessary for the series selection of each source.
  • the N bit input code B[N-1:0] is subdivided into MSB (Most Significant Bits) and LSB (Least Significant Bits), respectively H and V :
  • thermometric codes H and V are converted into thermometric codes, respectively HT and VT :
  • the bits of HT and VT codes are respectively horizontally and vertically routed to the source array.
  • a source located in position (h,v) is excited (i.e. its current is supplied to the load) in accordance with the condition :
  • HT[h] AND VT[v] OR VT[v+l] Starting with a zero input code on the DAC, only HT[0] and VT[0] are brought to "1". The only selected source is that of the upper left-hand corner. By increasing the code up to the least MSB, all the sources of the first left-hand column are progressively selected. When the smallest MSB assumes the value "1”, VT[1] is brought to "1", all the sources of the first column being maintained selected and the sources of the second column are progressively excited (Turn-on) and so on.
  • the AND-OR gate necessary for implementing the aforementioned condition is alongside each current source and controls a switch in series with the source, as shown in Fig. 4. In practice, the leaf cell zone is dominated by the AND-OR gate.
  • the object of the present invention is to reduce the area of the thermometric-type common DAC, whilst maintaining its inherent monotonicity and therefore increasing at the same time the integral linearity of the converter due to the improved matching of the near unit sources.
  • the present invention relates to digital-analog converter incorporating an array of current source cells connected at the output to a load as a function of an input code subdivided into respectively H and V, most significant bit (MSB) and least significant bit
  • thermometric codes (LSB) , converted into thermometric codes, respectively
  • each position cell (h, v) comprises a first and a second P type metal oxide semiconductor field effect transistor in series, in parallel with at least one third P type metal oxide semiconductor field effect transistor.
  • the gate of the second transistor receives a signal HT(h), and the gate of the third transistor receives a signal VT(v+1).
  • One current source is connected between the drains of the first and third P type metal oxide semiconductor field effect transistors and a polarization voltage VDD and the output signal is obtained on the source of the second P type metal oxide semiconductor field effect transistor.
  • the current source has a P type metal oxide semiconductor field effect transistor, e.g. a long transistor.
  • the first, second and third P type metal oxide semiconductor field effect transistors are wide transistors.
  • the first transistor receives a signal VT(v) on its gate.
  • a fourth P type metal oxide semiconductor field effect transistor is arranged in series with the third transistor, in parallel with the two first transistors, said fourth transistor receiving the signal VT(V+1) on its gate.
  • the first transistor receives a signal VS(v) on its gate, the signal VS, which is the V decoded 2 N conversion, being such that :
  • thermometric-type current DAC a reduced area for the thermometric-type current DAC
  • Figs. 1 to 4 illustrate different prior art devices.
  • Fig. 5 illustrates a first embodiment of the device according to the invention.
  • Fig. 6 illustrates a second embodiment of the device according to the invention.
  • the digital-analog converter or DAC comprises an array of current source cells connected at the output to a load as a function of an input code.
  • the input code is subdivided into respectively H and V, MSB and LSB bits, converted into ther ometric codes, respectively HT and VT, whose logic inverses, are respectively horizontally and vertically routed to said array.
  • Each position cell (h, v) comprises, as shown in Fig. 5, a first and a second PMOS (P type metal oxide semiconductor field effect transistor) (Ml, M2) in series and in parallel with a third PMOS transistor (M3) .
  • PMOS P type metal oxide semiconductor field effect transistor
  • the gate of the first transistor receives a signal VT(v), the gate of the second transistor receiving a signal HT(h), whilst the gate of the third transistor receives a signal VT(v+l).
  • a current source e.g. a PMOS transistor, is connected between the drains of the first and third PMOS transistors and a voltage VDD. The output signal is obtained on the source of the second PMOS transistor.
  • the transistors used are solely PMOS transistors for controlling the current source.
  • a simple improvement of the AND-OR function by means of PMOS switches is shown in Fig. 5, using inverse thermometric codes HT and VT.
  • an array of four switches advantageously replaces the A ⁇ D-OR gate shown in Fig. 4, which requires a separate well P (P-well) and a rail voltage VSS.
  • HT and VS are routed vertically on the source array, whereas HT is shifted horizontally.
  • the complete leaf cell of the DAC is then constituted by a current source and four switches, as shown in Fig. 6.
  • VS[v] and VT[v+l] are never on at the same time and the current can flow either through transistors Ml and M2 only, or through transistors M3 and M4 only.
  • the transistor M4 is a dummy used only for matching the impedance of the transistors Ml and M2.
  • the signals VT, VS and HT do not use the logic levels [VSS, VDD] . They are always brought to VDD (switch off) or to a polarization voltage (switch on) , which keeps the PMOS transistor saturated. Thus, they act like a cascode device for increasing the output impedance of the DAC.
  • Such a construction makes it possible to obtain a reduced size converter having a better current source matching and therefore a greater integral linearity, whilst requiring a reduced power for conducting the control signals.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

A digital-analog converter incorporates an array of current source cells connected at the output to a load as a function of an input code subdivided into respectively H and V, most significant bit (MSB) and least significant bit (LSB), converted into thermometric codes, respectively HT and VT, whose logic inverses are respectively horizontally and vertically routed to said array. Each position cell (h, v) comprises a first and a second P type metal oxide semiconductor field effect transistor in series, in parallel with at least one third P type metal oxide semiconductor field effect transistor.

Description

DIGITAL-ANALOG CONVERTER
DESCRIPTION
TECHNICAL FIELD
The present invention relates to a digital-analog converter.
PRIOR ART
In prior art devices, e.g. in the digital-analog converter (DAC) described in the article by Jean Michel Fournier and Patrice Senn entitled "A 130 MHz 8-b CMOS video DAC for HDTV Application" (IEEE Journal of Solid- State Circuits, volume 26, No. 7, July 1991, pages 1073-1077), one of the methods used for producing a digital-analog converter (DAC) consists of using an array of current sources, connected to a load in accordance with the input code of the DAC. Two operating diagrams are widely used for obtaining a given resolution of N bits.
1) Use is made of an array of N binary weighted sources controlled directly by the N bits of the input code, as shown in Fig.l.
2) Use is made of an array or 2N unit sources controlled by the thermometric conversion of the input code, as shown in Fig. 2
The first solution supplies the smallest and fastest configuration, but a matching to N bits of the current sources is necessary in order to ensure monotonicity. The second solution ensures monotonicity no matter what the matching, but requires a large silicon area, which does not correspond to the actual current sources : even in the case of binary weighted sources, the latter are formed by unit cells in parallel for matching reasons. The supplementary area is due to the logic necessary for the series selection of each source.
In typical manner, as shown in Fig. 3 : the N bit input code B[N-1:0] is subdivided into MSB (Most Significant Bits) and LSB (Least Significant Bits), respectively H and V :
Figure imgf000004_0001
The codes H and V are converted into thermometric codes, respectively HT and VT :
HT[2N-1:0] with HT[j]=l for j≤val(H) and HT[j]=0 for j>val(H)
VT[2N-1:0] with VT[j]=l for j≤val(V) and VT[j]=0 for j>val (V)
The bits of HT and VT codes are respectively horizontally and vertically routed to the source array. A source located in position (h,v) is excited (i.e. its current is supplied to the load) in accordance with the condition :
HT[h] AND VT[v] OR VT[v+l] Starting with a zero input code on the DAC, only HT[0] and VT[0] are brought to "1". The only selected source is that of the upper left-hand corner. By increasing the code up to the least MSB, all the sources of the first left-hand column are progressively selected. When the smallest MSB assumes the value "1", VT[1] is brought to "1", all the sources of the first column being maintained selected and the sources of the second column are progressively excited (Turn-on) and so on.
The AND-OR gate necessary for implementing the aforementioned condition is alongside each current source and controls a switch in series with the source, as shown in Fig. 4. In practice, the leaf cell zone is dominated by the AND-OR gate.
The object of the present invention is to reduce the area of the thermometric-type common DAC, whilst maintaining its inherent monotonicity and therefore increasing at the same time the integral linearity of the converter due to the improved matching of the near unit sources.
DESCRIPTION OF THE INVENTION
The present invention relates to digital-analog converter incorporating an array of current source cells connected at the output to a load as a function of an input code subdivided into respectively H and V, most significant bit (MSB) and least significant bit
(LSB) , converted into thermometric codes, respectively
HT and VT, whose logic inverses are respectively horizontally and vertically routed to said array, wherein each position cell (h, v) comprises a first and a second P type metal oxide semiconductor field effect transistor in series, in parallel with at least one third P type metal oxide semiconductor field effect transistor.
Advantageously the gate of the second transistor receives a signal HT(h), and the gate of the third transistor receives a signal VT(v+1). One current source is connected between the drains of the first and third P type metal oxide semiconductor field effect transistors and a polarization voltage VDD and the output signal is obtained on the source of the second P type metal oxide semiconductor field effect transistor.
Advantageously, the current source has a P type metal oxide semiconductor field effect transistor, e.g. a long transistor.
Advantageously, the first, second and third P type metal oxide semiconductor field effect transistors are wide transistors.
In a first embodiment the first transistor receives a signal VT(v) on its gate.
In a second embodiment a fourth P type metal oxide semiconductor field effect transistor is arranged in series with the third transistor, in parallel with the two first transistors, said fourth transistor receiving the signal VT(V+1) on its gate. In addition, the first transistor receives a signal VS(v) on its gate, the signal VS, which is the V decoded 2N conversion, being such that :
VS[j]=l for val(v) and VS(j)=0 for j≠val(v). The invention makes it possible to obtain the following advantages :
- a reduced area for the thermometric-type current DAC,
- a better matching of the current sources, because they are nearer, and thus a greater integral linearity on the DAC,
- a reduced power for conducting the control signals (minimum four PMOS switches instead of six CMOS transistors) .
BRIEF DESCRIPTION OF THE DRAWINGS
Figs. 1 to 4 illustrate different prior art devices. Fig. 5 illustrates a first embodiment of the device according to the invention.
Fig. 6 illustrates a second embodiment of the device according to the invention.
DETAILED DESCRIPTION OF EMBODIMENTS
The digital-analog converter or DAC according to the invention comprises an array of current source cells connected at the output to a load as a function of an input code. The input code is subdivided into respectively H and V, MSB and LSB bits, converted into ther ometric codes, respectively HT and VT, whose logic inverses, are respectively horizontally and vertically routed to said array. Each position cell (h, v) comprises, as shown in Fig. 5, a first and a second PMOS (P type metal oxide semiconductor field effect transistor) (Ml, M2) in series and in parallel with a third PMOS transistor (M3) . The gate of the first transistor receives a signal VT(v), the gate of the second transistor receiving a signal HT(h), whilst the gate of the third transistor receives a signal VT(v+l). A current source, e.g. a PMOS transistor, is connected between the drains of the first and third PMOS transistors and a voltage VDD. The output signal is obtained on the source of the second PMOS transistor.
In this embodiment of the invention, the transistors used are solely PMOS transistors for controlling the current source. A simple improvement of the AND-OR function by means of PMOS switches is shown in Fig. 5, using inverse thermometric codes HT and VT.
However, such a construction leads to three conductor modes for the current source, as a function of the input code the current can flow solely through the transistors Ml and M2, solely through the transistor M3 or through transistors M1/M2 and M3. The variable impedance of the conductor path affects the current source, which can destroy the monotonicity.
In order to reduce this effect, a high output impedance source (long transistor) and high conductance PMOS switches (wide transistors) must be used, which increases the size of the leaf cell and the load connected to the control signals HT and VT, which also increases the power required. Moreover, it prevents the use of switches such as cascode devices in order to increase the output impedance of the DAC.
In a variant, in each leaf cell, an array of four switches advantageously replaces the AΝD-OR gate shown in Fig. 4, which requires a separate well P (P-well) and a rail voltage VSS. Thus, this variant is based on a supplementary control signal VS, which is the V decodes 2Ν conversion : VS[j]=l for val(V) and VS[j]=0 for j≠val(V)
The inverse logic words HT and VS are routed vertically on the source array, whereas HT is shifted horizontally. The complete leaf cell of the DAC is then constituted by a current source and four switches, as shown in Fig. 6.
VS[v] and VT[v+l] are never on at the same time and the current can flow either through transistors Ml and M2 only, or through transistors M3 and M4 only. The transistor M4 is a dummy used only for matching the impedance of the transistors Ml and M2. Moreover, the signals VT, VS and HT do not use the logic levels [VSS, VDD] . They are always brought to VDD (switch off) or to a polarization voltage (switch on) , which keeps the PMOS transistor saturated. Thus, they act like a cascode device for increasing the output impedance of the DAC.
Such a construction makes it possible to obtain a reduced size converter having a better current source matching and therefore a greater integral linearity, whilst requiring a reduced power for conducting the control signals.

Claims

1. Digital-analog converter incorporating an array of current source cells connected at the output to a load as a function of an input code subdivided into respectively H and V, most significant bit (MSB) and least significant bit (LSB), converted into thermometric codes, respectively HT and VT, whose logic inverses are respectively horizontally and vertically routed to said array, wherein each position cell (h, v) comprises a first and a second P type metal oxide semiconductor field effect transistor in series, in parallel with at least one third P type metal oxide semiconductor field effect transistor.
2. Digital-analog converter according to claim 1, wherein the gate of the second transistor receives a signal HT(h), the gate of the third transistor receives a signal VT(v+l), wherein one current source is connected between the drains of the first and third P type metal oxide semiconductor field effect transistors and a polarization voltage VDD and wherein the output signal is obtained on the source of the second P type metal oxide semiconductor field effect transistor.
3. Digital-analog converter according to claim 2, wherein the current source incorporates a P type metal oxide semiconductor field effect transistor.
4. Digital-analog converter according to claim 3, wherein the P type metal oxide semiconductor field effect transistor is a long transistor.
5. Digital-analog converter according to claim 1, wherein the first, second and third P type metal oxide semiconductor field effect transistors are wide transistors.
6. Digital-analog converter according to claim 1, wherein the first transistor receives a signal VT(v) on its gate.
7. Digital-analog converter according to claim 1, wherein a fourth P type metal oxide semiconductor field effect transistor is arranged in series with the third transistor and in parallel with the two first transistors, said fourth transistor receiving the signal VT(V+1) on its gate.
8. Digital-analog converter according to claim 7, wherein the first transistor receives a signal VS(v) on its gate, the signal VS, which is the V decoded 2N conversion, being such that :
VS[j]=l for val(V) and VS[j]=0 for j≠val(V).
PCT/EP1995/004248 1994-11-01 1995-10-26 Digital-analog converter WO1996013904A1 (en)

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US08/333,008 1994-11-01
US08/333,008 US5600319A (en) 1994-11-01 1994-11-01 Thermometric-to-digital-to-analog converter occupying reduced chip area

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