WO1996010843A1

WO1996010843A1 - Photosensitive semiconductor array

Info

Publication number: WO1996010843A1
Application number: PCT/AU1995/000644
Authority: WO
Inventors: John Frank Siliquini; Lorenzo Faraone
Original assignee: The University Of Western Australia
Priority date: 1994-09-30
Filing date: 1995-09-29
Publication date: 1996-04-11

Abstract

An array of photo sensing elements and a pixel therefor comprising a photoconductor semiconductor material (31, 33) fixed to a conducting (or in some applications non-conducting) substrate (29) which can conduct photons to be detected by the pixel. On top of the photoconductor semiconductor material (31, 33) is a metal terminal (41), which provides an electrode connection to the pixel. In the case of a conducting substrate, mounted on the light receiving face on the side of the substrate (29) opposite the pixel, are metal terminals (45), to provide the other terminal connections. The light receiving face of the substrate is on the opposing side of the substrate to the pixels, which allows a higher packing density of the pixels, and other advantages. Indium bumps (43) provide a connection for signal processing. The semiconductor surfaces have a passivation layer (39).

Description

"Photosensitive Semiconductor Array"

This invention relates to the field of imaging, and in particular to a photoconductor device structure suitable for two-dimensional infrared focal plane arrays.

The development of infrared focal plane arrays (IRFPAs) is essential for enhancing the performance of advanced thermal imaging systems. Apart from offering increased sensitivity and spatial resolution, large two-dimensional IRFPAs also can reduce system complexity, cost and weight. The additional benefits of developing portability, ease-of-use and enhanced reliability brought about by these second generation device structures are becoming increasingly recognised.

The preferred material for fabricating these second generation infrared detector arrays has been semi- conducting Hg.. Cd Te (also known as HgCdTe, MCT, or mercury cadmium telluride) because of its high quantum efficiency, tunable absorption wavelength, and wide operating temperature range. Moreover, since the invention of Charge Coupled Devices (CCDs) it has become possible to couple a very large array of Hg,. Cd Te detectors with on- focal-plane silicon multiplexing technologies. In order to successfully interface Hg_{1 χ} Cd Te detector arrays directly with the CCD input devices it is necessary that the individual detectors have a high impedance. A further requirement is that the individual infrared detector elements themselves dissipate very little power in order to meet practical cryogenic cooling limits. It is for these reasons that research and development of Hg_{1 χ} Cd_χ Te detector technology for large two-dimensional IRFPAs has focused exclusively on p-n junction photovoltaic (PV) structures rather than photoconductive (PC) devices. Photovoltaic Hg_{1 χ} Cd_χ Te devices have high impedance and dissipate very little power, whereas photoconductive Hg., Cd Te detectors have low impedance and, due to detector biasing, dissipate considerable power. Notwithstanding these limitations of PC detectors for IRFPAs, the possibility of using PC detectors instead of PV detectors offers many potential advantages, particularly in the 8 to 14 μm long wavelength infrared (LWIR) spectral region.

Photoconductive Hg_{1 χ} Cd_χ Te arrays are a mature technology, and have been the workhorse for high volume production of first generation sensor systems in the LWIR spectral region for the past two decades. In contrast, photovoltaic

Hg. Cd Te arrays are a comparatively immature technology. Although large two dimensional PV arrays have been demonstrated, these are in the short and medium wavelength infrared (SWIR and MWIR) spectral regions.

In accordance with a first aspect of the present invention there is provided a photosensing element comprising a plurality of pixels mounted as a two dimensional array on a suitable substrate, each said pixel including a photosensitive semiconductor and being adapted to be biased in use via a terminal connecting to said photosensitive semiconductor at an aspect thereof opposite to the aspect on which photon radiation is incident.

Preferably each said terminal is centrally located on each said pixel.

Preferably each said pixel includes a second terminal located on either side of said centrally located terminal.

Preferably said substrate is electrically insulating and transparent to infrared radiation. Preferably each said pixel includes a main body of n-type compound semiconductor on top of said substrate.

Preferably each said pixel includes a cap layer of n type compound semiconductor on top of the said main body.

Preferably said main body is epitaxial.

Preferably said main body comprises Hg_{1 χ} Cd_χ Te semiconductor, where x is approximately 0.21.

Preferably said cap layer comprises Hg.. Cd Te semiconductor, where x is approximately 0.25.

Preferably each said pixel includes a passivation layer covering the semiconductor surface (including the said cap layer). The passivation layer may comprise an oxide/ZnS passivation layer.

Preferably each said terminal is located on top of the said passivation layer, to allow easy interconnection to a silicon chip comprising signal processing circuitry. These terminals contact to the said cap layer only through suitable via holes opening through the said passivation layer.

Preferably each said pixel includes a plurality of semiconductor element portions located in layers on said substrate, each element portion having sensitivity to a predetermined bandwidth.

Preferably said predetermined bandwidths cover different wavelengths. In this manner the photo sensing element will be multi-spectral.

Preferably said semiconductor element portions each comprise epitaxial hetero unction layers. Preferably said epitaxial heterojunction layers are separated by an electrically insulating layer and are continuously consecutive therewith.

Preferably said electrically insulating layer is a low doped semiconductor.

Preferably the starting Hg_{1 χ} Cd_χ Te semiconductor material consists of epitaxially grown heterojunction layers in which a two-dimensional mosaic of photoconductors are fabricated. The heterojunction layer provides high performance devices at greatly reduced power dissipation levels, while by suitably forming the contacts, allows for the high density integration of photoconductors in a two- dimensional array geometry with high fill factor.

The semiconductor element portions, if utilised, may also comprise epitaxially grown heterojunction layers.

Alternatively the photosensing element is fabricated on a conventional single n-type epitaxial Mercury Cadmium Telluride layer on an insulating substrate. In this case, instead of using wider bandgap Mercury Cadmium Telluride layers in order to produce the low recombination velocity contacts, indium diffused n+ "blocking" contacts can be formed at the two terminals. This type of blocking contact has also been shown to be effective in reducing the effects of minority carrier sweepout. The use of blocking contacts is a viable alternative in order to maintain high responsivities in the photoconductor.

The photosensing element may be connected to signal processing circuitry by forming an indium bump interconnect to each terminal. This offers high performance devices at reduced power dissipation levels, and by suitably forming the contacts, allows for the high density integration of photoconductors in a two-dimensional array geometry with high fill factor. ln accordance with a second aspect of the present invention there is provided a photosensing element comprising a plurality of pixels mounted as a two dimensional array on a suitable substrate, said substrate providing a surface for incident photon radiation on one side of said photosensing element, and each said pixel including a photosensitive semiconductor having a terminal connecting thereto on the opposite side of said photosensing element to said surface.

In one preferred form, said terminal is centrally located on each said pixel.

In an alternative preferred form, said terminal surmounts said pixel and each said pixel includes a second terminal either comprising said substrate or located adjacent to said substrate, in connection with each said pixel.

In a further alternative form said second terminal also surmounts said pixel, adjacent to said terminal. In either alternative the terminal need not be centrally located.

Preferably said pixel includes a plurality of semiconductor element portions located in layers on said substrate, each element portion having sensitivity to a predetermined bandwidth.

Preferably said semiconductor element portions each comprise epitaxial heterojunction layers. Preferably said epitaxial heterojunction layers are separated by an electrically insulating layer and are continuously consecutive therewith.

Preferably said electrically insulating layer is a low doped semiconductor.

Preferably the starting Mercury Cadmium Telluride semiconductor material consists of epitaxially grown heterojunction layers in which a two-dimensional mosaic of photoconductors are fabricated. The heterojunction layer provides high performance devices at greatly reduced power dissipation levels, while the unique design allows for the high density integration of photoconductors in a two-dimensional array geometry with high fill factor. The semiconductor element portions if utilised, may also comprise epitaxially grown heterojunction layers.

The photosensing element may be connected to signal processing circuitry by forming an indium bump interconnect to each terminal photoconductive device. This offers high performance devices at reduced power dissipation levels, and by suitably forming the contacts, allows for the high density integration of photoconductors in a two-dimensional array geometry with high fill factor.

In accordance with a third aspect of the present invention there is provided a photo sensing element comprising a plurality of pixels mounted as a two dimensional array on a suitable substrate, each said pixel including a photosensitive semiconductor and being adapted to be biased in use with a voltage field extending away from the plane of said substrate.

Preferably, each said pixel includes a first terminal located on said pixel, distal from said substrate, and a second terminal located toward, adjacent, or on said substrate away from said first terminal.

Preferably said substrate is electrically conductive and serves as a second terminal for each said pixel.

Preferably each said pixel includes a main body of n-type compound semiconductor.

Preferably each said pixel includes a highly doped layer of compound semiconductor between said first terminal and said main body.

Preferably each said pixel includes a highly doped layer of compound semiconductor between said second terminal and said main body.

Preferably said highly doped layer between said second terminal and said main body exhibits low free carrier absorption.

Preferably said main body comprises Hg.. Cd Te semiconductor, where x is approximately 0.21.

Preferably said main body is epitaxial.

Preferably said highly doped layers comprise Hg_{1 χ} Cd_χ Te semiconductor, where x is approximately 0.24 to 0.25. Preferably each said pixel includes a passivation layer covering the semiconductor surface. The passivation layer may comprise an oxide/ZnS passivation layer.

Preferably said first terminals are located distal from the substrate, on top of the semiconductor material comprising each said pixel, to allow easy interconnection to a silicon chip comprising signal processing circuitry.

Preferably said semiconductor element portions each comprise epitaxial heterojunction layers.

Preferably said epitaxial heterojunction layers are separated by an electrically insulating layer and are continuously consecutive therewith.

Preferably said electrically insulating layer is a low doped semiconductor.

Preferably the starting Mercury Cadmium Telluride semiconductor material consists of epitaxially grown heterojunction layers in which a two-dimensional mosaic of photoconductors are fabricated. The heterojunction layer provides high performance devices at greatly reduced power dissipation levels, while the unique design allows for the high density integration of photoconductors in a two-dimensional array geometry with high fill factor. The semiconductor element portions if utilised, may also comprise epitaxially grown heterojunction layers. Alternatively the photosensing element is fabricated on a conventional single n-type epitaxial Mercury Cadmium Telluride layer on an insulating substrate. In this case, instead of using wider bandgap Mercury Cadmium Telluride layers in order to produce the low recombination velocity contacts, indium diffused n+ "blocking" contacts can be formed at the two terminals. This type of blocking contact has also been shown to be effective in reducing the effects of minority carrier sweepout. The use of blocking contacts is a viable alternative in order to maintain high responsivities in the photoconductor.

In accordance with a fourth aspect of the present invention, there is provided a photosensing element comprising a plurality of pixels mounted as a two dimensional array on a suitable substrate, each said pixel including a plurality of semiconductor element portions located in layers on said substrate.

Preferably each said semiconductor element portion comprises an epitaxial heterojunction layer.

Preferably said electrically insulating layer is a low doped semiconductor.

Preferably each element portion has a sensitivity to a predetermined bandwidth. Preferably said predetermined bandwidths cover different wavelengths. In this manner the photo sensing element will be multi-spectral.

In accordance with a fifth aspect of the invention, there is provided a photoconductive sensing element for high density two dimensional infrared focal plane array applications, comprising epitaxial heterojunction layers in which a two-dimensional mosaic of vertically biasable photoconductors are fabricated. The heterojunction layer provides high performance devices at greatly reduced power dissipation levels, while the vertical design allows for the high density integration of photoconductors in a two-dimensional array geometry with high fill factor.

In accordance with a sixth aspect of the present invention, there is provided a method for fabricating a photoconductor array having at least one terminal on each pixel on the side of the substrate opposite to the side which radiation is incident.

In accordance with a seventh aspect of the invention there is provided a method for fabricating a photoconductor array on a substrate, having a voltage field bias in each pixel extending away from the plane of said substrate.

In accordance with an eighth aspect of the invention there is provided a method for fabricating a multispectral photoconductor array.

The invention will now be described in the following description of seven embodiments thereof, made with reference to the drawings in which:

Figure 1 is an illustration of a conventional (prior art) lateral photoconductor structure; Figure 2 is an illustration of one embodiment of a photoconductor construction according to the invention;

Figure 3 is a side cross-section of a photoconductor construction with heterojunction contacts, according to a fourth embodiment of the invention;

Figure 4 is a side cross-section of a photoconductor construction with no heterojunction contacts, but with standard n-type MCT with n+ blocking contacts, according to a third embodiment of the invention;

Figures 5 to 8 are side cross-section views showing the production of a photoconductor array according to a second embodiment of the invention;

Figure 9 is a perspective view showing detail view of a hybridised photoconductor array and signal processing chip;

Figure 10 shows a graph showing calculated responsivity as a function of device length for a vertical photoconductor with either heterojunction, n+ blocking, or ohmic contacts;

Figure 11 is a graph showing calculated noise voltages a function of device length for a vertical photoconductor with either heterojunction, n+ blocking, or ohmic contacts;

Figure 12 is a graph showing calculated detectivity as a function of device length for a vertical photoconductor with either heterojunction, n+ blocking, or ohmic contacts; Figure 13 is a graph showing calculated optimum length as a function of power dissipated for a vertical photoconductor with either heterojunction, n+ blocking, or ohmic contacts;

Figure 14 is a graph showing calculated responsivity as a function of power dissipated for a vertical photoconductor with either heterojunction, n+ blocking, or ohmic contacts having device lengths of 10 μm , 14 μm and 82 μm respectively;

Figure 15 is a side cross-section of a photoconductor construction with heterojunction contacts, according to a fifth embodiment of the invention;

Figures 16 to 19 are side cross-section views showing the production of a photoconductor array according to the fifth embodiment of the invention;

Figure 20 is a top view of a photoconductor array according to the fifth embodiment of the invention.

Figure 21 is a side cross-section of a photoconductor construction with heterojunction contents, according to the sixth embodiment of the invention;

Figures 22 to 25 are side cross-section views showing the production of a photoconductor array according to the sixth embodiment of the invention;

Figure 26 is a top view of the photoconductor array according to the sixth embodiment of the invention;

Figure 27 is a side cross-section of a photoconductor construction with heterojunction contacts, according to a seventh embodiment of the invention; Figure 28 is a side cross-section of a photoconductor construction with heterojunction contacts, according to the seventh embodiment but utilising an indium bump for the common terminal of each pixel;

Figure 29 to 34 are side cross-section views showing the production of a photoconductor array according to the seventh embodiment of the invention; and

Figures 35 and 36 show top views of multi-spectral photoconductor arrays having differing common configurations, according to the seventh embodiment.

Referring to figure 1 , a prior art pixel is shown, in which a photosensitive semiconductor 11 is mounted on an insulating substrate 13. Metal contacts 15 provide the terminals to bias the photosensitive semiconductor 11 with a voltage field having a polarity extending normal to the direction that radiation is incident.

In comparison, the first set of embodiments of the invention, described with reference to at least figures 2 to 8 inclusive, comprises photosensitive elements in the form of pixels formed of photoconductor semiconductor material having terminals formed to provide in use a voltage field which is substantially transverse to, or at least across the plane of the substrate, substantially in the same direction of incident radiation.

The first embodiment is shown in figure 2, and comprises a photo sensing element including a pixel 17 having a photoconductor semiconductor material 19 fixed to a conducting substrate 21 which can conduct electricity and incident photons to be detected by the pixel. On top of the photoconductor semiconductor material 19 is a metal terminal 23, which provides an electrode connection to the pixel, and mounted on the light receiving face 25 on the opposite side of the pixel is a metal terminal 27.

In contrast to conventional lateral photoconductors, in which the bias field is applied laterally along the plane of the semiconductor and at right angles to the incoming radiation, in the case of vertical photoconductors the bias field is applied axially of the incoming radiation and at right angles to the plane of the semiconductor. The vertical photoconductor configuration offers a number of important advantages over the traditional lateral design:

(i) Because the incoming photons are transmitted through the substrate and absorbed in the Hg-_j Cd_χ Te layer near the positive contact, the majority of photogenerated electron hole pairs are in this vicinity. This is believed to sweep the photogenerated minority carrier holes towards the upper negative contact, where recombination can occur. This is in contrast to a lateral device in which the generated minority carriers are generated uniformly between the two contacts and the applied field is along the plane of the semiconductor. In the lateral design case, therefore, the large proportion of minority carrier holes generated near the negative contact have a greatly reduced lifetime due to carrier "sweepout" to the high recombination region of the metal contact.

(ii) The deterioration of minority carrier lifetime due to enhanced recombination at the Hg.. Cd Te surface is greatly reduced in the vertical PC design. The degree to which minority carrier lifetime is affected is inversely proportional to the separation between the regions of high electron hole pair photogeneration and those of high recombination at the exposed Hg.. Cd Te surfaces. Because of the re-orientation and interchange of thickness and length in the two device structures, for typical device dimensions, this degradation of minority carrier lifetime is reduced substantially in the vertical structure. (iii) Since only one contact per sensing element is required on the top semiconductor surface in the vertical design of the embodiment, very high device densities and large fill factors are achievable. In principal, with a conducting substrate is utilised for the common ground terminal, the density and fill factor will only be limited by the photolithography and etching process used to delineate the individual detectors. Furthermore, as illustrated in figure 9, the array structure afforded by the configuration of the photosensing elements is suitable for hybrid flip chip mating to a silicon multiplexer. This hybridisation technology is a well-established technology and in application to the invention, the front side of the detector array is aligned with the silicon multiplexer and one contact for each photoconductor is made using a previously deposited set of indium "bumps" fabricated on both the focal plane array and on the multiplexer chip. In the standard lateral photoconductor this type of hybrid technology is not possible since two contacts per element are required on the upper semiconductor surface. In addition, a large percentage of the area in the conventional lateral devices is taken up by contacts and metal interconnects which results in low density and low fill factors making them unsuitable for high density IRFPAs.

The second embodiment is the most preferred embodiment and is shown in figures 5 to 8. In this arrangement, the photosensitive element utilises the most preferred material structure for the LWIR vertical photoconductor array. The starting material consists of a conducting substrate 29 that is transparent to LWIR radiation (e.g. GaAs) on which is grown a highly doped n-type layer 31 of Hg₁ Cd Te which has a slightly wider bandgap (delta x approximately 0.04) than the main body or absorbing Hg._|__χ Cd_χ Te layer 33. This bandgap engineered structure forms a heterojunction contact that has been shown to dramatically minimise the deleterious effects of minority carrier sweepout. In addition to this layer being highly doped thereby minimising the substrate/semiconductor contact resistance, it should also be relatively thick (approx. 5 μm) so as to minimise the series resistance to the photoconductor active area for situations in which an insulating substrate is used (see figures 3 and 4). It should be noted that since the array is backside illuminated, the free carrier absorption of this n+ layer 31 needs to be minimised. The infrared absorbing layer 33 of n-type Hg_{1 χ} Cd_χ Te of the appropriate x value and thickness is then grown. Another highly doped n-type layer 35 of wider bandgap (delta x approximately 0.04) than the absorbing layer 33 of Hg_{1 χ} Cd Te is then grown as the final layer.

The major fabrication steps required in order to realise the vertical photoconductor array are outlined in figures 6 to 8. The procedure consists of first defining the photoconductor active or window regions and delineating each element of the array by mesa etching (e.g. by use of ion beam etching) of the semiconductor down to the underlying conducting substrate. The next step is to make an electrical connection from the conducting Hg_{1 χ} Cd_χ Te epitaxial layer to an external circuit in order to anodise the surface in the usual way. Because, by its very nature, the anodisation process tends to be a self regulating one in terms of thickness and insulating properties, the oxide layer formed during growth is extremely uniform over the entire exposed semiconductor surface area of the mesa structure. After anodisation, the wafer is loaded into a vacuum evaporation system for deposition of the ZnS passivation layer 39. The metal contact areas can then be defined by another photoresist process which allows the native oxide and ZnS to be etched away from the contact areas. First terminals in the form of suitable metal contacts 41 or layers can then be deposited and defined using a liftoff process in order to form ohmic contacts to the Hg₁ Cd Te top mesa surface. It should be noted that this process results in a self-alignment of the passivation layer with the metal contacts. Consequently, the entire Hg_{1 χ} Cd_χ Te surface is protected by either the anodic oxide/ZnS passivation layer or the multi-metal contact layer 41. Finally, indium

"bumps" 43 can be formed by another liftoff process for subsequent interfacing to suitable silicon read-out circuits via standard hybrid flip chip bonding. Second terminals in the form of metal contacts or layers 45 are bonded to the substrate 29, between the LWIR pathways to the pixels, so as not to obscure the pixels from incoming radiation. The conducting substrate 29 forms the common ohmic contact to all photoconductor elements which allows a close-packed two- dimensional mosaic of detectors to be formed on a minimum pitch. This material structure is considered optimum since it also offers the least contact and series resistance, thus maximising responsivity.

As will be understood, only three photo-masks are required to fabricate this embodiment of the photoconductor array, and the photoconductor array may be produced by the use of standard fabrication processes which are compatible with existing Hg,. Cd Te photoconductor technology. It is believed that the photoconductor array may be produced by both existing or future Hg. Cd Te epitaxial growth processes.

It will also be appreciated that there are a number of different combinations and variations in device structure possible depending on the epitaxial Hg. Cd Te substrate material that is available. Accordingly the third embodiment as shown in figure 4, is such an example, wherein the array is formed on a conventional single n-type epitaxial Hg^ Cd Te layer 47 on an insulating substrate 49. In this embodiment, instead of using wider bandgap HgCdTe layers in order to produce the low recombination velocity contacts, indium diffused n+ "blocking" contacts can be formed on the top and common terminals. This type of blocking contact has also been shown to be effective in reducing the effects of minority carrier sweepout.

The fourth embodiment is shown in figure 3 and utilises heterolayers as used in the second embodiment (figs 5-8), formed on an insulating substrate 49. In this case the CdHgTe layers are etched down to remove the absorbing layer lying between the pixels 17, but leave intact the highly doped n+ layer 31 adjacent to the substrate 49. Second terminals in the form of metal contacts 45 are then bonded to the layer 31 , at positions between the pixels .

The fifth embodiment is directed towards a photo sensitive element of a significantly different form of pixel construction than adopted in the preceding embodiments, although still following the general principle of element construction salient to the invention.

Moreover, as shown in figures 15 to 20 of the drawings, the photo sensitive element 61 comprises an insulating, photoconductive substrate 63 having an anti-reflection coating 65 on one surface for receiving incident infrared radiation, and a plurality of pixels 67 mounted as a planar two dimensional array on to the opposing surface of the substrate.

Each pixel of the array consists of a conventional lateral heterojunction photoconductor but rather than the two terminal contacts being on either side of the active or window area for receiving incident IR radiation, at least one contact terminal 71 is placed on the top passivated semiconductor surface 69 of each pixel, on the side opposite to the incident IR radiation. In the present embodiment, all of the terminals are located on top of the infrared detecting area of the pixel, opposite to the incident IR radiation. The detected radiation enters from the coating side of the substrate 63 into the absorbing main body semiconductor 73 and is detected by applying a suitable bias electric field between the two terminals.

A material structure for the LWIR lateral photoconductor array according to the fifth embodiment, is shown in figures 15 to 19. The starting material consists of a insulating substrate 63 (e.g. CdTe or CdZnTe) on which is grown an infrared absorbing layer of n-type Hg_{1 χ} Cd_χ Te of the appropriate x value and thickness. Another n-type layer of Hg_{1 χ} Cd_χ Te which has a slightly wider bandgap (x approximately 0.04) than the absorbing Hg_{1 χ} Cd_χ Te layer is then grown on top of the absorbing layer of Hg_{1 χ} Cd_χ Te. This bandgap engineered structure forms a heterojunction contact that has been shown to dramatically minimise the deleterious effects of minority carrier sweepout.

The major fabrication steps required in order to realise the lateral photoconductor array are outlined in figures 16 to 19. The procedure consists of first defining the photoconductor active or window regions and delineating each element or the array by mesa etching (e.g. by use of ion beam etching) of the semiconductor down to the underlying insulating substrate 63. The next step is to make an electrical connection from the conducting Hg. Cd Te epitaxial layer 73 to an external circuit in order to anodise the surface in the usual way. Because, by its very nature, the anodisation process tends to be a self regulating one in terms of thickness and insulating properties, the oxide layer 69 formed during growth is extremely uniform over the entire exposed semiconductor surface area of the mesa structure. After anodisation, the wafer is loaded into a vacuum evaporation system for deposition of the ZnS passivation layer 65. The metal contact areas can then be defined by another photoresist process which allows the native oxide and ZnS to be etched away from the contact areas at the required locations. Suitable metal layers can then be deposited and defined using a lift-off process in order to form ohmic contacts 71 to the Hg. Cd Te top mesa surface. Finally, indium "bumps" 75 can be formed by another lift-off process for subsequent interfacing to suitable silicon readout circuits via standard hybrid flip chip bonding.

The sixth embodiment of the invention is similar to the fifth embodiment in that the array consists of lateral heterojunction photoconductors in which all of the terminals are located on top of the infrared detecting area of the pixel, opposite to the incident IR radiation. In contrast to the fifth embodiment, however, instead of having common metal lines (see figure 19, 71a and figure 20) running across the length of the array, common Indium bumps 77 are formed. These bumps 77, which act as metal commons for the photoconductors, may also be bump bonded to the silicon readout chip as previously described. This sort of structure will reduce the effects of series resistance on the photoconductor array. Also, it should be pointed out, that combinations of this sixth embodiment and the fifth embodiment can also be considered where the number of indium bumps used for the commons can vary from none to all photoconductors in the array.

The most preferred material structure of the LWIR lateral photoconductor array according to the sixth embodiment is shown in figures 21 to 25 which is similar to that utilised in the fifth embodiment.

The major fabrication steps required in order to realise the lateral photoconductor array are outlined in figures 22 to 25 in cross section. The procedure consists of first defining the photoconductor active or window regions and delineating each element of the array by mesa etching (e.g. by use of ion beam etching) of the semiconductor down to the underlying insulating substrate. The next step is to make an electrical connection from the Hg. Cd Te epitaxial layer to an external circuit in order to anodise the surface in the usual way. Because, by its very nature, the anodisation process tends to be a self regulating one in terms of thickness and insulating properties, the oxide layer formed during growth is extremely uniform over the entire exposed semiconductor surface area of the mesa structure. After anodisation, the wafer is loaded into a vacuum evaporation system for deposition of the ZnS passivation layer. The metal contact areas can then be defined by another photoresist process which allows the native oxide and ZnS to be etched away from the contact areas. Suitable metal layers can then be deposited and defined using a lift-off process in order to form ohmic contacts to the Hg,^ Cd Te top mesa surface. Finally, indium "bumps" 77 can be formed on some or all of the common terminals by another lift-off process, for subsequent interfacing to suitable silicon readout circuits via standard hybrid flip chip bonding. Figure 26 depicts a top view of the lateral photoconductor array with indium bumps 77 formed for the common terminals.

In summary, the salient features of this detector technology are:

(i) complete passivation of all semiconductor surfaces,

(ii) only three photo-masks required,

(iii) compatibility with any existing or future Hg_{1 χ} Cd_χ epitaxial growth process, and (iv) the use of standard fabrication processes which are compatible with existing Hg,_|__χ Cd photoconductor technology.

The seventh embodiment of the invention is similar to the fifth and sixth embodiment in that the array consists of conventional lateral heterojunction photoconductors in which all of the terminals are located on top of the infrared detecting area of the pixel, opposite to the incident IR radiation. In contrast to the fifth and sixth embodiments, however, multi-layers of Hg. Cd Te are used for the specific attempt to form parallel photoconductive elements that can simultaneously detect infrared radiation in a number of wavelength regions of the electromagnetic spectrum. We shall use the term "multi-spectral photoconductor array" to describe the seventh embodiment of the invention. Although what will be described in the following description is specific to infrared radiation detection in 2 regions of the electromagnetic spectrum, the invention covers the detection in any number of regions of the electromagnetic spectrum by suitably growing further layers of Hg. Cd Te with the desired x values and thicknesses.

The most preferred material structure for the tnulti- spectral lateral photoconductor array is shown in figures 27 to 36 in cross section. The starting material consists of an insulating substrate 63 (eg CdTe or CdZnTe) on which is grown an infrared absorbing layer of n-type Hg_{1 χ} Cd_χ Te semiconductor 79 of x value x1 and desired thickness. Another n-type layer of Hg. Cd Te semiconductor 81 which has a slightly wider bandgap x2 (x2-x1 approximately equal to 0.04) than the first absorbing layer x1 is then grown on top of the Hg.

Cd Te layer of x value x1. This bandgap engineered structure between x1 and x2 forms a heterojunction contact that has been shown to dramatically minimise the deleterious effects of minority carrier sweepout. Following this, another layer of Hg. Cd Te semiconductor 83 is grown on top of layer 81. This semiconductor layer 83 has x value x3 which has a sufficiently high bandgap, sufficiently low doping and sufficient thickness so as to effectively electrically isolate the layer of Hg.. _χ Cd_χ Te semiconductor 81 with x value x2 from any subsequent layers of Hg_{1 χ} Cd_χ Te grown on top of this Hg_{1 χ} Cd_χ Te semiconductor layer 83. A second infrared absorbing layer of n-type Hg. Cd

Te semiconductor 85 of x value x4 of appropriate thickness is grown on top of the Hg. I ^— A Cd Λ Te semiconductor layer 83. Another n-type layer of Hg. I ~Λ Cd Λ Te semiconductor 87 which has a slightly wider bandgap x5 (x5-x4 approximately equal to 0.04) than the second absorbing layer 85 x4 is then grown on top of the Hg. Cd_χ Te layer 85. This bandgap engineered structure between x4 and x5 forms a heterojunction contact that has been shown to dramatically minimise the deleterious effects of minority carrier sweepout. Since the array is illuminated from the back, the layer of n-type Hg_{1 χ} Cd Te with x value x4 should have an x value greater than the first infrared absorbing layer of n-type Hg. Cd Te of x value x1. Thus the infrared radiation of shorter wavelength will be absorbed in the first absorbing layer. The radiation with longer wavelength will pass through Hg_{1 χ} Cd_χ Te layers with x values x1 , x2 and x3 and be absorbed in the second infrared absorbing layer of Hg_{1 χ} Cd Te with x value x4. Since the layer of Hg., Cd Te with x value x4 can also absorb radiation of the shorter wavelength, the layer of Hg,, Cd Te with x value x1 should be sufficiently thick so as to minimise the number of photons of shorter wavelength that pass through this layer. This will minimise the effects of crosstalk between the two wavelengths that are being detected.

The major fabrication steps required in order to realise the multi-spectral photoconductor array are outlined in figures 29 to 36. The procedure consists of first defining the photoconductor active or window regions and delineating each element of the array by mesa etching (e.g. by use of ion beam etching) of the semiconductor down to the underlying insulating substrate (see figure 30). The next step (see figure 31) is to etch ridges between adjacent photoconductors through Hg. Cd Te layers with x values x5, x4 and x3 again by a mesa etching process. This step will allow contact to be made to the layer of Hg.

Cd Te epitaxial layers with x values x2 and x5 to an external circuit in order to anodise the Hg. Cd Te surfaces in the usual way. Because, by its very nature, the anodisation process tends to be a self regulating one in terms of thickness and insulating properties, the oxide layer formed during growth is extremely uniform over the entire exposed semiconductor surface area of the mesa structure. After anodisation, the wafer is loaded into a vacuum evaporation system for deposition of the ZnS passivation layer (or any other suitable insulating layer). The metal contact areas can then be defined by another photoresist process which allows the native oxide and ZnS to be etched away from the contact areas (see figure 32). Suitable metal layers can then be deposited and defined using a lift-off process in order to form ohmic contacts 71 to the Hg. Cd Te layers of x value x2 and x5 and to the common areas of the photoconductors (i.e. the Hg. _χ Cd_χ Te layers of x values x2 and x5 mesa surfaces). This is illustrated in figure 33. Finally, indium "bumps" can be formed including some or all of the common terminals by another lift-off process for subsequent interfacing to suitable silicon readout circuits via standard hybrid flip chip bonding. This is illustrated in figure 34. It should be noted that each photoconductive element has two indium bumps 75 as positive terminals for current flow (i.e. one for each parallel photoconductive element) and optionally one for the common or negative or ground terminal 77. The geometry of the arrangement of the contacts and indium bumps is best illustrated from a top view of the multi- spectral photoconductor array as shown in figures 35 and 36. Figure 35 shows the multi-spectral photoconductor array with no indium bumps for the common terminal and instead uses common metal lines, while figure 36 shows the multi-spectral photoconductor array with indium bumps used for the commons.

It should be pointed out that in all the embodiments presented herein, the x values used as the mole fraction of Cd in Hg_{1 χ} Cd_χ Te were for illustration purposes only and in fact many other x values could be used for which this invention is still applicable.

There are obviously a number of different combinations and variations in device structure possible depending on the epitaxial Hg. Cd Te/substrate material that is available. For example, it may be possible to form the array on a conventional single n-type epitaxial Hg^_ Cd Te layer on an insulating substrate. This is the most common form of high quality epitaxial Hg. Cd Te layers that are commercially available at the present time. In this case, instead of using wider bandgap Hg. Cd_χ Te layers in order to produce the low

recombination velocity contacts, indium diffused n "blocking" contacts can be formed on the top and common terminals. This type of blocking contact has also been shown to be effective in reducing the effects of minority carrier sweepout.

One form of the proposed photoconductor array has been experimentally verified in a 3 X 3 array format. These devices were fabricated on material that was at hand, which does not represent the optimum for this configuration. The following device specifications have been experimentally measured. ELEMENT 1 ELEMENT 2 ELEMENT 3

300 X 300 μm² nominal 300 X 300 μm² nominal 300 X 300 μm² nominal

30.2 Ohms 28.6 Ohms 28.3 Ohms

10V/cm 10V/cm 10V/cm

1.60x10⁴VW 1.59x10⁴V/W 1.42x10⁴VW

>3x10¹⁰cmHz¹²W¹ >3x10¹⁰cmHz^1/2W^"1 >3x10¹⁰cmHz¹²W^'1

9.8 μm 9.8 μm 9.8 μm

ELEMENT 6 ELEMENT 5 ELEMENT 4

300 X 300 μm² nominal 300 X 300 μm² nominal 300 X 300 μm² nominal

28.2 Ohms 27.9 Ohms 30.2 Ohms

10V/cm 10V/cm 10V/cm

1.60x10 V/W 1.49x10⁴VW 1.48x10 VW

>3x10¹⁰cmHz¹²W^"1 >3x10¹⁰cmHz¹²W^"1 >3x10¹⁰cmHz^1/2W^"1

9.8 μm 9.7 μm 9.7 μm

ELEMENT 7 ELEMENT 8 ELEMENT 9

300 X 300 μm² nominal 300 X 300 μm² nominal 300 X 300 μm² nominal

31.4 Ohms 32.7 Ohms 34.3 Ohms

10V/cm 10V/cm 10V/cm

1.36x10⁴V/W 1.47x10 V/W 1.30x10⁴V/W

>3x10¹⁰cmHz¹²W^"1 >3x10⁰cmHz¹²W^"1 >3x10¹⁰cmHz ²W^"1

9.8 μm 9.8 μm 9.8 μm

Legend

1) Element size 2) Resistance at 80K.

15 -3 Carrier concentration/Electron mobility of MCT used = 1x10 cm and

9.6x10⁴ cm²V^~V¹ at 80K, respectively

3) Bias electric field

4) Responsivity measured at 9.0 μm 5) Detectivity with a 300K background, 2 π field of view

6) Cut-off wavelength

It should be noted that the above data in no way represents the current state of the art performance achievable for these photoconductors due to: 1) Wet chemical etching resulting in areal non-uniformities,

2) Absence of heterojunction blocking contacts which would substantially reduce power consumption,

3) Large area sensing elements in comparison to typical elements used in

2 a 2-D array format, e.g. a 30x30 μm element would result in

5 responsivities > 10 V W at the same bias electric field

The following information also relates to the developed photoconductor array technology:

2 a) Array fill factor for 50x50 μm element size - approx. 75% for 10 μm design rules, approx. 85% for 5 μm design rules.

b) Yield - 100%

c) Electrical crosstalk - approx. 0%

d) IRFPA architecture- Hybrid flip-chip; identical to that used for MCT PV arrays.

It should be appreciated that in each of the embodiments, the limit to Hg. Cd Te-based IRFPA operability is essentially determined by non-uniformities in the performance of individual elements. Ignoring dimensional fluctuations, these variations in performance may be caused by preexisting spatial inhomogenities in Hg. Cd Te starting material, or may be introduced during device fabrication. For LWIR photovoltaic Hg,. Cd Te arrays made using grown doublelayer junctions and mesa technology, (e.g. as used by Santa Barbara Research Center) the measured variations in responsivity uniformity are attributed to variations in junction area caused by ± 1 μm fluctuations in dimensional control. The 1 μm variations are believed to be consistent with the mesa etching depths, processed by wet chemical etching, providing poorly defined boundaries between adjacent devices. For the above reasons, LWIR photovoltaic Hg.. Cd Te arrays have uniformity limits of between 3 and 8%.

Assuming the starting material is homogeneous, it may be assumed that the photoconductor Hg. Cd Te array will be uniformity limited by the same dimensional controls as these mesa PV Hg_{1 χ} Cd_χ Te arrays. The photoconductive Hg. Cd Te detectors are defined in the vertical dimension by some etching process (e.g. ion beam) through about 10 μm thickness of material. It is the dimensional control of this etching process that determines the active optical area of the individual elements and thus the responsivity uniformity of the photoconductor array. The published values for the uniformity of conventional PC Hg. Cd Te detectors is surprisingly high at between 6 and

10 %, although this may not represent what is achievable with present-day growth and device processing technology. In order to maximise the responsivity uniformity for the photoconductive array it is essential that the mesa etching process used to define the active optical area should be examined for uniformity and tight control. In addition, the responsivity uniformity of PC Hg,_j__χ Cd_χ Te detectors can also be improved by using internal laser-trimmed load resistors for each detector element. This has achieved detector output responsivity uniformities of 1% in some conventional PC Hg_{1 χ} Cd_χ Te detector arrays.

There are no reported yield figures in the literature for large LWIR PV Hg. Cd Te arrays. It is generally accepted, however, that LWIR PV Hg_{1 χ} Cd_χ Te detectors in large focal plane arrays suffer from low yield due to random point and native defects in the Hg_{1 χ} Cd_χ Te material which result in excessive tunnelling leakage currents. This low yield is supported by the fact that very few publications describe the performance of large two- dimensional arrays made from Hg. Cd Te and operating in the long wavelength region of 8-14 μm . On

the other hand, there have been considerably more publications reporting on large LWIR PC Hg_{1 χ} Cd_χ Te linear arrays. Although no yield figures are reported, it can be deduced that the yield of these photoconductive arrays is very much higher than comparable photovoltaic arrays. Further evidence for the yield advantage of photoconductive devices in the LWIR, is the fact that the only large FPAs that are commercially produced in high volume are variants of the US Common Module, which is photoconductor-based. The reasons for this can be attributed to the fact that photoconductive detectors are not as sensitive to localised defects and non- uniformities as photovoltaic devices. Photoconductor device performance depends mainly on the excess carrier lifetime which is determined by the spatial average over the detector volume and it would not be expected to be affected greatly by localised non-uniformities and a low density of point and native defects. This places photoconductive detectors at an intrinsic advantage over photovoltaic devices in terms of pixel yield in an array.

Fill factors of nearly 100% have been reported for medium wavelength infrared (MWIR) PV Hg_{1 χ} Cd_χ Te arrays. To limit crosstalk although, it is desirable to place PV detectors at least two minority carrier diffusion lengths apart, since photogenerated minority carriers generated between PV detectors may diffuse laterally to adjacent detectors. This limitation is not present in the PC array design. In this case photogenerated electron/hole pairs are only generated in the absorbing Hg. Cd Te column, and only these can contribute to the photoconductive signal. There are no photogenerated carriers generated between the PC elements, since this material consists either of wider bandgap material, or no Hg_{1 χ} Cd_χ Te at all. Fill factors may therefore approach 100% without any minority carrier diffusion crosstalk restrictions, and will only be limited by photolithographic and etching processes required in order to delineate the individual sensing elements.

As was mentioned above, photovoltaic detectors suffer from crosstalk due to photogenerated minority carriers that diffuse laterally between adjacent devices. Since the detector elements are physically delineated by etching, this type of crosstalk is not present for the photoconductor array. The photoconductor array is only limited by crosstalk due to phenomena such as optical reflection or refraction, optical scattering, diffraction of the target spot and optical system aberrations, which is also present in all IRFPAs. The majority of these effects can be controlled by suitable design considerations, and crosstalk levels of less than 0.5% should be achievable.

LWIR PV Hg,, Cd Te detectors usually operate at zero or near zero bias voltages and thus dissipate very little power. This has been a major advantage of the photovoltaic device that has lead to their predominance in the design of IRFPAs. It has long been the disadvantage of photoconductive detectors that they dissipate excessive power and are therefore unsuitable for large IRFPA applications. It has been recently demonstrated however, that over an order of magnitude increase in voltage responsivity is achieved by using heterojunction contacts for PC Hg. Cd Te detectors over the standard design photoconductor. This equates to three orders of magnitude reduction in power dissipation of the heterojunction PC over the standard PC for a given responsivity. These significant reductions in power dissipation for PC detectors make them much more attractive for use in large IRFPAs. Furthermore, in a PC array configuration where detectors are read simultaneously for a single frame, the applied DC electric field bias to the PC elements need not be continuous. For typical video frame rates the PC elements may be "switched in", depending on the integration time, on a duty cycle basis. For a scan rate of 109 frames/second, and a short integration times of 1 ms (made possible due to the high quantum efficiency of LWIR PC Hg.._ Cd_χ Te detectors) electric field bias switching may further reduce the power dissipation levels by approximately 90%.

Traditionally, the hybrid flip-chip architecture has been the most commonly used for interfacing two-dimensional PV Hg,, _χ Cd_χ Te detector arrays to the silicon multiplexer. In this architecture the electrical connection is made with indium "bumps" that provide a soft metal interconnect between each pixel and the silicon read-out electronics. This arrangement facilitates the interconnection of a large number of pixels with individual preamplifiers coupled to row and column multiplexers. As is illustrated in figure 9, the same well-established hybrid arrangement can be used with the proposed design photoconductor arrays. This is a significant feature of the photoconductor array design since it can use a proven and well developed silicon interface technology.

The R A values of LWIR PV Hg_{1 χ} Cd_χ Te detectors are typically 1-100 Ω cm.

These low input impedances impose difficult design constraints for the silicon input circuit with regard to achieving high injection efficiency, and low noise levels. Similarly and more seriously, the very low impedance of LWIR PC Hg.

Cd Te detectors creates a difficulty in coupling them to CCD read-out circuits for IRFPA applications. This problem has already been overcome to some extent by the use of suitable buffer interfaces. Multiplexing PC Hg. Cd Te detectors with a silicon CCD with these buffer interfaces have been successfully demonstrated. The drawback, however, of using these types of buffer interfaces is the increased power dissipation in the preamplifier itself. Less power dissipated in the PC detector array means less stringent power constraints for the silicon input buffer circuits. More effort though is needed in the design of silicon CMOS compatible, low power dissipation buffer circuits for the PC Hg.

Cd Te array to become viable. However, it might be much easier solving a silicon circuit technology problem than solving a PV Hg. Cd Te device technology problem.

The ultimate factor that restricts array size is the substrate-to-silicon thermal expansion mismatch. For Hga_j_ Cd_χ Te detectors on CdZnTe substrates, the

2 chip size is limited to about 8 mm . For the photoconductor array with optical areas of 30 μm and a detector spacing of 2 μm , this corresponds to a maximum array size of 250 X 250 detector elements. This density may not be achievable for planar LWIR PV Hg_{1 χ} Cd Te detector arrays due to crosstalk restrictions on minimum detector spacing requirements.

In terms of power dissipation, arrays operating at 80K should be designed with heat loads in the order of 0.5 Watts in order to meet practical cryogenic cooling limits. If 0.25 Watts is allowed for the silicon input circuits, then 0.25 Watts can be dissipated by the photoconductor array. This therefore places a constraint on the power dissipation of each element on the array and/or how many elements can be placed in an array. The array size considered for these simulations consists of 128 X 128 photoconductor elements, thus giving a power dissipation requirement of 15.2 μWatts per element. Shown in figure 10 are the responsivities achievable for vertical photoconductors with this power constraint as a function of detector length for the cases where Ohmic, blocking and heterojunction contacts are assumed. From the figure, it is evident that there exists an optimum detector length such that the responsivity is maximum. This may be explained by recognising that the responsivity of a photoconductor is proportional to the number of photons absorbed in the photoconductor material, and the biasing field, E_b , and inversely proportional to the length I . For short

detector lengths, the number of photons absorbed increases rapidly with increased detector lengths and is the dominant factor in determining the value of Rλ . For detector length greater than the optimum the number of absorbed photons begins to saturate causing Rλ to reach its peak value before decaying at a slow rate (inversely proportional to I ). For cases where sweepout conditions dominate minority carrier recombination (i.e. for the Ohmic contact and to a lesser extent the blocking contact devices), it is beneficial to increase the drift length (i.e. the detector length V I ) of these devices such that the drift time is comparable to the bulk minority carrier lifetime. These devices therefore require longer device lengths to achieve optimum performance. As a comparison, the optimum device length for the heterojunction contact is 10 μm while for the ohmic contact device the optimum length is 82 μm .

Figure 11 shows the noise performance of the above vertical photoconductors as a function of detector length with the same power constraint. Amplifier noise

1/2 is assumed to be 1 nVHz^" , which places a noise floor limit for practical devices. The general shape of these curves is similar to those of responsivity shown in figure 10. The reason for this is that the detectors are background g-r noise limited and the dependence of this type of noise on bias field and effective minority carrier lifetime is equivalent to that of responsivity. It should also be noted that the devices with heterojunction and n+ blocking contacts achieve background g-r noise levels well in excess of the noise floor limit. This is highly desirable since the goal is to design, fabricate and operate the detectors so that background g-r noise dominates all other noise sources. This is not the case for the device with Ohmic contacts, however, where the overall minority carrier lifetime is low, and consequently the background component of g-r noise falls below the noise floor limit. The consequence of this is that the detectivity for this device will be less than those with heterojunction or n+ blocking contacts. By combining the results of figures 10 and 11 it is possible to determine the specific detectivity of the vertical photoconductive devices under consideration, and this is shown in figure 12. This figure shows that background limited detectivities of

6x10 cmHz^1/2W~ are achievable for the vertical photoconductor with either heterojunction or n+ blocking contacts. Figure 13 shows the optimum detector length as a function of power dissipation for a vertical photoconductor when Ohmic, blocking and heterojunction contacts are assumed. It is evident from figure 13 that the optimum detector length for a given power dissipation requirement is relatively independent of the magnitude of that power (except at high power dissipation levels) for the cases where devices have blocking and heterojunction contacts. This is the case since the blocking and heterojunction contact devices are limited by photon absorption whereas the Ohmic contact device is limited by sweepout and minority carrier recombination at the semiconductor/metal interface.

In terms of device performance, figures 10 and 13 show that for a 128 X 128 element array, individual photoconductor element responsivities greater than

1x10⁵ Volts/Watt and background limited detectivities of 6x10¹⁰ cmHz ^{1 2}W^"1 are achievable for a total power dissipation of less than 0.25 Watts for vertical design photoconductors with heterojunction contacts. These performance figures represent state of the art devices suitable for use in very high performance thermal imaging systems. Responsivities of greater than 9x10 Volts/Watt can be achieved for devices that have suitable blocking contacts with the same power dissipation level. This value of responsivity is also sufficiently high to ensure that the individual detectors operate with near background limited detectivity. In contrast, responsivities of devices with Ohmic contacts are restricted to about 2x10 Volts/Watt with correspondingly lower detectivities. These figures highlight the importance of low minority carrier recombination rates at the contacts in order to achieve high responsivity and detectivity photoconductors.

Based on the optimum length of the photoconductor simulated above, figure 14 shows a plot of responsivity versus power dissipation for detector lengths of 82 μm, 14 μm and 10 μm for devices where Ohmic, blocking and heterojunction contacts are assumed, respectively. As explained before, higher responsivity can only be achieved at the expense of greater power dissipation. The relationship, however, is not a linear one. From figure 14 it is evident that the slope of the curve decreases with power. As we move up the power scale, a smaller gain in responsivity would be achieved for every increment in power. Hence, it is more beneficial to operate near the lower end of the power scale.

The present embodiments provide for a Mercury Cadmium Telluride photoconductive device structure that has been designed specifically as a sensing element for high density two-dimensional infrared focal plane array applications. This structure allows for high performance devices at greatly reduced power dissipation levels, while allowing for the high density integration of photoconductors in a two dimensional array geometry with high fill factor such that hybrid bonding to silicon read-out circuits is readily achievable.

It should be appreciated however, that the invention is not limited to the specific embodiments herein described, and indeed may be applicable to other types of photosensitive semiconductor devices and methods of forming the same. Further, the invention is not limited to HgCdTe semiconductors, and a skilled addressee will understand that other semiconductors such as InSb may be suitably employed. It will be understood that photosensitive semiconductor compounds are being developed all the time, and it will be understood that these will be suitable for utilising in this invention.

Claims

1. A photosensing element comprising a plurality of pixels mounted as a two dimensional array on a suitable substrate, each said pixel including a photosensitive semiconductor and being adapted to be biased in use via a terminal connecting to said photosensitive semiconductor at an aspect thereof opposite to the aspect on which photon radiation is incident.

2. A photosensing element as claimed in claim 1 wherein each said terminal is centrally located on each said pixel.

3. A photosensing element as claimed in claim 1 or 2 wherein each said pixel includes a second terminal located on either side of said centrally located terminal.

4. A photosensing element as claimed in any one of the preceding claims wherein said substrate is electrically insulating and transparent to infrared radiation.

5. A photosensing element as claimed in any one of the preceding claims wherein each said pixel includes a main body of n-type compound semiconductor on top of said substrate.

6. A photosensing element as claimed in claim 5 wherein each said pixel includes a cap layer of n type compound semiconductor on top of the said main body.

7. A photosensing element as claimed in claim 5 or 6 wherein said main body is epitaxial.

8. A photosensing element as claimed in any one of claims 5 to 7 wherein said main body comprises Hg Cd Te semiconductor, where x is approximately

1-x x

0.21.

9. A photosensing element as claimed in claim 6 wherein said cap layer comprises Hg Cd Te semiconductor, where x is approximately 0.25.

1-x x

10. A photosensing element as claimed in any one of claims 6 to 9 wherein each said pixel includes a passivation layer covering the semiconductor surface including the surface of said cap layer.

11. A photosensing element as claimed in any one of the preceding claims wherein each said terminal is located on top of the said passivation layer contacting each said cap layer, to allow easy interconnection to a silicon chip comprising signal processing circuitry.

12. A photosensing element as claimed in any one of the preceding claims wherein each said pixel includes a plurality of semiconductor element portions located in layers on said substrate, each element portion having sensitivity to a predetermined bandwidth.

13. A photosensing element as claimed in claim 12 wherein said predetermined bandwidths cover different wavelengths.

14. A photosensing element as claimed in claim 12 or 13 wherein said semiconductor element portions each comprise epitaxial heterojunction layers.

15. A photosensing element as claimed in claim 14 wherein said epitaxial heterojunction layers are separated by an electrically insulating layer and are continuously consecutive therewith.

16. A photosensing element as claimed in claim 15 wherein said electrically insulating layer is a low doped semiconductor.

17. A method of fabricating a photosensing element as claimed in any one of the preceding claims, wherein the starting Hg^Cd_xTe semiconductor material consists of epitaxially grown heterojunction layers in which a two-dimensional mosaic of photoconductors are fabricated.

18. A photosensing element comprising a plurality of pixels mounted as a two dimensional array on a suitable substrate, said substrate providing a surface for incident photon radiation on one side of said photosensing element, and each said pixel including a photosensitive semiconductor having a terminal connecting thereto on the opposite side of said photosensing element to said surface.

19. A photosensing element as claimed in claim 18 wherein said terminal is centrally located on each said pixel.

20. A photosensing element as claimed in claim 18 or 19 wherein each said pixel includes a second terminal located on either side of said centrally located terminal.

21. A photosensing element as claimed in claim 18 wherein said terminal surmounts said pixel and each said pixel includes a second terminal either comprising said substrate or located adjacent to said substrate, in connection with each said pixel.

22. A photosensing element as claimed in claim 18 wherein said terminal surmounts said pixel and each said pixel includes a second terminal also surmounting said pixel, adjacent to said terminal.

23. A photosensing element as claimed in any one of claims 18 to 22 wherein each said pixel includes a plurality of semiconductor element portions located in layers on said substrate, each element portion having sensitivity to a predetermined bandwidth.

24. A photosensing element as claimed in claim 23 wherein said predetermined bandwidths cover different wavelengths.

25. A photosensing element as claimed in any one of claims 18 to 24 wherein said semiconductor element portions each comprise epitaxial heterojunction layers.

26. A photosensing element as claimed in claim 25 wherein said epitaxial heterojunction layers are separated by an electrically insulating layer and are continuously consecutive therewith.

27. A photosensing element as claimed in claim 26 wherein said electrically insulating layer is a low doped semiconductor.

28. A photo sensing element comprising a plurality of pixels mounted as a two dimensional array on a suitable substrate, each said pixel including a photosensitive semiconductor and being adapted to be biased in use with a voltage field extending away from the plane of said substrate.

29. A photo sensing element as claimed in claim 28 wherein each said pixel includes a first terminal located on said pixel, distal from said substrate, and a second terminal located toward, adjacent, or on said substrate away from said first terminal.

30. A photo sensing element as claimed in claim 29 wherein said substrate is electrically conductive and serves as a second terminal for each said pixel.

31. A photo sensing element as claimed in any one of claims 28 to 30 wherein each said pixel includes a main body of n-type compound semiconductor.

32. A photo sensing element as claimed in any one of claims 29 to 31 wherein each said pixel includes a highly doped layer of compound semiconductor between said first terminal and said main body.

33. A photo sensing element as claimed in any one of claims 30 to 32 wherein each said pixel includes a highly doped layer of compound semiconductor between said second terminal and said main body.

34. A photo sensing element as claimed in claim 33 wherein said highly doped layer between said second terminal and said main body exhibits low free carrier absorption.

35. A photo sensing element as claimed in any one of claims 31 to 34 wherein said main body comprises Hg-ι__x Cd _x Te semiconductor, where x is approximately 0.21.

36. A photo sensing element as claimed in any one of claims 31 to 35 wherein said main body is epitaxial.

37. A photo sensing element as claimed in any one of claims 32 to 36 wherein said highly doped layers comprise Hg_{1 (}Cd_xTe semiconductor, where x is approximately 0.24 to 0.25.

38. A photo sensing element as claimed in any one of claims 28 to 37 wherein each said pixel includes a passivation layer covering the semiconductor surface.

39. A photo sensing element as claimed in any one of claims 29 to 38 wherein said first terminals are located distal from the substrate, on top of the semiconductor material comprising each said pixel, to allow easy interconnection to a silicon chip comprising signal processing circuitry.

40. A photo sensing element as claimed in any one of claims 28 to 30 wherein each said pixel includes a plurality of semiconductor element portions located in layers on said substrate, each element portion having sensitivity to a predetermined bandwidth.

41. A photo sensing element as claimed in claim 40 wherein said predetermined bandwidths cover different wavelengths.

42. A photo sensing element as claimed in claim 40 to 41 wherein said semiconductor element portions each comprise epitaxial heterojunction layers.

43. A photo sensing element as claimed in claim 42 wherein said epitaxial heterojunction layers are separated by an electrically insulating layer and are continuously consecutive therewith.

44. A photo sensing element as claimed in claims 43 wherein said electrically insulating layer is a low doped semiconductor.

45. A photosensing element comprising a plurality of pixels mounted as a two dimensional array on a suitable substrate, each said pixel including a plurality of semiconductor element portions located in layers on said substrate.

46. A photosensing element as claimed in claim 45 wherein each said semiconductor element portion comprises an epitaxial heterojunction layer.

47. A photosensing element as claimed in claim 46 wherein said epitaxial heterojunction layers are separated by an electrically insulating layer and are continuously consecutive therewith.

48. A photosensing element as claimed in claim 47 wherein said electrically insulating layer is a low doped semiconductor.

49. A photosensing element as claimed in any one of claims 45 to 48 wherein each element portion has a sensitivity to a predetermined bandwidth.

50. A photosensing element as claimed in claim 50 wherein said predetermined bandwidths cover different wavelengths.

51. A photoconductor construction substantially as herein described, with reference to the description of the embodiments.

52. A photoconductor array substantially as herein described, with reference to the description of the embodiments.