WO1996001008A1 - Circuit de raccordement pour applications a grande vitesse - Google Patents

Circuit de raccordement pour applications a grande vitesse Download PDF

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Publication number
WO1996001008A1
WO1996001008A1 PCT/US1995/008184 US9508184W WO9601008A1 WO 1996001008 A1 WO1996001008 A1 WO 1996001008A1 US 9508184 W US9508184 W US 9508184W WO 9601008 A1 WO9601008 A1 WO 9601008A1
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WO
WIPO (PCT)
Prior art keywords
buffer
impedance
output
input
resistor
Prior art date
Application number
PCT/US1995/008184
Other languages
English (en)
Inventor
Lance L. Sundstrom
Original Assignee
Honeywell Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc. filed Critical Honeywell Inc.
Publication of WO1996001008A1 publication Critical patent/WO1996001008A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks

Definitions

  • the present invention relates generally to impedance matching. More particularly, the present invention presents an active termination circuit.
  • Impedance discontinuities can cause reflections that cause ringing (overshoots and undershoots).
  • the harmful side effects of an impedance discontinuity can inadvertently cause circuit voltages to cross logic thresholds resulting in a false triggering. This can be detrimental or even fatal to system performance.
  • SCP single chip package
  • MCM multichip module
  • PWA printed wiring assembly
  • terminating interconnects between devices has become especially important when the propagation delay time of the interconnect between devices exceeds one half of the rise or fall time of the driving devices. This means that reflections from an impedance discontinuity at the end of the interconnect return to the source after the rise or fall time of the driving device and must therefore be added to the timing equations. Under these conditions, the interconnect between devices must be treated as a transmission line.
  • Interconnect 30 couples a first electronic device 50 to a second electronic device 60.
  • Interconnect 30 is comprised of an I/O buffer 40, a transmission line 20, having an impedance ZQ, and an I/O buffer 41.
  • I/O Buffer 40 is comprised of an input buffer 10 and an output buffer 11 while I/O buffer 41 is comprised of an input buffer 12 and an output buffer 13.
  • Output buffer 11 is a tristateable device controlled by an enable line 11a, which is connected to circuitry not shown.
  • enable line 1 la When enable line 1 la is high, output buffer 11 produces an output signal that is the same as the received signal.
  • enable line 11a is low, the impedance of output buffer 11 is high.
  • Output buffer 13 has an enable line 13a which operates in the same manner as enable line 11a. It should be noted that although I/O buffer 40 and electronic device 50 are shown separately many prior art devices physically place I/O buffer 40 within electronic device 50. Likewise for I/O buffer 41 and electronic device 60.
  • the voltage waveforms present at points A through D, in the circuit depicted in Figure la, are shown in Figures lb through Id.
  • the vertical axis represents voltage, while the horizontal axis represents time.
  • Device 50 transmits a signal to device 60 in the following manner.
  • Device 50 generates the signal to be transmitted to device 60.
  • the signal is chosen to be a square wave representing two different logic levels.
  • This signal is received by the input of output buffer 11 , denoted as point A. It is further assumed for the purposes of this description that output buffer 11 is enabled for the duration of the time period depicted in Figures lb through Id. Thus, output buffer 11 produces an output signal closely resembling the received signal.
  • Z L is a high impedance (e.g., a CMOS input)
  • some of the incident wave energy is absorbed by the input protection circuitry of buffer 12, but most of it is reflected back to the source at point B.
  • Z ⁇ is the output mode impedance (occurring when enable 1 la is high) of I/O buffer 41. Reflections continue until the incident wave energy is dissipated. These reflections distort the signal produced by output buffer 11. If the signal distortion is large enough, logic thresholds are crossed more than once resulting in glitches in the received signal at points C and D. The amount of time needed for the reflections to dissipate is referred to as the settling time.
  • Interconnect 31 is comprised of a series terminating resistor 70 connected between the output of buffer 11 and transmission line 20.
  • the impedance of resistor 70, R x is chosen such that the effective output mode impedance, Z s , is close to the impedance of transmission line 20.
  • the effective output mode impedance, Z s is the sum of the output mode impedance of I/O buffer 40,
  • VRt depicts the voltage across the output mode impedance of buffer 11 combined with the voltage across the impedance of resistor 70.
  • this particular configuration of interconnect 31 has several limitations.
  • the effective output mode impedance and the impedance of transmission line 20 form a voltage divider that reduces the magnitude of the voltage step in the transmitted incident wave to Z,-/ (Z s + Z 0 ) times the unloaded voltage step at the output of buffer 11.
  • additional power is consumed by resistor 70 when buffer 11 transitions from one state to another.
  • resistor 70 limits the number of devices I/O buffer 40 can drive.
  • Figure 3a depicts a prior art single parallel terminated interconnect 32.
  • Interconnect 32 has a parallel terminating resistor 75, connected between the input of I/O buffer 41 and ground. In this configuration the impedance of resistor 75 is equal to the impedance of transmission line 20.
  • the voltage waveforms present at points A through D, in the circuit depicted in Figure 3a, are shown in Figures 3b through 3d.
  • interconnect 32 can control reflections.
  • the termination at the input of buffer 12 and the load on buffer 11 is unbalanced.
  • a low-to-high transition is slower than a high-to-low transition.
  • a logic level high signal causes more power dissipation across resistor 75 than a logic level low signal.
  • Figure 4a depicts a prior art Thevenin parallel terminated interconnect 33. Components in Figure 4a, having the same function as in Figure 3 a, have retained the same numerical identification.
  • Interconnect 32 has two parallel terminating resistors 80 and 85.
  • Resistor 80 is connected between the input of buffer 12 and a logic voltage source 87. Depending on the technology of the circuitry, logic voltage source 87 is typically equal to either 3.3 or 5.0 volts.
  • Resistor 85 is connected between the input of buffer 12 and ground. In this configuration the impedance of each resistor 80 and 85 is equal to twice the impedance of transmission line 20 for a parallel Thevenin equivalent impedance equal to Z 0 .
  • interconnect 33 provides balanced line termination and buffer loading at the cost of two resistors and continuous loading of buffer 11. In this case, the dissipation simply shifts from one termination resistor to the other during a logic transition. Thus, one of the two resistors is continuously dissipating power.
  • Figure 5a depicts a prior art AC parallel terminated interconnect 34.
  • Interconnect 32 has a series connected terminating capacitor 90 and resistor 95, or R ⁇ , connected between the input of buffer 12 and ground.
  • the impedance of resistor 95 is equal to the impedance of transmission line 20.
  • the value of terminating capacitor 90 is typically choose to be equal to 200 pF.
  • the voltage waveforms present at points A through D and across resistor 95, in the circuit depicted in Figure 5a, are shown in Figures 5b through 5d.
  • interconnect 34 provides balanced line termination and I/O buffer loading with reduced power dissipation at the cost of a resistor and a capacitor. All passive line terminations present a trade-off between part count, termination quality and power dissipation at the PWA level.
  • a device for terminating a transmission line.
  • the termination device is comprised of a buffer and a matching device.
  • the buffer has an input and an output.
  • the input of the buffer is connected to the transmission line, while the output is connected to an electronic circuit or device.
  • the matching device also has an input and an output.
  • the input of the matching device is connected to the output of the buffer, while the output of the matching device is connected to the input of the buffer.
  • the impedance of the output of the matching device is equal to the impedance of the transmission line.
  • Figure 1 depicts a prior art unterminated interconnect and its associated wave forms.
  • Figure 2 depicts a prior art series source terminated interconnect and its associated waveforms.
  • Figure 3 depicts a prior art single parallel terminated interconnect and its associated waveforms.
  • Figure 4 depicts a prior art Thevenin parallel terminated interconnect and its associated waveforms.
  • Figure 5 depicts a prior art AC parallel terminated interconnect and its associated waveforms.
  • Figure 6 depicts an active termination circuit constructed and operated in accordance with the present invention and waveforms associated with the circuit.
  • Figure 7 depicts several alternate embodiments of an active termination circuit constructed and operated in accordance with the present invention.
  • Figure 8 depicts one embodiment for the internal construction of a tristate buffer utilized in an active termination circuit constructed and operated in accordance with the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 6a illustrates the use of a lower power, latching, active termination circuit 105 constructed and operated in accordance with the present invention.
  • An interconnect 100 couples a first electronic device 150 to a second electronic device 160.
  • Interconnect 100 is comprised of an I/O buffer 140, a transmission line 120, and active termination circuit 105.
  • I/O buffer 140 is comprised of an input buffer 110 and an output buffer 111.
  • the output of buffer 110 is connected to device 150.
  • the input of buffer 111 is connected, at point A, to device 150.
  • the input of buffer 110 and the output of buffer 111 are connected, at a point B, to transmission line 120.
  • Active termination circuit 105 is comprised of a buffer 112 and a matching resistor 130.
  • buffer 112 The input of buffer 112 is connected, at a point C, to transmission line 120.
  • the output of buffer 112 is connected, at a point D, to device 160.
  • Matching resistor 130 is connected in parallel with buffer 112 between point C and point D. It should be noted that in this particular embodiment, active termination device 105 is only capable of receiving signals from transmission line 120.
  • Active termination circuit 105 applies a matched bias impedance at the point of termination. In this embodiment, this is accomplished by selecting an impedance for matching resistor 130, such that the sum of the output impedance of buffer 112, R s , plus the impedance of the matching resistor 130, R x , is equal to the impedance of transmission line 120, Z 0 .
  • active termination circuit 105 actively biases the point of termination to either a logic 0 or a logic 1 voltage. Under static conditions, both point C and point D are at the same logic voltage level, thus no power is dissipated by either matching resistor 130 or in the output impedance of buffer 112.
  • buffer 111 launches an incident wave (or logic transition) down transmission line 120 toward point C.
  • an incident wave logic transition
  • point C it encounters a matching bias impedance to the opposite logic level (the previous logic state). The incident wave energy is absorbed by the matching bias impedance before the matching bias impedance is actively switched to the new logic voltage level.
  • VR ⁇ depicts the voltage across the output impedance of buffer 112 in series with the voltage across the impedance of resistor 130.
  • the vertical axis represents voltage, while the horizontal axis represents time.
  • resistor 130 consumes power only when buffer 112 is undergoing a transition.
  • Termination circuit 105 provides a matched and balanced line termination that eliminates reflections and false triggering.
  • incident wave switching is enabled. With no reflections, and incident wave switching, only the device rise and fall times and single trace delays need be included in the system timing and performance equations. Bus or line settling time, associated with multiple reflections is then removed from the system timing and performance equations.
  • the described active termination circuit 105 provides balanced driver loading and very low power dissipation. This reduces power supply requirements and system costs. It should be noted that the described active termination circuit 105 resistively latches or "toggles" the connected line to its last driven state. This allows buffer 111 to launch a logic transition and then immediately tristate its output. The new logic state is latched by termination circuit. In bussed applications, this minimizes the time that a driver must drive the bus and maximizes the time available for other drivers on the bus to drive it.
  • the termination bias impedance provides positive hysteresis 8 around the buffer's input switching thresholds, resulting in cleaner switching and added noise immunity.
  • FIG. 6a depicts active termination circuit 105 as being implemented using discrete components. Those skilled in the art however, will recognize other methods of implementing active termination circuit 105 consistent with the teachings of this invention. For example, active termination circuit 105 can be implemented at the integrated wafer level.
  • active termination circuit 105 at the integrated wafer level provides several advantages.
  • Figures 7a and 7b depict alternate embodiments for implementing an active termination circuit. As previously discussed, those skilled in the art will recognize several different methods of implementing each embodiment.
  • Figure 7a depicts an active termination circuit 105a.
  • Circuit 105a is comprised of a resistor 210 and an inverting buffers 220a and 220b.
  • the sum of the impedance of resistor 210 plus the output impedance of buffer 220b is designed to be equal the impedance of transmission line 120 shown in Figure 6a .
  • This termination circuit provides continuous active termination at point C. This circuit can only be utilized to receive signals from transmission line 120.
  • the output impedance of buffer 220b can be designed to match the impedance of transmission line 120, depicted in Figure 6a.
  • resistor 210 can be replaced with a component having no impedance, thus eliminating the cost associated with having resistor 210.
  • Figure 7b depicts an active termination circuit 105b.
  • Circuit 105b is comprised of a resistor 210 and an input buffer 250 and an output buffer 260.
  • the total impedance of resistor 210 plus the output impedance of buffer 260, when enabled, are adjusted to match the impedance of transmission line 120 shown in Figure 6a.
  • Active termination circuit 105b has both standard and active terminated input modes controlled by enable line 260a.
  • the output impedance of buffer 260 can be designed to match the impedance of transmission line 120. When this occurs, resistor 210 can be eliminated from the active termination circuit 105 b. Thus, the output of output buffer 260 can be directly connected to point C. This eliminates the cost associated with having resistor 210.
  • output buffer 260 is a tristateable device
  • the terminating bias impedance at point C can be turned on or off via an enable 260a.
  • one embodiment might allow terminations to be programmed via control pins at the PWA level.
  • Programmable terminations could be especially useful in a device having a bus, which is capable of receiving plug in cards. Usually, only those cards at the two ends of the bus should be terminated while the rest of the cards are unterminated. Programmable terminations allow a user to plug in an additional end card which will automatically unterminated the previous end card, and terminate the new end card.
  • input buffer 250 and output buffer 260 can be replaced with inverting buffers.
  • inverting buffers 220a and 220b, depicted in Figure 7a can be replaced with non-inverting buffers. Any combination of inverting and non-inverting buffers can be used as long as the bias at the point of termination is non-inverting with respect to the applied signal. Inverting buffers are especially useful for those transmission line designs that carry binary data in complimented form.
  • Figure 8 depicts the internal construction of one possible embodiment for the tristateable output buffer 260 depicted in Figure 7b. Components in Figure 8, having the same function as in Figure 7b, have retained the same numerical designation. This particular embodiment is designed specifically for a digital data system.
  • a non-inverting buffer 300 and an inverting buffer 310 are connected to point D.
  • a NAND gate 320 receives as input the output of buffer 300 and the signal on enable line 260a.
  • An AND gate 330 receives as input the output of inverting buffer 310 and the signal on enable line 260a.
  • the gate of a p-channel CMOS transistor 340 receives the output of NAND gate 320.
  • the drain of CMOS transistor 340 is connected to a logic voltage source. Depending on the technology of the circuitry, the logic voltage source is typically equal to either 3.3 or 5.0 volts.
  • the gate of a n- channel CMOS transistor 350 receives the output of AND gate 330.
  • CMOS transistor 340 The source of CMOS transistor 340 is connected to the drain of CMOS transistor 350, and resistor 210.
  • the source of CMOS transistor 350 is connected to ground.
  • CMOS transistors 340 and 350 are designed so that the output impedance, when enabled, of each is equal to the impedance of transmission line 120 shown in Figure 6a. This allows output buffer 260 to be designed without using a resistor.
  • this embodiment is particularly well suited for use in a integrated wafer design. Since, the limited number of components and small geometries reduce parasitic effects.

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  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention se rapporte à un circuit de raccordement comprenant un tampon et un dispositif d'adaptation. Le tampon présente une borne d'entrée et une borne de sortie. La borne d'entrée du tampon est connectée à la ligne de transmission, tandis que sa borne de sortie est connectée à un dispositif électronique. Le dispositif d'adaptation présente également une borne d'entrée et une borne de sortie, la borne d'entrée étant connectée à la borne de sortie du tampon, tandis que la borne de sortie du dispositif d'adaptation est connectée à la borne d'entrée du tampon. L'impédance de la borne de sortie du dispositif d'adaptation est égale à celle de la ligne de transmission.
PCT/US1995/008184 1994-06-30 1995-06-29 Circuit de raccordement pour applications a grande vitesse WO1996001008A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US26986794A 1994-06-30 1994-06-30
US08/269,867 1994-06-30

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WO1996001008A1 true WO1996001008A1 (fr) 1996-01-11

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0972343A4 (fr) * 1996-07-19 2000-01-19 Cecil H Kaplinsky Circuit de terminaison dynamique et programmable
US6413718B1 (en) 1996-05-01 2002-07-02 Visible Genetics Inc. Method for sequencing of nucleic acid polymers

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2063025A (en) * 1979-11-09 1981-05-28 Emi Ltd Active termination of a transmission line

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2063025A (en) * 1979-11-09 1981-05-28 Emi Ltd Active termination of a transmission line

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413718B1 (en) 1996-05-01 2002-07-02 Visible Genetics Inc. Method for sequencing of nucleic acid polymers
EP0972343A4 (fr) * 1996-07-19 2000-01-19 Cecil H Kaplinsky Circuit de terminaison dynamique et programmable
EP0972343A1 (fr) * 1996-07-19 2000-01-19 Cecil H. Kaplinsky Circuit de terminaison dynamique et programmable

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