WO1995001870A1

WO1995001870A1 - Design and fabrication of synthetic superconductors

Info

Publication number: WO1995001870A1
Application number: PCT/US1993/008167
Authority: WO
Inventors: Mehmet Rona
Original assignee: Arthur D. Little, Inc.
Priority date: 1993-07-07
Filing date: 1993-08-30
Publication date: 1995-01-19

Abstract

Synthetic superconductors adapated for superconduction at temperatures substantially above those near absolute zero where conventional superconduction has been observed. The superconductors comprise alternating and spaced conducting (20, 22) and lesser conducting (24) strata in a relationship which induces superconductivity as a result of the interplay between the conducting (20, 22) and lesser conducting (24) strata. The type, nature and dielectric spacing (26, 28) of the conducting (20, 22) and the lesser conducting (24) strata produce charge carrier pairing or grouping in the lesser conducting (24) strata by electrostatic forces. The grouped charge carriers provide the superconducting characteristic to the superconductors. The strata (20, 22, 24, 26, 28) may be produced by layered deposition or plating.

Description

DESIGN AND FABRICATION OF SYNTHETIC SUPERCONDUCTORS

RELATED CASE INFORMATION

This Application is a continuation-in-part application of application Serial No. 07/830,472, filed February 3, 1992 which is a FWC Application of 07/222,806, filed July 22, 1988.

FIELD AND BACKGROUND OF THE INVENTION

The present invention relates to a synthetic superconductor operating at temperatures substantially above those temperatures near absolute zero where conventional superconduction has been observed. These elevated superconduction temperatures are already seen in a selected group of chemical compounds in the vicinity of 100°K, for example. Such high temperature superconductors comprise a crystal structure containing a copper oxide formulation in which various elements, including thallium, calcium, yttrium and barium, to name a few, are incorporated. The particular collection of elements leading to compounds which exhibit good superconductivity properties are obtained through trial and error. Various theories have attempted to provide a description of superconductivity. They all attribute such superconductivity to layers of two dimensional copper and oxygen atoms within the crystal lattice. These layers are separated by low conductivity monodirectional filaments or one dimensional chains of copper oxide in the crystal structure.

The production of materials which are superconducting at elevated temperatures suffers from a number of production problems which limit the utility of such superconducting materials. These problems include not only the difficulty of identifying appropriate compositional mixes and production parameters which lead to superconductivity but also the difficulty in producing superconducting materials with mechanical strength, chemical stability and dimensional properties useful for high current applications. The difficulty in identifying new materials with desirable properties is attributable to a lack of an understanding of the superconducting mechanism in the new generation of elevated temperature superconducting materials, and has left these high temperature superconductors without present serious utility in actual industrial applications.

BRIEF SUMMARY OF THE INVENTION

According to the present invention, an understanding of the conduction mechanism of superconduction at elevated superconduction temperatures is first presented. A description is then presented of synthetic superconductor structures and a fabrication which will lead to useful superconductivity at elevated superconduction temperatures.

According to the present invention, a synthetic superconductor is provided having alternating conducting and lesser conducting layers or strata spaced by layers of insulation. The spacing function is provided by any insulating material including dielectrics, free space, etc. The layers, their spacing and conductivity levels are selected to produce electrostatic forces between the free charge carriers of the conducting and lesser conducting layers which cause the carriers in the lesser conducting layers to be electrostatically paired or grouped in small clusters defined by potential wells resulting from the properties and geometry of the layered structure. The resulting construction provides for superconductivity through the interplay of the conducting and lesser conducting layers. The lesser conducting layer is thus central to the exhibited superconductivity.

The superconductors according to the present invention are fabricated, in one embodiment, by depositing or plating layers of the conducting and lesser conducting strata one to several atoms in thickness, separated by an insulator, typically of very low dielectric constant, in order to permit the electrostatic forces required for charge pairing in the ' 5 lesser conducting layers to be strong.

BRIEF DESCRIPTION OF THE DRAWING

These and other features of the present invention are more fully set forth in the solely exemplary detailed description presented below and the accompanying drawing of 10 which:

Figs. 1A, IB, and 1C are crystal structures illustrating prior art superconducting ceramic designs;

Fig. 2 is a structure diagram illustrating the fabrication of a superconductor according to the present 15 invention;

Fig. 3 is a diagram illustrating the electrostatic interaction leading to superconduction according to the present invention;

Fig. 4 is a potential diagram illustrating the 20 electrostatic attraction effects of Fig. 3;

Fig. 5 is a diagram illustrating one form of deposition equipment for producing layered superconducting material of the present invention; and

Fig. 6 is a processing diagram illustrating the steps 25 in the fabrication of a superconductor according to the present invention.

DETAILED DESCRIPTION

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The present invention contemplates a synthetic superconductor effective at elevated superconduction

30 temperatures, in which conductivity is accomplished in a layered structure of alternating conductive and lesser conductive layers. Such an arrangement is distinct from conventional elevated temperature superconducting materials which comprise a crystal of, among other constituents, copper oxide as illustrated in Figs. 1A-1C. As shown in Figs. 1A-1C, crystal structures of the indicated formulation have been analyzed by X-ray diffraction to indicate a plurality of generally parallel planes 12 of copper oxide 14. These are spaced by one dimensional linear chains 16 of copper oxide 18. Additive atoms of thallium, barium, calcium, etc. are interspaced in the crystal to promote free carrier formation. The superconduction is envisioned as occurring near the planes 12. Fabrication of the crystal structure of Figs. 1A-1C includes combining the requisite elements, such as selected combinations of thallium, yttrium, barium or calcium, with copper and their oxides, for example. The controls over fabrication of superconducting materials according to this recipe is not understood and obtaining superconducting results is strictly by trial and error. The crystal structure which results when the lattice is realized is a complex combination of various elements and copper oxide networks without any predictability of results based upon the crystal structure appearance.

By contrast, superconductivity according to the present invention is accomplished by a controlled layering of conducting and lesser conducting strata separated by insulators as generally illustrated in Fig. 2. As shown there, a superconductor according to the present invention comprises a set of conducting layers 20 and 22 separated by a lesser conducting layer 24 with each of the conducting or lesser conducting layers 20, 22 and 24 spaced by insulating layers 26 and 28 which may be a dielectric material or free space. The layered structure is typically assembled on a substrate 30 by plating or particle deposition and may be repeated a plurality of times upon top of the layer 20. Typically the layers 20 and 22 will be the same metal conductor while the layers 26 and 28 will be the same insulating or dielectric material. Various processes may be used to produce each layer. For example, particle deposition by sputtering, and other techniques can be used to produce a disordered amorphous or polycrystalline film layer. Single crystal epitaxial film layers can be grown by chemical vapor deposition (CVD or MOCVD) organo metallic CVD, or high vacuum molecular beam epitaxy (MBE) . Assisted or reactive deposition, liquid melt deposition as well as plating may be used as appropriate.

The layer 24 in one embodiment is achieved by depositing the same material utilized to produce the layers 20 and 22 but at a sufficiently lower thickness in order to lower its overall conductivity according to the theoretical considerations presented below. Typically, the layer 24 may be of a thickness, for example, of three atoms while the layers 20 and 30 may be several times that in thickness. The materials for the layers 20 and 22, and optionally layer 24, are typically chosen to have good electrical conductivity properties and in particular are selected for as many free electrons per atom as can be conveniently obtained. Typical examples of such materials are metal like, gold, silver, beryllium and copper. The partial or lesser conducting layer 24, if of a different material than the metals used for the layers 20 and 22, may be of titanium, or aluminum as examples. None of these examples are intended to be limitations on the metal or its nature for the layers 20, 22 and 24. The theoretical considerations presented below will indicate the guidelines for the use of other materials.

The layers 20 and 24 as well as 22 and 24 are spaced by a thickness, ⁿC/2", which is typically on the order of ten Angstroms, but is more generally governed by the theoretical considerations identified below. It is preferable that the dielectric constant of the layers 26 and 28 separating the layers 20, 24 and 22 be relatively low, typically as close to 1 as is reasonable. This is for practical considerations of dimensioning the layers and not seen as a limitation. Typical examples for the layers 26 and 28 include silicon dioxide, silicon nitride, various fluoride compounds, glasses, and a diamond-like carbon film layer.

While the description above has focused on exemplary layers 20-30 in substantially planar disposition, it is to be understood that the invention is not to be so limited, but includes curved layers as might result from forming the layers as cylinders on a rotating preform. Additionally, the layers could be produced as semiconductor layers with suitable doping. In the case of semiconductor layering in a semiconductor such as gallium arsenide, it is convenient to make the lesser conducting layer of a doped GaAs semiconductor and the higher conductive layer of a grown metal layer or degenerately doped GaAs. The conductive layers would be separated by grown layers of insulator, Al_xGa_μxΑs. The higher conductive layer 20, 22 can have the number of charge carriers in a one cm square area of thickness t equal to or greater than 10¹³. This implies a thickness for this layer greater than 10¹³/n cm, where n is the density of charge carriers per cm³. For the lesser conducting layer 24 the number of charge carriers in a one cm square area of thickness "t" should be less than 10¹². The thickness "t" is then constrained to be less than 10¹²/n cm. If a one atom thick layer is considered, then n is limited to be less than 3 x 10¹⁹/cm³ for the lesser conducting layer. For the higher conducting layer n could exceed 10^2I/cm³.

To understand the specific dimensioning and composition of the superconducting material of Fig. 2 a theoretical explanation illustrated by Figs. 3 and 4 provides useful guidelines. In Fig. 3, first and second conducting plates 40 and 42 are shown to represent respectively the conductors 20 and 22. Centered between the plates 40 and 42 are charge carriers 44 which may be either positive or negative charge carriers typically representing the free or partially free charge carriers in the partially conducting layer 24. In order to develop a field theory for the electrostatic field surrounding the carriers 44 as well as the potential field around them, resort is had to image analysis, in which case an array of additional alternately charged particles 46 are substituted for the plates 40 and 42. The resulting field ' 5 and potential equation results from the superposition of the contributions from each carrier 44 and each particle 46. The resulting field can be summarized in a potential energy diagram illustrated in Fig. 4 as a function of the distance, "d", separating the charge carriers 44 from each other.

10 Different sets of potential curves 48 can be generated for different values of "C". For a range of C's, typically in the 10 Angstrom range, a potential diagram as illustrated in Fig. 4 will result. The potential curve shows a potential well 50 indicating that the carriers 44, contrary to

15 conventional thinking, will not be repulsed from each other but will rather be attracted to each other to a stable separation distance, represented by the bottom of the potential well 50, at the separation "d₀". Returningto the considerations of the conducting layer 40 and 42 in Fig. 3,

20 each of the carriers 44 will cause free carriers in the layers 40 and 42 to move under the influence of the electrostatic effects produced by the carriers 44 creating charge distributions 52 and 54 respectively in each plate as illustrated. The charges in the plates 40 and 42 will cause

25 an attractive effect between the carriers 44. Because of the conductivity of the plates 40 and 42 the charge bunching in plates 40 and 42 produced by one carrier 44 will have no net effect on that carrier 44 but the charge bunching produced by its neighboring carrier 44 will indeed be felt by the

30 first carrier 44 in such manner as to draw the carriers 44 _t together forming pairs despite being of the same charge. For this to function effectively, it is advantageous to have the plates 40 and 42, or the layers 20 and 22, as conductive as possible. On the other hand the layer 24, containing the

35 carriers 44, should have relatively fewer free or partially free charge carriers in order that their electric fields will not be shielded and cancelled, so that effective pairing or grouping in repeating clusters of carriers 44 will occur according to the electrostatics described above. If the charge carriers in the layer 24 are too prevalent, there will result a situation simply reflected by two parallel conductors.

Returning to theory, the dimension of the separation of the conducting layers, "C", is governed by the consideration that the binding energy between the charge carriers 44, considered as the difference between the bottom of the energy well 50 and the asymptotically approached limit of potential energy 54, reached at "d" equal to infinity, varies as a function of a factor representing the conductivity of the layers 20 and 22 over the product of the separation, ^l,C/2" and the dielectric constant of the insulators 26 and 28. Interestingly, hindsight indicates that fitting this theoretical potential energy theory to the experimentally observed results for known materials of the type illustrated in Fig. 1 indicates a substantially perfect fit, confirming the accuracy of the theory in predicting superconductivity.

Given this theory, a more practical approach to achieving superconductivity is achieved by synthesizing materials constituted of layers of the sort illustrated in Fig. 2 using a more controlled approach in which strata of conducting and lesser conducting layers are achieved. Under these theoretical guidelines, the constraints on the dimensions are indeed limited only by the necessity to achieve a potential well effect as illustrated in Fig. 4 and a controlled number of charge carriers, holes or electrons, freely available in the layer 24, as well as a limited number of carriers paired or grouped in each potential well, typically a few electrons or holes as the case may be. The diameter of the grouped carrier ensemble is typically on the same size order, 10 to 15 Angstroms, as the separation, "C", of the conducting layers 20 and 22. The important considerations are thus a relatively good level or density of free charge carriers in the conducting layers 20 and 22 and a more restricted availability in the layers 24. In addition, a separation of the layers as a function of the dielectric constant is also important. Consistent with the above observations the conducting layers 20 and 22 will typically have the number of carriers in a one cm² area be greater than 10¹³. For practical thicknesses, the volume density of carriers will be greater than 10²¹ per cm³. The layers should be of high purity as well. Similarly the partially conducting layers will have volume densities of carriers on the order of 10¹² particles per cm³ or less and a Debye length which is greater than the average interparticle spacing in order to permit the electrostatic fields to act through the partially conducting layers. As the dielectric constant of the insulators 26 and 28 increases, to maintain the same conditions, the separation must decrease. It is therefore practically advantageous to maintain the dielectric constant of the layers 26 and 28 as close to unity as possible. These figures are only quantitative guides and are not to be seen as limitations.

Apparatus for producing the layered structure of the embodiment represented in Fig. 2 can include any form of appropriate deposition, plating or microstructure forming apparatus. Such apparatus is illustrated in Fig. 5 in general in which layers 62, 64, 66 on a substrate 68 are deposited, grown or otherwise built up by any of the processes noted above or any other suitable processes within a vacuum chamber 60. An evacuating apparatus 61 maintains the interior 72 of the chamber 60 at a low enough pressure which prevents interference with the layer generation process. Particles 74 from a source 70, collect on the top surface of the layered structure.

In typical implementation the fabrication process will proceed according to the steps of Fig. 6. Initially, in step 80 the substrate 66 is placed into the chamber 60 and an appropriate vacuum, achieved. With the appropriate vacuum, a subsequent step 82 deposits the first layer 22. Subsequent steps 84, 86, 88, and 90 deposit the layers 28, 24, 26, and 20 as illustrated above. Steps 84 through 90 may be repeated by exiting a decision step 92 on a branch 94 calling for repetition of the layers in a repeating sandwich structure. Alternatively, decision step 92 may limit or terminate the layering according to programmed control produced by a controller 96. The commencement of layer formation may begin at any layer so long as the correct sequence is followed.

In practical application, there will typically be provided within the chamber 60 plural particle sources 70 to accommodate the various materials to be produced in each of the processing steps 82-90. This avoids the necessity to break the vacuum in the processing chamber 60 between each deposited layer in order to install an additional sputtered particle source.

Additional instrumentation may be associated with the processing chamber 60, such as thickness detection instrumentation, in order to automatically terminate deposition as a function of deposited layer thickness.

Vanishing electrical resistance is one of the unique characteristics of superconductors which provides such materials with enormous utility. That is, it is the characteristic of vanishing resistance that enables the conduction of current with minimal loss. Commercial applications for low loss conductors are countless. Thus, while materials having a resistance of approximately zero ohms are most preferable, materials with resistances approaching zero are advantageous in reducing the losses associated with electrical current transmission. Thus, it is desirable to have a material experiencing decreasing or diminishing resistance. The following example describes an illustrative embodiment of the above-described structure and the resulting vanishing resistance observed therein. Example I A square semiconductor chip was prepared having doped GaAs as the higher and lesser conducting layers interleaved between insulating Al₃Ga₇As layers. The doped GaAs layers were approximately 35 Angstroms thick and the insulating layers approximately 60 Angstroms thick. A low frequency AC phase locked measurement was obtained at 4.2°K. More particularly, a one microamp current modulated sinusoidally was applied between the two neighboring contacts on the corners of the square chip. The modulated current was first applied at 70 Hertz and then at 50 Hertz. The voltage drop across the opposing two corner contacts was measured in phase-lock with the applied current. Measuring the resistance with phase-locking renders spurious effects negligible. Irrespective of phase locking frequency, the voltage signal dropped to such a low level that whether or not the current was applied did not make a difference. Hence, it was concluded that the measurement was of vanishing resistance.

The above described structure and process for achieving a superconducting material according to the present invention is described with broad limits as permitted by the indicated theory for superconductivity. It is therefore intended to limit the scope of the invention only in accordance with the following claims.

Claims

In the Claims

1. A heterogeneous multilayer material comprising: a plurality of layers of a first metallic material characterized by a first surface carrier density; at least one layer of a second metallic material characterized by a second surface carrier density lower than said first surface carrier density; and a plurality of electrically insulating layers; wherein each layer of the first metallic material is separated from a layer of the second metallic material by one of said electrically insulating layers, the layers of the first and second metallic material and the electrically insulating layers thinly dimensional so as to cooperate to provide decreasing electrical resistance.

2. The heterogeneous multilayer material of claim 1 wherein the multilayer material includes a plurality of alternative layers of the first and second metallic materials each separated by one of said insulating layers.

3. The heterogeneous multilayer material of claim 1 wherein the electrically insulating layers are of a thickness on the order of 10 A.

4. The heterogeneous multilayer material of claim 1 where the electrically insulating layers are characterized by a dielectric constant that is substantially 1.

5. The heterogeneous multilayer material of claim 1 wherein the first metallic material is selected from the group consisting of a degenerately doped semiconductor, titanium, aluminum, beryllium, gold, silver, and copper.

6. The heterogeneous multilayer material of claim 5 wherein the semiconductor is gallium arsenide.

7. The heterogeneous multilayer material of claim 1 wherein the second metallic material is selected from the group consisting of a non-degenerately doped semiconductor, titanium, and aluminum.

8. The heterogeneous multilayer material of claim 7 wherein the semiconductor is gallium arsenide.

9. The heterogeneous multilayer material of claim 1 wherein each electrically insulating layer consists essentially of Al^a^s (where 0 < x < 1) , oxides, nitrides, fluorides, glasses, and carbon film with a diamond structure.

10. The heterogeneous multilayer material of claim 1 wherein the first metallic material is characterized by a volume density of carriers greater than 10²¹carriers per cm³.

11. The heterogeneous multilayer material of claim 1 wherein the first metallic material is of a thickness such that each layer has a surface carrier density of at least 10¹³ carriers per cm².

12. The heterogeneous multilayer material of claim 1 wherein the second metallic material is characterized by a volume density of carriers greater than 10¹⁹ carriers per cm³.

13. The heterogeneous multilayer material of claim 1 wherein the second metallic material is of a thickness such that each layer has a surface carrier density of at least 10¹² carriers per cm².

14. The heterogeneous multilayer material of claim 1 wherein each layer of the second metallic material one atom thick.

15. The heterogeneous multilayer material of claim 1 wherein each layer of metallic material is substantially pure.

16. The heterogeneous multilayer material of claim 1 wherein each layer of metallic material is of substantially the same thickness.

17. The heterogeneous multilayer material of claim 1 wherein the first surface carrier density is greater than the second surface carrier density.

18. A heterogeneous multilayer material comprising: a first plurality of layers of conductive material characterized by a first surface carrier density, each of said first plurality of layers having a thickness of between approximately one and three atoms; a second plurality of layers of conductive material characterized by a second surface carrier density lower than said first surface carrier density, said second plurality of layers having a thickness of between approximately one and three atoms and being interleaved with said first plurality of layers; and a third plurality of layers of an electrically insulating material, said third plurality of layers being disposed between adjacent ones of said first plurality of layers and said second plurality of layers, said third plurality of layers having a thickness greater than the thickness of said first plurality of layers and said second plurality of layers.

19. The heterogeneous multilayer material recited in Claim 18 wherein said conductive material comprising said first plurality of layers is selected from the group consisting of: degenerately doped semiconductor, titanium, aluminum, beryllium, gold, silver, and copper.

20. The heterogeneous multilayer material recited in Claim 18 wherein said conductive material comprising said second plurality of layers is selected from the group consisting of: non-degenerately doped semiconductor, titanium, and aluminum.

21. The heterogeneous multilayer material recited in Claim 18 wherein said electrically insulating material comprising said third plurality of layers is a dielectric material having a dielectric constant of approximately unity.

22. A heterogeneous multilayer material comprising: a first plurality of layers of conductive material characterized by a first surface carrier density, said conductive material comprising said first plurality of layers being selected from the group consisting of: degenerately doped semiconductor, titanium, aluminum, beryllium, gold, silver, and copper; a second plurality of layers of conductive material characterized by a second surface carrier density lower than said first surface carrier density, said conductive material comprising said second plurality of layers being selected from the group consisting of: non-degenerately doped semiconductor, titanium, and aluminum wherein said second plurality of layers are interleaved with said first plurality of layers; and a third plurality of layers of an electrically insulating material, said third plurality of layers being disposed between adjacent ones of said first plurality of layers and said second plurality of layers, wherein said electrically insulating material comprising said third plurality of layers is a dielectric material.

23. The heterogeneous multilayer material recited in Claim 22 wherein each of said first plurality of layers has a thickness of between approximately one and three atoms.

24. The heterogeneous multilayer material recited in Claim 22 wherein each of said second plurality of layers has a thickness of between approximately one and three atoms.

25. The heterogeneous multilayer material recited in Claim 22 wherein each of said third plurality of layers has a thickness larger than the thickness of said first plurality of layers and said second plurality of layers.

26. The heterogeneous multilayer material recited in Claim 22 wherein said dielectric material comprising said third plurality of layers has a dielectric constant of approximately unity.