WO1994028586A1 - Dispositif a semi-conducteur ayant une resistance elevee a la rupture - Google Patents
Dispositif a semi-conducteur ayant une resistance elevee a la rupture Download PDFInfo
- Publication number
- WO1994028586A1 WO1994028586A1 PCT/JP1994/000884 JP9400884W WO9428586A1 WO 1994028586 A1 WO1994028586 A1 WO 1994028586A1 JP 9400884 W JP9400884 W JP 9400884W WO 9428586 A1 WO9428586 A1 WO 9428586A1
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- WIPO (PCT)
- Prior art keywords
- semiconductor device
- semiconductor
- breakdown voltage
- groove
- high breakdown
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 230000015556 catabolic process Effects 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims description 51
- 238000009792 diffusion process Methods 0.000 claims description 25
- 239000012535 impurity Substances 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000014509 gene expression Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000011521 glass Substances 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000000087 stabilizing effect Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
- H01L29/102—Cathode base regions of thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/747—Bidirectional devices, e.g. triacs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
Definitions
- the present invention relates to a high breakdown voltage semiconductor device.
- grooves are provided by so-called mesa etching so that the Pn junction on the conductor surface is terminated, and glass is filled inside the mesa grooves as a surface stabilizing material. The method is taken.
- base layers 2 a and 2 b made of a p-type diffusion layer are formed on the front side and the back side of the n-type substrate 1.
- Emitter layers 3a and 3b each formed of an n-type diffusion layer are formed in the base layers 2a and 2b, respectively, and a mesa groove 4 is formed so as to surround the outer layer, and the glass 5 is filled therein.
- the Pn abutment between the base and the substrate which is one of the upper and lower sides, becomes a reverse abutment corresponding to the polarity of the applied voltage, and a depletion layer is formed near the base to generate current I will block it. Therefore, in order to obtain a high withstand voltage, it is necessary to prepare a high-resistance substrate in which the breakdown voltage of the pn junction is equal to or higher than the target withstand voltage.
- the high withstand voltage means a withstand voltage of 1200 V or more.
- a substrate with a specific resistance of 30 ⁇ cm should be used as shown in Fig. 13.
- the substrate resistance there are other factors such as crystal defects and impurity contamination in the substrate, unevenness and roughness of the joint surface and mesa groove surface, and the breakdown voltage such as the curvature of the mesa groove surface.
- the substrate resistance In order to obtain a semiconductor element with such a high breakdown voltage, the substrate resistance must be sufficiently high and It is necessary to increase the reverse breakdown voltage between the substrate and the substrate.
- the present invention has been made in view of the above circumstances, and has as its object to provide a high breakdown voltage semiconductor device.
- the distance from the bottom of the mesa groove formed from the first pn junction surface side to the second Pn junction surface is the second pn junction when the same voltage as the target withstand voltage is applied.
- the width of the mesa groove is formed to be larger than the extension of the depletion layer. Further, it is desirable that the groove width of the portion other than the corner of the mesa groove, that is, the groove width of the linear portion is substantially equal to the distance from the bottom of the mesa groove to the second pn junction.
- the first and second semiconductor layers of the second conductivity type formed on the front surface and the back surface of the semiconductor substrate of the first conductivity type are provided inside the first and second semiconductor layers.
- the target When a voltage equal to the withstand voltage V p is applied between the second semiconductor layer and the second semiconductor layer, it is formed from the second pn junction surface according to the impurity concentration N of the semiconductor substrate.
- the depletion layer region is configured not to exceed the bottom of the groove and the width of the groove. In addition, this specifically means that the configuration is such that the following expressions 0) and (2) are satisfied.
- the groove width at the corner portion is formed to be sufficiently larger than the groove width at the portion other than the corner.
- a groove is formed in the diffusion element isolation region by etching or the like prior to diffusion, and a through hole is formed. Keep the depth required for diffusion shallow.
- the present inventors have conducted experiments on the mechanism of breakdown, and have found the following facts.
- the upper pn junction becomes a reverse junction and the depletion layer moves downward from there, as shown in Fig. 15 (a). extend.
- the depletion layer may reach the lower base before reaching the original breakdown voltage of the pn junction, or may extend laterally outward and pass under the mesa groove to separate the diffusion element. It was found that the breakdown occurred due to punch-through in the area or the earlier one. Therefore, in this case, the inherent breakdown voltage of the pn junction can be realized by sufficiently increasing the distance between the pn junction and the width of the mesa groove.
- a + voltage is applied to the upper electrode and the voltage is gradually increased, and the lower pn contact becomes the reverse contact, and the depletion layer is Extends up.
- the breakdown will occur when the depletion layer reaches the bottom of the mesa groove before reaching the intrinsic breakdown voltage of the P n junction.
- the electric field concentrates in the depletion layer near the bottom of the mesa groove due to the curvature of the bottom of the mesa groove and the fixed charge in the glass filled in the mesa groove. . Therefore pn
- the distance from the bottom of the mesa groove to the lower Pn mounting needs to be formed sufficiently larger than the depletion layer width.
- the pn junction withstand voltage near the groove surface is considerably lower than the pn junction withstand voltage in the bulk, so that the width of the mesa groove is formed to some extent and the curvature of the groove surface is reduced.
- the wedge ratio at the corners of the mesa groove is quite common, and in some cases, the groove width must be made considerably large. Therefore, if the width of the mesa groove is the same in all parts as in the past, the mesa groove occupies a considerably large area on the element surface, the effective area of the element decreases, and the ON resistance increases. This is disadvantageous in element characteristics.
- the groove width of the linear portion is formed to be substantially equal to the distance from the bottom of the mesa groove to the lower pn junction, and only the groove width of the corner portion is formed sufficiently larger. This can suppress a decrease in the effective area of the element.
- a base that has a diffusion layer for element isolation around the element has the ability to penetrate and diffuse impurities of the opposite conductivity type to the substrate from both sides of the substrate; If the distance from the bottom of the mesa bottom to the lower pn junction is secured to achieve this, the thickness of the substrate will also increase, requiring high-temperature and long-time diffusion.
- a diffusion step of about 125 to 350 hours is required.
- such long-term diffusion at high temperatures is undesirable because it often damages the substrate such as crystal defects, warpage, and cracks.
- the thickness of the substrate in the element isolation region is sufficiently reduced by etching before the through diffusion step, so that the through diffusion time can be shortened and the thermal damage to the substrate can be reduced.
- the present invention is a semiconductor substrate impurity concentration 1 0 14 cnf 3 below, and a thickness of 2 4 0 ⁇ 111 or more], and those pertaining to the high-voltage Toraiatsuku with 2 0 0 V or more breakdown voltage.
- FIG. 1 is a diagram showing a triac according to a second embodiment of the present invention.
- FIGS. 2 (a) and 2 (b) are diagrams showing a manufacturing process of a triac according to the second embodiment of the present invention.
- FIGS. 3 (a) and 3 (b) are diagrams showing a manufacturing process of a triac according to the second embodiment of the present invention.
- 4 (a) and 4 (b) are process diagrams of manufacturing a triac according to the first embodiment of the present invention.
- FIG. 5 is a diagram showing a substrate resistance for achieving a withstand voltage of 50 ° V and a Pn contact from the bottom of the mesa groove. Diagram showing the relationship with the distance to
- Figure 6 shows the relationship between the chip effective Ei ⁇ ⁇ ⁇ for obtaining 0 N voltage and 0.3 V and the distance between the contacts A 00.
- FIGS. 7 (a) and 7 (b) are diagrams showing a manufacturing process of a triac according to the second embodiment of the present invention.
- FIGS. 8 (a) and 8 (b) are manufacturing processes of a triac according to the second embodiment of the present invention.
- FIGS. 9 (a) and 9 (b) are manufacturing process diagrams of a triac according to the second embodiment of the present invention.
- FIG. 10 is a diagram showing the substrate resistance to obtain a withstand voltage of 2000 V and the distance from the bottom of the mesa groove to the pn contact surface. Diagram showing the relationship with distance
- Fig. 11 shows a conventional triac.
- Figs. 12 (a) and 12 (b) show the conventional triac.
- Figure 13 shows the relationship between the reverse breakdown voltage of the pn junction and the substrate concentration.
- Figure 14 shows the dependence of the depletion layer width on the applied voltage.
- Fig. 15 (a) and Fig. 15 (b) show the depletion layer elongation when a voltage is applied.
- a semi-planar type triac having a withstand voltage of 1,500 V is shown in FIG. 1, and its manufacturing process is shown in FIGS. 2 (a), (b) to 4 (a), (b).
- base layers 12 a and 12 b consisting of a 35-m deep p-type diffusion layer are formed on the front and back surfaces of an n-type silicon substrate 11 having a specific resistance of 60 Qcm and a thickness of 300 in.
- an emitter layer composed of an n-type diffusion layer in the base layers 12a and 12b.
- 13a and b are formed, have a chip size of 7 mm square (effective area of the element is 6.2 mm square), and have a mesa groove with a depth of 85 i / m at the periphery of the chip.
- a glass layer 16 is filled in the mesa groove 15 and a groove 50 m deep is formed outside the glass layer 16.
- a P-type diffusion layer 18 for element isolation is formed from the groove 17. Formed and penetrate the substrate. In this case, the distance from the bottom of the mesa bottom to the lower Pn abutment is 180 ⁇ m.
- the groove width W s of the straight groove is 2 ⁇ ⁇ m, and the groove width of the corner is 3 ⁇ m.
- an n-type silicon substrate 11 having a chip size of 7 mm, a specific resistance of 60 ⁇ cm, and a thickness of 300 in was applied to the silicon oxide film by common photolithography and etching.
- boron is penetrated and diffused from both sides while the mask remains intact to form the P-type diffusion layer 18.
- FIG. 2 (a), FIG. 2 (b)) c At this time, a mixed solution of hydrofluoric acid, nitric acid and acetic acid is used as an etching solution.
- heat treatment is performed at 125 V for 150 hours to diffuse boron atoms.
- the mask Ml is removed, boron is diffused over the entire surface to form a base layer 12 made of a p-type diffusion layer having a thickness of 35 m, and then a mask made of a silicon oxide film is formed. Phosphorus is selectively diffused into 12 to form an n-type emitter layer 13 (FIGS. 3 (a) and 3 (b)).
- a mask made of a silicon oxide film is formed, a mesa groove 15 with a depth of 85 m is formed around the chip on the upper surface by etching, and a glass layer as a surface stabilizing material is applied and formed inside the groove. .
- a metal film is deposited on both surfaces, electrodes and ⁇ 2 (front electrode, back electrode T Titan) are formed by ordinary photolithography and etching, and finally dicing is performed using the groove 17 as the boundary.
- the trial chip is completed (Figs. 4 (a) and 4 (b)).
- Figure 5 shows the relationship between the substrate resistance and the distance from the bottom of the mesa groove to the lower pn junction for achieving a withstand voltage of 1500 V or more, based on our experimental results.
- the lower limit of the impurity concentration N of the substrate is determined from the relationship between the impurity concentration and the breakdown voltage in Fig. 13, and the range of the distance d between the bottom of the mesa groove and the second pn junction can be obtained from the width of the depletion layer when 50 ⁇ ⁇ is applied. From these results, it can be seen that when the specific resistance is 60 ⁇ cm and the distance from the bottom of the mesa to the lower pn junction is 18 mm, a withstand voltage of 1500 V or more can be obtained.
- Fig. 6 shows the results of measuring the relationship between the effective chip area and the Pn contact spacing to achieve an ON voltage of 0.3 V or less when the ON current is 4 OA.
- Toraiatsuku This results from the pn junction base of the pn junction and the bottom side of the upper side length 230 m, the effective area of the element is present invention is 38Itaiotaitaiota delta is 01 ⁇ voltages 1. be obtained sufficiently below 3 V You can see.
- FIGS. 7 (a), 7 (b) to 9 (a) and 9 (b) show a manufacturing process diagram of a mesa-type triac having a withstand voltage of 2000 V as a second embodiment of the present invention.
- This triac has a base layer 22 made of a p-type diffusion layer with a depth of 35 m formed in an n-type silicon substrate 21 with a specific resistance of 70 ⁇ cm and a thickness of 340 m, and has a chip size of 6.4.
- the periphery of the chip has mesa grooves 25a and 25b with a depth of 85.
- the mesa grooves 25 are coated with a glass layer 26.
- the distance from the bottom of the mesa bottom to the lower pn junction is 240 m.
- the width of the mesa groove in the straight part is 200 m, and the corner part is 30 m.
- an n-type silicon substrate 21 having a chip size of 6.4 mm square, a specific resistance of 70 ⁇ cm, and a thickness of 300 urn is prepared (FIGS. 7A and 7B).
- base layers 22a and 22b each made of a 35-m-thick p-type diffusion layer, and then a mask made of a silicon oxide film is formed. Then, phosphorus is selectively diffused into the base layers 22a and 22b to form n-type emitter layers 23a and 23b (FIGS. 8 (a) and 8 (b)).
- a mask made of a silicon oxide film is formed, and a mesa groove 25 a.b with a depth of 85 m is formed around the chip on the upper surface and the lower surface by etching, and a glass as a surface stabilizing material is formed inside the groove.
- Layer 26 is applied.
- a metal film is deposited on both sides, electrodes 27a and 27b are formed by ordinary photolithography and etching, and finally the wafer is diced to complete the triac chip (Fig. (A), Fig. 9) (b)) c
- the distance from the bottom of the mesa groove to the lower pn junction is 24 ⁇ um, and the i!
- FIG. 0 shows the relationship between the substrate resistance and the distance from the bottom of the mesa groove to the lower pn junction for realizing a withstand voltage of 200 OV or more, based on our experimental results.
- the lower limit of the impurity concentration N of the substrate is determined from the relationship between the impurity concentration and the breakdown voltage in Fig.
- Figure 6 also shows the results of measuring the relationship between the chip effective area and the ⁇ junction spacing for achieving a voltage of 1.3 V or less.From Fig. 6, the distance between the upper ⁇ junction and the lower ⁇ It can be seen that the triac of the present invention having an area of 270 m and an effective area of the element of 43 mm 4 ′ can sufficiently obtain an ON voltage of 1.3 V or less.
- Industrial applicability
- a triac having a high withstand voltage and a sufficiently low ON resistance can be obtained.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP94917138A EP0702412A4 (en) | 1993-06-01 | 1994-06-01 | SEMICONDUCTOR DEVICE HAVING HIGH BREAKING RESISTANCE |
US08/564,333 US5900651A (en) | 1993-06-01 | 1994-06-01 | High-withstand-voltage semiconductor device |
NO954863A NO954863L (no) | 1993-06-01 | 1995-11-30 | Halvlederanordning for höytålespenning |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5130649A JPH06342902A (ja) | 1993-06-01 | 1993-06-01 | 高耐圧半導体装置 |
JP5/130649 | 1993-06-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1994028586A1 true WO1994028586A1 (fr) | 1994-12-08 |
Family
ID=15039305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1994/000884 WO1994028586A1 (fr) | 1993-06-01 | 1994-06-01 | Dispositif a semi-conducteur ayant une resistance elevee a la rupture |
Country Status (6)
Country | Link |
---|---|
US (1) | US5900651A (ja) |
EP (1) | EP0702412A4 (ja) |
JP (1) | JPH06342902A (ja) |
CA (1) | CA2164339A1 (ja) |
NO (1) | NO954863L (ja) |
WO (1) | WO1994028586A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10044960B4 (de) * | 2000-09-12 | 2006-05-18 | Semikron Elektronik Gmbh & Co. Kg | Verfahren zur Herstellung eines Leistungshalbleiterbauelements |
FR2956923A1 (fr) * | 2010-03-01 | 2011-09-02 | St Microelectronics Tours Sas | Composant de puissance vertical haute tension |
JP5572531B2 (ja) * | 2010-12-08 | 2014-08-13 | 新電元工業株式会社 | 高信頼性半導体装置の製造方法 |
JP5820710B2 (ja) * | 2011-12-02 | 2015-11-24 | 新電元工業株式会社 | 半導体装置 |
US10103540B2 (en) | 2014-04-24 | 2018-10-16 | General Electric Company | Method and system for transient voltage suppression devices with active control |
US9806157B2 (en) | 2014-10-03 | 2017-10-31 | General Electric Company | Structure and method for transient voltage suppression devices with a two-region base |
WO2023053945A1 (ja) * | 2021-09-29 | 2023-04-06 | 新電元工業株式会社 | 双方向サイリスタ |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5621266B2 (ja) * | 1973-10-05 | 1981-05-18 | ||
JPS5745278A (en) * | 1980-08-29 | 1982-03-15 | Mitsubishi Electric Corp | 3-terminal bidirectional thyristor |
JPH0140505B2 (ja) * | 1980-07-22 | 1989-08-29 | Nippon Electric Co | |
JPH02114669A (ja) * | 1988-10-25 | 1990-04-26 | Sharp Corp | メサ型トライアック |
JPH02184026A (ja) * | 1989-01-11 | 1990-07-18 | Sharp Corp | 半導体装置の形成方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE639633A (ja) * | 1962-11-07 | |||
US3628107A (en) * | 1969-05-05 | 1971-12-14 | Gen Electric | Passivated semiconductor device with peripheral protective junction |
US4190853A (en) * | 1974-07-15 | 1980-02-26 | Hutson Jearld L | Multilayer semiconductor switching devices |
US3996601A (en) * | 1974-07-15 | 1976-12-07 | Hutson Jerald L | Shorting structure for multilayer semiconductor switching devices |
US3972014A (en) * | 1974-11-11 | 1976-07-27 | Hutson Jearld L | Four quadrant symmetrical semiconductor switch |
JPS5346285A (en) * | 1976-10-08 | 1978-04-25 | Hitachi Ltd | Mesa type high breakdown voltage semiconductor device |
FR2574594B1 (fr) * | 1984-12-11 | 1987-01-16 | Silicium Semiconducteur Ssc | Structure integree de triac a commande par diac |
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1993
- 1993-06-01 JP JP5130649A patent/JPH06342902A/ja active Pending
-
1994
- 1994-06-01 US US08/564,333 patent/US5900651A/en not_active Expired - Fee Related
- 1994-06-01 CA CA002164339A patent/CA2164339A1/en not_active Abandoned
- 1994-06-01 EP EP94917138A patent/EP0702412A4/en not_active Withdrawn
- 1994-06-01 WO PCT/JP1994/000884 patent/WO1994028586A1/ja not_active Application Discontinuation
-
1995
- 1995-11-30 NO NO954863A patent/NO954863L/no unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5621266B2 (ja) * | 1973-10-05 | 1981-05-18 | ||
JPH0140505B2 (ja) * | 1980-07-22 | 1989-08-29 | Nippon Electric Co | |
JPS5745278A (en) * | 1980-08-29 | 1982-03-15 | Mitsubishi Electric Corp | 3-terminal bidirectional thyristor |
JPH02114669A (ja) * | 1988-10-25 | 1990-04-26 | Sharp Corp | メサ型トライアック |
JPH02184026A (ja) * | 1989-01-11 | 1990-07-18 | Sharp Corp | 半導体装置の形成方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP0702412A4 * |
Also Published As
Publication number | Publication date |
---|---|
JPH06342902A (ja) | 1994-12-13 |
US5900651A (en) | 1999-05-04 |
NO954863D0 (no) | 1995-11-30 |
CA2164339A1 (en) | 1994-12-08 |
EP0702412A1 (en) | 1996-03-20 |
NO954863L (no) | 1996-01-19 |
EP0702412A4 (en) | 1999-06-09 |
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