WO1994016500A3 - A structured programmable datapath for a digital processor - Google Patents

A structured programmable datapath for a digital processor Download PDF

Info

Publication number
WO1994016500A3
WO1994016500A3 PCT/US1993/012573 US9312573W WO9416500A3 WO 1994016500 A3 WO1994016500 A3 WO 1994016500A3 US 9312573 W US9312573 W US 9312573W WO 9416500 A3 WO9416500 A3 WO 9416500A3
Authority
WO
WIPO (PCT)
Prior art keywords
device layers
digital processor
layers
basic cell
noring
Prior art date
Application number
PCT/US1993/012573
Other languages
French (fr)
Other versions
WO1994016500A2 (en
Inventor
Le Trong Nguyen
Ho Dai Truong
Original Assignee
S Mos Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S Mos Systems Inc filed Critical S Mos Systems Inc
Publication of WO1994016500A2 publication Critical patent/WO1994016500A2/en
Publication of WO1994016500A3 publication Critical patent/WO1994016500A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A digital processor datapath comprising a plurality of bit slices (202) arranged on a chip in mirrored pairs (204), each bit slice (202) comprising a plurality of basic cells (203), wherein adjacent bit slices (202) form channelless boundaries therebetween. Each basic cell (203) comprises a plurality of device layers. The plurality of device layers are identical for each basic cell (203). A plurality of mask programmable conducting layers are formed over said device layers. The mask programmable conducting layers and the device layers are selectively interconnected, so that each basic cell (203) forms one of the electronic functions comprising multiplexing, inverting, latching, NANDing, NORing, exclusive ORing and exclusive NORing.
PCT/US1993/012573 1992-12-31 1993-12-23 A structured programmable datapath for a digital processor WO1994016500A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US99794792A 1992-12-31 1992-12-31
US07/997,947 1992-12-31

Publications (2)

Publication Number Publication Date
WO1994016500A2 WO1994016500A2 (en) 1994-07-21
WO1994016500A3 true WO1994016500A3 (en) 1994-09-01

Family

ID=25544590

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/012573 WO1994016500A2 (en) 1992-12-31 1993-12-23 A structured programmable datapath for a digital processor

Country Status (1)

Country Link
WO (1) WO1994016500A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0113828A2 (en) * 1983-01-12 1984-07-25 International Business Machines Corporation Master slice semiconductor chip having a new multi-function FET cell
EP0332419A2 (en) * 1988-03-10 1989-09-13 Cirrus Logic, Inc. Integrated circuit
WO1991018447A1 (en) * 1990-05-15 1991-11-28 Siarc BASIC CELL FOR BiCMOS GATE ARRAY

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0113828A2 (en) * 1983-01-12 1984-07-25 International Business Machines Corporation Master slice semiconductor chip having a new multi-function FET cell
EP0332419A2 (en) * 1988-03-10 1989-09-13 Cirrus Logic, Inc. Integrated circuit
WO1991018447A1 (en) * 1990-05-15 1991-11-28 Siarc BASIC CELL FOR BiCMOS GATE ARRAY

Also Published As

Publication number Publication date
WO1994016500A2 (en) 1994-07-21

Similar Documents

Publication Publication Date Title
EP1034686A4 (en) A low latency shared memory switch architecture
FR2670322B1 (en) SOLID STATE MEMORY MODULES AND MEMORY DEVICES CONTAINING SUCH MODULES
FR2687817B1 (en) THIN INTEGRATED CIRCUIT CARD AND MANUFACTURING METHOD.
NO904757D0 (en) MODULE DEVICE FOR RECEIVING, COLLECTING AND TRANSFERING SEISMIC DATA IN MULTIPLE MULTIPLE LEVELS.
TW357458B (en) Re-configurable application specific device
DE69635603D1 (en) Bump contact for a printed circuit board and semiconductor module with the same
EP0707316A3 (en) Semiconducteur device and method for fabricating the same, memory core chip and memory peripheral circuit chip
FR2591770B1 (en) DATA PROCESSING DEVICE IN THE FORM OF MULTIPLE PARALLEL DATA PROCESSING MODULES, MULTIPLE REDUNDANCY CLOCK DEVICE HAVING SEVERAL RECIPROCAL AUTOSYNCHRONIZATION CLOCK CIRCUITS FOR USE IN SUCH A DATA PROCESSING DEVICE AND CIRCUIT IN SUCH A CLOCK DEVICE
DE69219017T2 (en) Personal data card made from a polymeric thick film circuit
KR910010508A (en) Semiconductor devices
DE69217524D1 (en) Test circuit provided in digital logic circuits
DE69822368D1 (en) Semiconductor memory circuit with a selector for multiple word lines, and test method therefor
GB9616540D0 (en) Integrated circuit device manufacture
ES549413A0 (en) A PROCEDURE FOR PRODUCING A MULTIPLE LAYER CIRCUIT BOARD BASED ON CERAMIC AND COPPER.
DE69625571T2 (en) Semiconductor memory with a small chip size and reduced redundancy access time
DE69517072T2 (en) Semiconductor memory device test circuit with data encryption function
TW359036B (en) Semiconductor memory
NO983997D0 (en) Self-compressing surge arrester module and method for manufacturing the same
DE68921780T2 (en) Redundancy circuit built into a semiconductor memory device.
DE68909666D1 (en) Crosspoint circuit element between two data bus lines.
WO1994016500A3 (en) A structured programmable datapath for a digital processor
TW337614B (en) A semiconductor device
DE68915050D1 (en) Chip enable input circuit in a semiconductor memory device.
DE69324020T2 (en) Semiconductor memory with redundant circuit
TW338812B (en) Cell apparatus and method for use in building complex integrated circuit devices

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP

AK Designated states

Kind code of ref document: A3

Designated state(s): JP

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)