WO1994016487A2

WO1994016487A2 - Self powered integrated circuit modules

Info

Publication number: WO1994016487A2
Application number: PCT/US1993/009691
Authority: WO
Inventors: Bobby L. Buchanan; Edward A. Burke; Roger G. Little
Original assignee: Spire Corporation
Priority date: 1992-10-16
Filing date: 1993-10-07
Publication date: 1994-07-21
Also published as: WO1994016487A3

Abstract

A microprocessing module (100) is powered by radio-nuclide voltaic-junction batteries (114). The microelectronics circuitry (104) includes a clock circuit unit (120), a central processing unit with an arithmetic logic unit (122), a read only memory (124), and a random access memory (126). The input/output circuitry includes a serial input/output interface (128), a parallel input/output interface (130), and a priority interrupt controller (132). The microprocessor module (100) also has a control bus (108) and a data bus (106).

Description

TITLE: SELF POWERED INTEGRATED CIRCUIT MODULES

1. Field of the Invention

The present invention relates to integrated circuits, and more particularly, to microelectronic circuits and power supplies therefor.

2. The Prior Art

_. As is well known, an integrated circuit may be a complete functional element or system containing transistors, diodes, resistors, reactors and interconnecting conductors, all structured on and with a semiconductor wafer composed, for example, of silicon, gallium arsenide or indium phosphide. Typically although these components constitute a chip, that may be only a few millimeters square, they are encapsulated in a larger package. Much of the additional bulk of this package is mandated by relatively large pins or terminals which must be delicately connected to the circuit for input and output signals and power.

Two of the major advantages of integrated circuits are small size and high reliability. Both of these advantages are affected by the manner and source of the power delivery. Power supplies tend to be large and to require thermal cooling because of heat dissipation, thereby adding significantly to the overall size of integrated circuit systems. The delivery of power, particularly from AC to DC converters, generates noise which tends to interfere with data and control signals within and among the components to which the power is applied. It is desired that the manner and source of power delivery for integrated circuits be improved in order to further reduce the size of integrated circuit systems and to further increase their reliability.

RELATED APPLICATION This application is a continuation-in-part of Application Serial No. 672,879, filed March 18, 1991, in the names of two of the inventors herein, for High Energy Density Nuclide-Emitter, Voltaic-Junction Battery, the specification and drawings of which are incorporated herein by reference. BRIEF DESCRIPTION OF THE INVENTION The object of the present invention is to decrease the size and to increase the reliability of a microelectronic unit by integration therewithin of radio-nuclide voltaic-junction power in addition to microelectronic circuitry.

The present invention is based on the fact that a radio-nuclide voltaic-junction battery generally is a small fraction of the size of a chemical battery and a much smaller fraction still of a conventional AC to DC converter. More specifically it has been found that a radio-nuclide voltaic-junction battery with sufficient power to run part or all of a microelectronic circuit may be commensurate in size with that circuit.

The present invention structurally provides an internally powered integrated circuit comprising: an insulating encapsulation, which presents externally accessible terminals and which encloses a semiconductor wafer having doped regions; a radio-nuclide voltaic-junction battery; and a network of conductors bonded to the wafer and constituting, with its doped and other regions, a transistorized circuit having signal leads operatively connected to the externally accessible terminals and power leads operatively connected to the radio-nuclide voltaic-junction battery. The externally accessible terminals are in various forms, for example, either metallic pins that project through the surface of the encapsulation or, in limited cases, optical or capacitive couplings that do not.

In a preferred form the radio-nuclide voltaic-junction is a novel high energy density electric cell or stack of cells comprising a nuclear source of relatively high energy radiation and concomitant heat, a semiconductor junction incorporating an inorganic crystalline compound of Group III and Group V elements or other radiation damage resistant compounds such as silicon carbide and copper indium diselenide, characterized power generation in response to the nuclear source, and an enclosure having a sufficiently high thermal impedance to retain therewith a sufficient quantity of the heat generated by the nuclear source for maintenance of the semiconductor junction above a predeter inely high annealing temperature during operation. The nuclear radiation includes energetic radiation such as alpha, beta or gamma emissions or combinations thereof. The semiconductor junction, for example, includes compounds of indium and phosphorous differentially treated with N or P type dopants. The thermal impedance is composed of a thermal insulator such as a ceramic electrical non-conductor. In this battery, damage to the semiconductor junction resulting from the highly energetic emissions from the nuclear source is repaired by annealing in real time at the predetermined temperature maintained within the insulating enclosure.

The self-powered integrated circuit above described is such that each bias voltage is supplied by a direct current source in the immediate locale required. The contemplated radio-nuclide voltaic-junction batteries are such that sufficient power is delivered throughout a useful life that is tailored to be commensurate with the useful life of the product in which it is incorporated. The result is a microelectronic system which avoids the noise and minimizes the unwanted heat that usually attends elongated metallic conductors connected to remote power sources.

Other objects of the present invention will in part be obvious and will in part appear hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

For a fuller understanding of the nature and objects of the following specification, which is taken in connection with the accompanying drawings wherein:

Fig. 1 is a schematic drawing of self-powered integrated circuits in the form of a microcomputer embodying the present invention;

Fig.2 is a perspective mechanical view, of the integrated circuit chips comprising the microcomputer of Fig. 1 mounted on a modified multichip carrier;

Fig. 3 is a cutaway view of a portion of the chip carrier of Fig. 2 showing a single radio-nuclide battery mounted on the insulated structure and substrate of the multichip carrier;

Fig. 4 is an exploded view of a radio nuclide battery showing several semiconductor power cells and the associated thermal control and shielding package;

Fig. 5 is an exploded view of a single semiconductor showing the two semiconductor dies comprising the cell with the radioactive source material on the bottom layer;

Fig. 6 is a static RAM (SRAM) memory chip based upon CMOS technology with a built in radio-nuclide battery to insure a non-volatile memory.

Fig. 7 is an electrical schematic of the SRAM memory cells on the chip shown in Fig. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The Microcomputer of Figs. 1 and 2 The microprocessor module of Fig. 1 and Fig. 2, shown generally at 100, comprises microelectronic chips 102, which incorporate circuitry 104. As will be explained in detail below, chips 102 are mounted on a modified multichip carrier as shown in Fig. 2. The modified multichip carrier provides a very high density of interconnects with minimum inductive and capacitive power losses and provides a very high chip packing density. The chips are mounted on an insulating encapsulation 105, which consists of metal conductors separated by an organic deposited thin film. This structure is mounted on a substrate (typically ceramic or silicon) which presents externally accessible terminals 112.

The chips 102 are formed on semiconductor wafers, which preferably are composed of silicon or gallium arsenide. The semiconductor chips are provided with a distribution of P and N doped regions, and a network of conductors bonded to the semiconductor wafers and constituting therewith transistorized circuitry 104. Circuitry 104 includes internal (on chip) and external (in the insulating structure 105) data buses 106 and a control buses 108. The components of circuitry 104 are powered by radio-nuclide batteries 114 and to be described in detail below, which are mounted on and incorporated into some of the circuitry of chip 102 in one embodiment or immediately adjacent to the circuit chips on the insulating structure 105 in another embodiment.

As shown, microelectronics circuitry 104 is a microprocessor organized conventionally with processing elements, memory elements, and input/output elements. The processor chips include a clock circuit unit (CCU) 120 and a central processing unit (CPU) 122 having and arithmetic/logic unit. The memory chips include a read only memory (ROM) 124 and a random access memory (RAM) 126. The input/output modules include a serial input/output interface (SIO) 128, a parallel input/output interface (PIO) 130 and a priority interrupt controller (PIC) 132.

The functions of these components are well-known. ROM 124 stores the instructions of permanent executable programs for booting the microprocessor and performing other tasks, and RAM 126 stores programs of instructions, operand data and result data, which ordinarily in the past have been volatile. CCU 120, times the execution rates of the microprocessor, often at rates in the megahertz range, and CPU 122 executes instructions received from ROM 124 and RAM 126 on the basis of associated operand data from RAM 126 to produce associated result data to RAM 126. SIO 128 and PIO 130 receive and transmit signals via pins 112 under control of PIC 132, which determines the priority sequencing of signal reception and transmission. The interaction of the foregoing modules is effected via control bus 108 and data bus 106, which are connected variously to pins 112.

It will be observed in the illustrated embodiment that none of the chips are provided with power from outside the multichip carrier module. In accordance with the present invention, each of the chips is provided with DC power internally from one or more radio-nuclide voltaic-junction batteries 114.

The Radionuclide Voltaic Junction Battery of Figs. 3, 4, 5. A preferred battery in accordance with the present invention is shown in Fig. 4 as comprising a stack 222 of alternating emitting nuclide and semiconductor strata, a high thermal impedance housing 224 that retards heat transfer from within stack 222, absorbs any penetrating nuclear radiation escaping from stack 222, and provides an external casing for the voltaic cell. The electrical output of stack 222 is established across a positive terminal 230 and a negative terminal 232. Negative terminal 232 connects electrically to the ground plane 228 of the insulating structure shown in Fig. 3. Positive terminal 230 projects through an opening in the electrically insulating housing 224 shown in Fig. 4.

As shown, stack 222 is characterized by four superposed power cells of the type shown in Fig. 5. The vertical thickness of the material shown in Fig. 5 is five times greater than would appear in an exact scale drawing, in order to make clear the component strata. Each power cell includes a pair of semiconductor junction strata 234 between which is sandwiched a radio-nuclide emitter stratum 236. Each semiconductor- junction stratum typically ranges in thickness from 10 to 250 microns. At the lower end of this stack, the semiconductor junction stratum (e.g. of indium phosphide) , in one form is deposited on a substrate composed, for example of silicon 239. Each radio-nuclide emitter stratum typically ranges in thickness from 0.1 to 5 microns. The upper thickness limit is determined by undue self absorption of emitted particles. Each semiconductor junction has an electrically positive face region 238 and an electrically negative face region 240. Positive face region 238 is established by subjection to a P-dopant selected, for example in the case of indium phosphide, from the class consisting of zinc and cadmium. Negative face region 240 is established by subjection to an N-dopant selected for example, from the class consisting of silicon and sulfur. A lead from positive face region 238 and a lead 244 from negative face region 240 connect into the remainder of the electrical system.

In one form emitter strata 236 produce alpha particles characterized by a nonenergetic energy level in excess of 4.5 MeV and ranging upwardly to about 6.5 MeV and ordinarily 5 to 6.1 MeV. In another form, emitter strata 236 produces beta particles having a maximum energy level in excess of 0.01 MeV and ranging upwardly to about 3.0 MeV. Typical compositions of emitter strata 236 are selected from the class consisting of the isotop ^res listed in the following ^ table, in which Emax refers to maximum energy and T. ,_ to half life:

Preferably, voltaic junction strata 234 are inorganic semiconductors which are binary, ternary and/or quaternary compounds of Group III and Group V elements of the Periodic Table. Preferred Group III elements are selected from the class consisting of boron, aluminium, gallium and indium. Preferred Group V elements are selected from the class consisting of phosphorous, arsenic, and antimony. These compounds are typified by the class consisting of AlGaAs, GaAsP, AllnP, InAlAs, AlAsSb, AlGalnP, AlGalnAs, AlGaAsSb, InGaAs, GaAsSb, InAsP, AlGaSb, AllnSb, InGaAsP, AlGaAsSb, and AlGalnSb. Additional compound semiconductors with demonstrated radiation damage resistance include silicon carbide, SiC, and copper indium diselenide, CuInSe„.

EXAMPLES The batteries of the present invention are specifically illustrated by the configuration of the battery of Figs. 3, 4 and 5, in which voltaic junction 234 is an indium phosphide stratum, opposite face regions of which are implanted with (1) zinc ions to establish a P-region and (2) silicon ions to establish an N-region. Specific parameters for one particular indium phosphide battery of this example using Cm-244 for the radionuclide emitter are as follows:

TABLE II

Another example suitable for providing CMOS-RAM standby power and direct incorporation into a RAM chip has the following parameters:

TABLE III

In one version of these examples, the emitter stratum is composed of Pu-238. In another version, the emitter stratum is composed of Sr-90. Each emitter stratum is approximately 1.5 micrometers in thickness. Thermal insulating enclosure 224 is composed of ceramic. The thickness and composition of insulating enclosure 224 is selected to maintain the temperature of stack 222 at 50° in an environment where the temperature (1) is no greater than 20°C, i.e. for space where the cell is shielded from heating by solar radiation, or (2) no greater than 35°C, i.e. for terrestrial applications in which the cell operates at room or body temperatures below 100°c. It will be observed that in the illustrated microprocessor, each of chips 120, 122, 124, 126, 128, 130 and 132 is shown as being powered by its own radio-nuclide voltaic-junction battery. It is to be understood that in other embodiments, plural batteries are located at selected locations which are contiguous with or an intrinsic part of the integrated circuit chip. In this way true distributed power can be provided in accordance with design requirements. The Self Powered Component of Figs. 6 and 7 Also commonly occurring in the circuitry of Figs. 1 and Fig. 2 is a self-powered random access memory chip 300. As shown in Fig. 6, this RAM includes an array of one-bit storage circuits 310 arranged at the intersections of rows and columns on a silicon chip 300. Standby power is provided by the radio-nuclide battery 320. A circuit diagram of a typical CMOS static RAM (SRAM) memory cell is .shown in Fig. 6. It consists of six transistors (MOSFET's) 311 to 316. When transistor 311 is OFF (not conducting) and transistor 312 is ON the cell is read as containing a ZERO and when the reverse holds it is read as containing a ONE. The state of the cell can be changed or read by applying a voltage bias to the word-line 317. The conducting states of transistor 311 and transistor 312 can be detected through the bit lines 318 and 319 when transistor 313 and transistor 314 are turned ON. A ZERO can be read into the memory cell by increasing the voltage on bit line 318 and decreasing the potential on bit line 319. The result is that the transistor 313 is turned ON and transistor 314 is turned OFF. This leads to switching transistor 312 ON and transistor 311 OFF and the cell is left in a ZERO state. The memory cell can best be set in a ONE state by decreasing the voltage on bit line 318 and increasing the voltage on bit line 319. Transistors 315 and 316 limit the current through the cell and replace charge lost by leakage, thereby maintaining the information in the cell. Operation of the Illustrated Self-Powered Microelectronic Circuitry The batteries of the present invention incorporate semiconductors with three unique features: (1) relatively high radiation resistance, (2) continued photovoltaic function at elevated temperatures, and (3) real time annealing of radiation damage in the same temperature range. These features support a high energy density radio-nuclide battery operating with relatively high energy beta and/or alpha particle sources. The design of these batteries takes into consideration the rapidity of annealing of radiation damage in InP when irradiated at 100° C, the continued operation during annealing, the tolerance of different intensities of alpha and beta radiation for different applications, and the useful battery life which must be commensurate with the intended life of the circuitry as a whole. Annealing at elevated tempera- ture supports a large dose rate with minimal degradation in power output.

In a typical InP battery of the present invention, a

Pm-147 silicon cell has the following characteristics. T. ,_~

2 refers to half-life, Emax refers to maximum energy, Ci/cm'^' refers to curies per square centimeter, BOL refers to "Beginning Of Life", EOL refers to "End Of Life", W refers to watts and h refers to hours.

TABLE IV

TT E Activity Output (5 years)

2 Years MeV Ci/cm BOL ₃ EOL ₃ Total ₃

W/cm W/cm W-h/cm 2.62 0.230 1.50 1000 266 24.3

As seen in Fig. 1, all power within the illustrated microcomputer is internally generated. Only the control bus and the data bus are connected to pins 112 of Fig. 2. In a typical integrated circuit, where each gate or switch is of the order of 50 micrometers in maximum extent, a radio-nuclide standby battery is of the order of 0.06 centimeters in maximum extent.

Claims

WHAT IS CLAIMED IS:

1. A self powered microelectronic unit comprising:

(a) an insulating encapsulation presenting externally accessible terminals;

(b) a semiconductor wafer having doped regions within said encapsulation;

(c) a radio-nuclide voltaic-junction battery having terminals within said encapsulation;

(d) a network of conductors bonded to said wafer within said encapsulation;

(e) said conductors and said doped regions constituting a transistorized circuitry having signal leads and power leads;

(f) said signal leads being connected to said externally accessible terminals;

(g) said power leads being connected to said terminals of said battery.

2. The microelectronic unit of claim 1 wherein said battery comprises:

(a) a semiconductor junction incorporating an inorganic crystalline compound of Group III and Group V elements of the Periodic Table characterized by a predetermined annealing temperature for defects therein; (b) a nuclear source of relatively high energy radiation and concomitant heat, said radiation causing generation of said defects in said semiconductor junction; and

(c) a thermal impedance enclosure for said nuclear source and said semiconductor-junction for retaining therewithin a sufficient quantity of the heat generated by said nuclear source to maintain a functional relationship between said generation of defects and said predetermined annealing temperature during operation.

3. The microelectronic unit of claim 1 wherein said terminals are battery terminals.

4. The microelectronic unit of claim 3 wherein said terminals are in a distributed in a rectangular manner.

5. The microelectronic unit of claim 1 wherein said terminals are microelectronic chip terminals.

6. The microelectronic unit of claim 5 wherein said terminals are distributed in a rectangular manner.

7. The microelectronic unit of claim 2, wherein said nuclear source is a beta emitter.

8. The microelectronic unit of claim 2 wherein said nuclear source is an alpha emitter.

9. The microelectronic unit of claim 2 wherein said Group III elements are selected from the class consisting of boron, aluminum, gallium and indium.

10. The microelectronic unit of claim 2 wherein said Group V elements are selected from the class consisting of phosphorous, arsenic and antimony.

11. The microelectronic unit of claim 2 wherein the normal operating temperature within said thermal impedance enclosure is at least as great as 50°C.

12. The microelectronic unit of claim 2 wherein said semiconductor-junction is a stratum, one surface of which is characterized by a p-dopant and the other surface of which is characterized by an n-dopant.

13. The microelectronic unit of claim 2 wherein said p-dopant is selected from the class consisting of zinc and cadmium, and said n-dopant is selected from the class con¬ sisting of silicon and sulfur.

14. The microelectronic unit of claim 2 wherein said nuclear source is a radionuclide selected from the class consisting of alpha, and gamma emitters.

15. The microelectronic unit of claim 2 wherein said semiconductor junction contains indium phosphide.

16. The microelectronic unit of claim 1 wherein said battery comprises:

(a) a stack of power cells including radio-nuclide emitter strata and voltaic junction strata;

(b) said radionuclide emitter strata constituting a nuclear source of relatively high energy radiation and concomitant heat;

(c) said voltaic junction strata being composed of semiconductor compounds of Group III and Group V elements of the periodic table subject to generation of mobile defects therein characterized by a predetermined annealing temperature;

(d) a thermal impedance enclosure for said stack for retaining therewithin a sufficient quantity of heat generated by said nuclear source to maintain said semiconductor junction strata above said predetermined annealing temperature during operation;

(e) said semiconductor junction strata being characterized at their opposite surfaces by p-regions and n-regions, positive conductor terminals being operatively connected to said p-regions, negative conductor terminals being operatively connected to said n-regions;

(f) said positive conductor terminals and said negative conductor terminals being accessible externally of said thermal impedance enclosure.

17. The microelectronic unit of claim 12, wherein said nuclear source is an alpha emitter.

18. The microelectronic unit of claim 12 wherein said nuclear source is a beta emitter.

19. The microelectronic unit of claim 12 wherein said source is a gamma emitter.

20. The microelectronic unit of claim 12 wherein said Group III elements are selected from the class consisting of boron, aluminium, gallium and indium.

21. The microelectronic unit of claim 12 wherein said Group V elements are selected from the class consisting of phosphorous, arsenic and antimony.

22. The microelectronic unit of claim 12 wherein the normal operating temperature within said thermal impedance enclosure is at least as great as 50°C.

23. The microelectronic unit of claim 12 wherein said semiconductor strata have opposed faces characterized by a p-dopant and an n-dopant.

24. The microelectronic unit of claim 19 wherein said said p-dopant is selected from the class consisting of zinc and cadmium, and said n-dopant is selected from the class consisting of silicon and sulfur.

25. The microelectronic unit of claim 12 wherein said nuclear source is a radio-nuclide selected from the class consisting of alpha, beta and gamma emitters.

26. The microelectronic of claim 12 wherein said semiconductor junction contains indium phosphide as its characteristic ingredient. 27. A self powered microelectronic gate comprising:

(a) an insulating encapsulation presenting externally accessible terminals;

(b) a semiconductor wafer having doped regions within said encapsulation;

(c) a radio-nuclide voltaic-junction battery mounted on said wafer and having terminals within said encapsulation;

(d) a network of conductors bonded to said wafer within said encapsulation;

(e) said conductors and said doped regions constituting transistorized circuitry having signal leads and power leads;

(f) said signal leads being connected to said externally accessible terminals;

(g) said power leads being connected to said terminals of said battery.

28. The microelectronic unit of claim 23 wherein said battery comprises:

(a) a semiconductor junction incorporating an inorganic crystalline compound of Group III and Group V elements of the Periodic Table characterized by a predetermined annealing temperature for defects therein;

(b) a nuclear source of relatively high energy radiation and concomitant heat, said radiation causing generation of said defects in said semiconductor junction; and (c) a thermal impedance enclosure for said nuclear source and said semiconductor-junction for retaining therewithin a sufficient quantity of the heat generated by said nuclear source to maintain a functional relationship between said generation of defects and said predetermined annealing temperature during operation. 29. A self powered microelectronic logic unit comprising:

(a) an insulating encapsulation presenting externally accessible terminals;

(b) a semiconductor wafer having doped regions within said encapsulation;

(d) a network of conductors bonded to said wafer within said encapsulation;

(f) said signal leads being connected to said externally accessible terminals; (g) said power leads being connected to said terminals of said battery. 30. The microelectronic logic unit of claim 25 wherein said battery comprises:

(b) a nuclear source of relatively high energy radiation and concomitant heat, said radiation causing generation of said defects in said semiconductor junction; and

31. A self powered microelectronic random access memory comprising:

(a) an insulating encapsulation presenting externally accessible terminals;

(b) a semiconductor wafer having doped regions within said encapsulation;

(d) a network of conductors bonded to said wafer within said encapsulation;

(f) said signal leads being connected to said externally accessible terminals;

(g) said power leads being connected to said terminals of said battery;

(h) said random access memory being non-volatile. 32. The microelectronic random access unit of claim 31 wherein said battery comprises:

(c) a thermal impedance enclosure for said nuclear source and said semiconductor-junction for retaining therewithin a sufficient quantity of the heat generated by said nuclear source to maintain a functional relationship between said generation of defects and said predetermined annealing temperature during operation. 33. A self powered microelectronic read only memory comprising:

(a) an insulating encapsulation presenting externally accessible terminals;

(b) a semiconductor wafer having doped regions within said encapsulation;

(d) a network of conductors bonded to said wafer within said encapsulation;

(f) said signal leads being connected to said externally accessible terminals;

(g) said power leads being connected to said terminals of said battery.

34. The read only memory of claim 33 wherein said battery comprises : (a) a semiconductor junction incorporating an inorganic crystalline compound of Group III and Group V elements of the Periodic Table characterized by a predetermined annealing temperature for defects therein;

35. A self powered microelectronic crystal clock unit comprising:

(a) an insulating encapsulation presenting externally accessible terminals;

(b) a semiconductor wafer having doped regions within said encapsulation;

(d) a network of conductors bonded to said wafer within said encapsulation;

(f) said signal leads being connected to said externally accessible terminals;

(g) said power leads being connected to said terminals of said battery.

36. The microelectronic crystal clock unit of claim 31 wherein said battery comprises:

(c) a thermal impedance enclosure for said nuclear source and said semiconductor-junction for retaining therewithin a sufficient quantity of the heat generated by said nuclear source to maintain a functional relationship between said generation of defects and said predetermined annealing temperature during operation. 37. A self powered microelectronic central processing unit comprising:

(a) an insulating encapsulation presenting externally accessible terminals;

(b) a semiconductor wafer having doped regions within said encapsulation;

(d) a network of conductors bonded to said wafer within said encapsulation;

(f) said signal leads being connected to said externally accessible terminals;

(g) said power leads being connected to said terminals of said battery.

38. The microelectronic central processing unit of claim 3 wherein said battery comprises:

39. A self powered microelectronic output/input unit comprising:

(a) an insulating encapsulation presenting externally accessible terminals;

(b) a semiconductor wafer hav,ing doped regions within said encapsulation;

(d) a network of conductors bonded to said wafer within said encapsulation;

(f) said signal leads being connected to said PAGE NOT TRANSMITTED TO- THE INTERNATIONAL BUREAU AT THE TIME OF PUBLICATION

said encapsulation;

(d) a network of conductors bonded to said wafer within said encapsulation;

(f) said signal leads being connected to said externally accessible terminals;

(g) said power leads being connected to said terminals of said battery;

(h) said transistorized circuitry including a read only memory for storing the instructions of permanent executable programs, a random access memory for storing programs of instructions, operand data and result data, and a central processing unit for executing instructions received from said read only memory and said random access memory;

(i) said battery comprising a semiconductor junction, a nuclear source, and a thermal impedance enclosure;

(j) said semiconductor junction incorporating an inor¬ ganic crystalline compound of Group III and Group V elements of the Periodic Table characterized by a predetermined annealing temperature for defects therein ;

(k) said nuclear source being of relatively high energy radiation and concomitant heat, said radiation causing generation of said defects in said semicon¬ ductor junction; and

(1) said thermal impedance enclosure being for said nuclear source and said semiconductor-junction for retaining therewithin a sufficient quantity of the heat generated by said nuclear source to maintain a functional relationship between said generation of defects and said predetermined annealing temperature during operation.

42. The microprocessor of claim 37, wherein said nuclear source is a beta emitter.

43. The microprocessor of claim 37 wherein said nuclear source is an alpha emitter.

44. The microprocessor of claim 37 wherein said Group III elements are selected from the class consisting of boron, aluminium, gallium and indium.

45. The microprocessor of claim 37 wherein said Group V elements are selected from the class consisting of phosphorous, arsenic and antimony.

46. The microprocessor of claim 37 wherein the normal operating temperature within said thermal impedance enclosure is at least as great as 50°C. 47. The microprocessor of claim 37 wherein said semiconductor-junction is a stratum, one surface of which is characterized by a p-dopant and the other surface of which is characterized by an n-dopant.

48. The microprocessor of claim 37 wherein said p-dopant is selected from the class consisting of zinc and cadmium, and said n-dopant is selected from the class consisting of silicon and sulfur.

49. The microprocessor of claim 37 wherein said nuclear source is a radionuclide selected from the class consisting of , and emitters.

50. The microprocessor of claim 37 wherein said semicon¬ ductor junction contains indium phosphide.