WO1993012582A1

WO1993012582A1 - Programmable logic device cell and method

Info

Publication number: WO1993012582A1
Application number: PCT/US1992/010010
Authority: WO
Inventors: Pei-Lin Pai; Fu-Chieh Hsu
Original assignee: Knights Technology, Inc.
Priority date: 1991-12-13
Filing date: 1992-11-19
Publication date: 1993-06-24

Abstract

A programmable gate array device comprises a substrate having a plurality of cells (50 and 51), each of the cells including at least one semiconductor device (e.g., a transistor) (M1-M4); a first plurality of links or interconnect segments for connecting together selected ones of the semiconductor devices (C, D, E, F, G, H); a second plurality of links or interconnect segments (53, U, V, W, X, Y, Z) and a plurality of connection points, for connecting together selected ones of the first plurality of links to selected ones of the second plurality of links (L1-L26).

Description

PROGRAMMABLE LOGIC DEVICE CELL AND METHOD

BACKGROUND OF THE INVENTION The present invention relates generally to the field of semiconductors and, more specifically, to programmable logic cells and interconnect structures used programmable read-only memories (PROM's), programmable log devices (PLD's), and application-specific integrated circuits (ASIC's) . An integrated circuit (IC) is a complete electronic circuit, containing transistors and perhaps diodes, resistors, and capacitors, along with their interconnecting electrical connectors contained in a highl compact form on a silicon wafer. Instead of building an electronic circuit out of discrete components, however, an entire circuit may be fabricated on the same piece of silicon in the form of a number of superimposed layers of conducting, insulating, and transistor forming materials. In this manner, a circuit having a required function may b fabricated by arranging predetermined geometric shapes in each of these layers.

Unfortunately, the process by which an integrate circuit is fabricated is long and complex, requiring sophisticated machinery and custom masks which must be specially setup for each specific type of custom integrate circuit to be fabricated. Thus, the process is only economical if very large quantities of integrated circuits are produced for a given setup. However, there exists applications where the quantities desired of a specific circuit are not large.

One approach to this problem has been the development of integrated circuits known as "gate arrays." In a typical gate array, a large number of transistors and other components are produced by the aforementioned IC mas production process. In addition, specific interconnection between the components are formed on the chip, thus making it suitable for a specific circuit.

A particular advantage of this device is the reduced number of customization mask layers that are required, thus reducing prototype cost and turnaround time. Representative of this type of device are application- specific integrated circuits (ASIC's) — primarily programmable gate arrays (PGA) and standard cells (SC) — which have found wide application in a variety of circuits. To further reduce cost and turn-around time, many different types of quick-turnaround application-specific integrated circuits and programmable logic devices (PLD's) have emerged. These typically employ different customization techniques, including laser exposure, laser deposition, laser cutting, electron-beam exposure, focused- ion beam deposition/etching, and electrical programming. At the expense of much lower performance, the electrically programmable devices offer the fastest turnaround time. Employing EPROM, EEPROM, pass-transistor, and antifuse technologies, these devices usually incur much higher per unit production costs and have a higher incidence of non-compatible logic cells. Common examples of electrically programmable devices include programmable array logic (PAL), electrically programmable logic device (PLD's), and field-programmable gate arrays (FPGA's) . For a general introduction, see Iscoff, R. , Characterizing ASIC' s: It ' s Done With Mirrors, Semiconductor International, August 1990, 68-73.

In comparison, physically programmable devices (e.g., those programmed by laser beam, electron beam, focused-ion beam, and the like) provide shorter turnaround time and higher performance, but incur increased expense during setup and processing. Furthermore, these devices have limited compatibility, reduced gate count, and lower utilization rate (e.g., by laser cutting).

Several programmable gate array devices have been described. U.S. Patent No. 4,924,287, issued to Orbach, describes a programmable gate array device having laser programmable gate array logic cells, where the programmable element is a conventional fuselink. In the circuit, the resultant logic function is limited, and the interconnect capacity is dramatically reduced (when compared to standard mask-programmable gate array devices) . In particular, each interconnect track in Orbach's design occupies two metal line/space pitches in both horizontal and vertical directions, thereby reducing the interconnect capacity by a factor of four.

U.S. Patent No. 4,937,475, issued to Rhodes, describes a programmable gate array device having both lase breakable conductors and laser activated lateral diffused links. Although more flexible in implementing interconnect patterns than the device of Orbach, this device is not compatible with standard mask-programmable gate arrays because the architecture of the laser activated lateral diffused links still occupies two metal line/space pitches per interconnect in each of the X and Y directions. The resultant logic modules, therefore, uses ten (10) pairs of transistors to implement simple two-input functions, as compared to typically two (2) pairs of transistors in standard gate arrays.

SUMMARY OF THE INVENTION

A programmable gate array of the present inventio device comprises a substrate having a plurality of cells, each of the cells including at least one semiconductor device (typically transistors) ; a first plurality of links or interconnect segments for connecting together selected ones of the semiconductor devices; a second plurality of links or interconnect segments; and a plurality of connection points, for connecting together selected ones of the first plurality of links to selected ones of the secon plurality of links.

In a method for fabricating a programmable gate array device having connection points, a substrate is provided. Next, a first interconnect layer is deposited and etched, according to a pattern, on the substrate. This is followed by the deposition of a dielectic layer. A second interconnect layer is then deposited. Interlayer connection points are formed by removing selected portions of the second interconnect layer and the dielectric. After depositing a plug metal layer, the process is completed by etching the second interconnect layer and the plug metal layer according to a pattern.

BRIEF DESCRIPTION OF DRAWINGS Fig. LA is a layout diagram showing the typical interconnection layout employed in prior art programmable gate arrays. Fig. IB is a layout diagram showing a prior art programmable gate array employing lateral diffused laser links.

Fig. 2 is a layout diagram showing an interlayer connection point of the present invention. Fig. 3 is a diagram illustrating how the logic cells of the present invention are laid out in rows.

Fig. 4 is a schematic diagram of a programmable gate array logic cell of the present invention which employs two pairs of transistors per cell, and interlayer connection points.

Fig. 5 is a schematic diagram illustrating a first alternative embodiment of the present invention, where the cell of Fig. 4 has a reduced number of input/output pins. Fig. 6 is a schematic diagram illustrating a second alternative embodiment of the present invention, where the embodiment of Fig. 5 has a different input/output pin arrangement.

Fig. 7 is schematic diagram illustrating a third alternative embodiment of the present invention, where the embodiment of Fig. 6 utilizes shared vertical tracks between two cells.

Fig. 8 is a schematic diagram of a fourth alternative embodiment of the present invention, where the embodiment of Fig. 4 employs both interlayer and intralaye connection points.

Fig. 9 is a schematic diagram of a fifth alternative embodiment of the present invention, where the embodiment of Fig. 8 employs intralayer connection points both interconnect layers.

Fig. 10 is a schematic diagram illustrating an exemplary application of the programmable logic cell embodiment of Fig. 8, where the left cell implements a

MULTIPLEXER gate and the right cell implements a NAND gate Fig. 11 is a schematic diagram of an alternative embodiment of the present invention, where a programmable gate array logic cell employs one pair of transistors per cell and interlayer connection points in a continuous gate arrangement.

Fig. 12 is schematic diagram illustrating a firs alternative to the embodiment of Fig. 11,.where the programmable logic cell employs more fully populated interlayer connection points.

Fig. 13 is a schematic diagram illustrating a second alternative to the embodiment of Fig. 11, where the cell employs both interlayer and intralayer connection points. Fig. 14 is a schematic diagram illustrating an exemplary application of the programmable logic cell embodiment of Fig. 12, where the embodiment implements a MULTIPLEXER gate.

Fig. 15 is a schematic diagram, illustrating another exemplary application of the programmable logic ce embodiment of Fig. 12, where the embodiment implements a NAND gate.

Figs. 16A-C are cross-sectional diagrams illustrating a processing method of the present invention for forming the interlayer and intralayer connection point which may be programmed through masking.

Figs. 17A-C are cross-sectional diagrams of a processing method of the present invention for forming the interlayer and intralayer connection points which may be programmed through energy means.

Figs. 18A-C are cross-sectional diagrams of an alternative processing method of the present invention for forming the interlayer and intralayer connection points which may be programmed through energy means.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In rodue ion

Referring now to Fig. 1A, the typical interconnection layout employed in prior art programmable gate arrays is illustrated. Programmable gate array cell 2000 includes five vertical wiring tracks and two horizontal wiring tracks. Connection between the tracks is established by an interconnect layout having conventional fuses (cutting), for example, as taught by U.S. Patent No. 4,924,287; see also. High Density Laser Programmable Gate Array Family, IEEE 1987 Custom Integrated Conference, pages 526-528.

To implement a linkage between cross-over wires (e.g., interconnect link 2002a and interconnect link 2003a), a cross-over cut-site (e.g. site 2004) is provided in a pre- laid-out fashion. As seen in the implementation of Fig. LA, however, each cut-site requires two horizontal wiring pitches (e.g., horizontal interconnects 2002a, 2002b) and two vertical wiring pitches (e.g. , vertical interconnects 2003a, 2003b) . Furthermore, each horizontal track only has linkage points to every other vertical track. Referring now to Fig. IB, an alternative prior art interconnection layout is illustrated. PGA cell 2050 employs lateral diffused laser links, for example, as taught by U.S. Patent No. 4,937,475. For each cross-over link point implemented, two horizontal wiring pitches and three or more vertical wiring pitches are required. Thus, the two horizontal wiring tracks 2006a, 2006b and three vertical wiring tracks 2007a, 2007b, 2007c occupy about the same area as that of cell 1 (when using the same minimum layout rules). Moreover, the diffused link sites (e.g., site 2008) typically require even more surface area than allowed by minimum layout rules. Referring now to Fig. 2, an interconnect layout

2100 of the present invention is illustrated. Layout 2100 includes two horizontal tracks 2120a, 2120b and three vertical tracks 2100a, 2110b, 2110c. Connection between tw wiring tracks is achieved by an interlayer connection point 2130 of the present invention. As shown, only one horizontal wiring pitch (e.g. , track 2120b) and one vertica wiring pitch (e.g., track 2120c) is needed for each cross¬ over link point (e.g. , at point 2130) . Therefore, the two horizontal wiring tracks and three vertical wiring tracks occupy a much smaller area than that of prior art implementations. As a result, the compact layout of the present invention allows a programmable logic cell to be laid out directly on top of standard gate array transistors, thus achieving direct gate-to-gate and transistor-to- transistor compatibility with standard gate arrays.

Referring now to Fig. 3, a programmable gate arra device 2200 of the present invention is shown. Device 2200 includes a plurality of logic cells laid out in rows, with wiring channels disposed in between rows of logic cells. I this fashion, the device 2200 achieves maximum compatibilit with standard gate array layout. Both interlayer connectio points and intralayer connection points (not shown) are provided in the logic cells and in both the vertical and horizontal wiring tracks.

interlayer connect^*--JOT^{* *■*•**}* dintents

Referring now to Fig. 4, a programmable gate arra (PGA) 1 constructed in accordance with the principles of th present invention comprises a plurality of logic cell pairs, such as cells 10, 11, arranged in a standard gate array fashion. Each cell includes a desired configuration of semiconductor elements, which may be selectively connected to one another. The specific construction of PGA l will be described with reference to the left cell 10. Since the right cell 11 is substantially (although not identically) the mirror image of the left cell 10, its construction and operation may be ascertained from the following description as well.

Logic cell 10 of the present invention includes a four-transistor-per-logic-cell configuration, as shown by a first pair M1/M3 and a second pair M2/M4 of transistors, which is directly gate-to-gate and transistor-to-transistor compatible with a standard mask programmable gate array (MPGA) having four-transistor logic cells. Logic cell 10 also includes two power lines V_cc and V^, two inputs A and B, and up to six outputs C, D, E, F, G, and H. Connection between the various elements (e.g., transistors) of the cell 10 is provided by conductive lines or segments arranged in separate layers. As shown, cell 10 includes a first interconnect layer having a first set of conductive segments or links (e.g., line 16 shown as a solid line) and a second interconnect layer having a second set of conductive segments or links (e.g., line 14 shown as a hatched line) . While the first interconnect segments are illustrated as thin (metal) lines and the second interconnect segments are illustrated as wide (metal) lines, those skilled in the art will appreciate that the two interconnects will typically be of the same width, or of any desired width relative to one another.

Connection between the layers (more particularly, between conductive links or segments in separate layers) is provided by a plurality of pre-laid-out connection points.

For example, interlayer connection points L1-L18 selectively connect lines in one layer with those of another. As illustrated, all interlayer connection points in a logic cell are laid-out in an "in-line" fashion in both horizontal and vertical directions, thus conforming to a standard gate array routing grid. In this manner, the cell occupies minimum area (i.e., the minimum distance between the center of any two interlayer connection points is a single metal line/space pitch) .

By "sharing" selected segments between cells, th

* density of logic cells in PGA 1 may be increased even

5 further. For example, vertical interconnect segment 12,

• which lies on the substrate/well pickup area (normally lai out in standard MPGA) , is shared between two neighboring cells. To preserve the in-line nature of the interlayer connection points in the shared segment 12, the left and

10 right cells 10, 11 will typically not be true mirror image of one another. Nevertheless, the two cells are functionally equivalent.

Referring now to Fig. 5, a first alternative embodiment of the present invention is shown. Programmabl

15 gate array 2 comprises a plurality of logic cell pairs (e.g., cells 20, 21) arranged in a standard gate array fashion. Except for a difference in pin configuration, PG 2 is identical to PGA 1. This difference will now be described.

20 With the aid of interlayer connection points L21

L30, cell 20 achieves a reduced number of I/O pins by combining inputs and outputs. As illustrated in Fig. 5, t two inputs A, B and the six outputs C, D, E, F, G, H are selectively connected to six input/output pins U, V, W, X,

25 Y, and Z. Since the two inputs A, B can be accessed from either the top pins U, V or the bottom pins X, Y of the logic cell 20, additional routing flexibility is afforded. Nevertheless, the in-line nature (i.e., conformance to a standard routing grid) is still preserved.

30 In addition to reducing the required number of I pins, the configuration of PGA 2 includes modification to s the vertical track shared between cells. As shown, shared vertical track 22 includes two additional segments S and T thereby providing additional pins.

35 Those skilled in the art will appreciate that other permutations of the basic configuration of PGA 2 are possible within the scope of the present invention. For example, the two inputs A, B may be connected to the input/output pins V, W (respectively) as shown at the top of cell 30 in Fig. 6. Moreover, the free pins of the shared vertical track S, T may serve as additional input/output pins for the logic cells, such as shown by I/O pins 43, 44 of Fig. 7.

Intralayer and Interlayer Connection Embodiments

By employing both interlayer connection points and intralayer connection points within a programmable gate array logic cell, additional functionality and advantages may be achieved. Referring now to Fig. 8, a programmable gate array employing both interlayer and intralayer connection points in accordance with the principles of the present invention will be described.

PGA 5 comprises a plurality of logic cell pairs (e.g., cells 50, 51) arranged in a standard gate array fashion. Again, the basic cell — logic cell 50 — is a four-transistor logic cell having the previously described interlayer connection points L1-L18 (of Figs. 4-7) . In addition, cell 50 includes intralayer connection points Nl- N12 and input/output pin interlayer connection points L21- L26.

In an exemplary configuration of PGA 5, the power lines V_cc and V^ are implemented using the first interconnect layer, and the input/output pins are implemented using a continuous second interconnect layer, with pre-laid-out intralayer connection points. Again, those skilled in the art will appreciate that the arrangement of. the inputs A, B through the interlayer connection points L21-L26 may have a variety of possible configurations, in addition to those shown.

A particular advantage of this embodiment is increased flexibility of the routing tracks. In particular, any vertical track (e.g., vertical track 53) not used to configure the underlying logic cell can be used as a free vertical feedthrough track. In addition to enhanced flexibility, this design permits increased utilization of the routing tracks in the interconnect area.

Those skilled in the art will appreciate that other permutations of the basic configuration of PGA 5 are possible within the scope of the present invention. As shown in Fig. 9, for example, the power line connections ma be altered. Instead of the previously employed interlayer connection points L1-L6, the power line connections V_cc and V_ss may be made through intralayer connection points N21-N26 Additional intralayer connection points (e.g., connection points N21-N28) may be added to each cell, thus permitting extra circuit configurations. For example, intralayer connection points N27, N28 may be employed to electrically separate the gates of the N and P-channel transistor pair.

Referring now to Fig. 10, an exemplary applicatio of the programmable gate array 5 is illustrated by the PGA 7. Circuit 7 includes logic cells 70, 71 which implement a MULTIPLEXER 70 and a NAND gate 71, respectively. For purposes of illustration, an interlayer connection point that has been short-circuited is represented by a hatched circle, and an intralayer connection point that has been open-circuited is represented by an open square.

As illustrated, the cell 70 implements a MULTIPLEXER gate with two CLK inputs CLKl, CLK2, two signal inputs INI, IN2, and one signal OUTPUT. In this manner, th MULTIPLEXER of cell 70 employs three vertical tracks 73, 74 75 (including the shared track) . Vertical track 71 is free however, and may be employed as a vertical feedthrough track. Cell 71, on the other hand, implements a NAND gate having two inputs INI, IN2 and one OUTPUT. As shown, two vertical tracks 76, 77 are employed, while a third vertical track 78 of the cell remains free.

As the logic cell of the present invention is highly flexible, the foregoing MULTIPLEXER/NAND gate implementation is but one of many possible configurations. Those skilled in the art will appreciate other possible configurations, employing different combinations and numbers of tracks and/or input/output signals, which achieve the same or similar functionality.

Sinσle-Transistor-Pair Logic Cell Embodiments

Referring now to Fig. 11, a programmable gate array of the present invention employing a different logic cell is shown. Programmable gate array 8 comprises a plurality of logic cell pairs, such as cells 80, 81, where a single pair of transistors (e.g., transistors Ml, M2) is employed per logic cell. As before, the basic logic cells of PGA 8 are arranged side-by-side in a continuous gate fashion.

Logic cell 81 includes a transistor pair Ml, M2, a plurality of interlayer connection points L1-L18, two power lines _cc, ^v _ss- ^{anci two} vertical tracks with pins W, X, Y, Z. As shown, each logic cell (e.g., cell 80) includes a conductor (e.g., conductor 85) that connects each drain node (e.g. , node 86) to three neighboring drain nodes (e.g., nodes 87, 88, 89). This "three-neighbor" connection exists for both N- and P-channel transistors.

To achieve isolation between logic gates, "boundary cells" are employed around the cells of interest. Boundary cells (e.g., cells 123, 124 of Fig. 15) are cells which have their N- and P-channel gates connected to V-^ and V_cc, respectively. This configuration isolates the cells (e.g., cells 120, 121 of Fig. 15) which are located between adjacent boundary cells.

As shown in Fig. 11, the connections of PGA 8 may be traced as follows. Connection L6 is attached to the drain node 85 of transistor Ml; connection L5 is attached to the drain node to the immediate right (i.e., node 87); connection L7 is attached to the drain node to the left (i.e., node 90); and connection L8 is attached to the drain node to the second left (not shown) . Those skilled in the art will appreciate that the three-neighbor configuration of the present invention may be implemented in a variety of configurations including: 1) 2 left and 1 right (as shown in Fig. 11); 2) l left and 2 right; 3) 3 left and 0 right; and 4) 0 left and 3 right.

To minimize unused regions, "local tracks" (e.g., tracks 91, 92 of Fig. 11) may be employed. Local tracks ar optional horizontal tracks having interlayer connection points (e.g., points L19, L20) . As such, the tracks may be located on either or both sides of the lateral connection points (e.g., points L15-L18) , and serve as additional feedthrough tracks. Vertical tracks, if not used to configure the underlying logic cell, may also serve as additional (vertical) feedthrough tracks.

As shown in Fig. 12, the embodiment of Fig. li ma be altered to include additional interlayer connection points. In particular, each drain node connector (e.g., L5 is now connected to a plurality of gate nodes, in addition to its previous connection to a plurality of drain nodes.

Referring now to Fig. 13, another alternative to the embodiment of Fig. 11 is shown. Programmable gate arra 10 is identical to gate array 8, with the added feature of both interlayer and intralayer connection points. For example, connection points N3, N4 replace the lateral connection points L15-L18 (of Fig. 11) , thus providing additional routing flexibility. Referring now to Fig. 14, an exemplary applicatio of the PGA 9 (of Fig. 12) is shown. Gate array circuit 11 implements a MULTIPLEXER gate function as follows. Two cells 110, 111 implement the necessary logic function, whil two cells 112, 113 are employed to isolate cells 110, 111. In this example, no free vertical tracks are available.

The PGA 9 illustrates but one of many possible implementations of a MULTIPLEXER gate using the principles of the present invention. For example, all the functions o a three-neighbor arrangement may instead be implemented wit a greater than three-neighbor extension of the drain node. Also, if the MULTIPLEXER gate function is not needed (or necessary to be efficient) , a simpler two-neighbor arrangement may be employed to implement most of the other gate functions. In this case, connections L15-L18 (from Fig. 11) are employed to establish the lateral connections between W, Y and X, Z. Only a selected one of L15, L16 and a selected one of L17, L18 need be employed. Due to its efficiency, the three-neighbor configuration of the present invention is particularly advantageous for implementing efficient MULTIPLEXER gate functions.

Referring now to Fig. 15, an exemplary implementation of a NAND gate using the programmable gate array 9 of the present invention will be described. PGA 12 comprises logic cells 120, 121, which implement the necessary logic function, and boundary cells 123, 124, which serve as isolation. In this manner, three vertical tracks are employed, and two vertical tracks remain free. Again, those skilled in the art will appreciate that in the logic cell of the present invention each logic gate function can be implemented in a variety of ways.

Processing Method

Referring now to Figs. 16-18, methods of constructing programmable gate arrays in accordance with the present invention will be described. For purposes of illustration, the following description will focus on particular methods of construction and certain alternatives. The methods of the present invention are not limited to these specific examples, however, but instead may be advantageously implemented with numerous variations. For example, the interlayer connection points and intralayer connection points of the present invention may be constructed using different processing methods, including antifuse, fuse, via-hole, and the like. In addition, the devices of the present invention may be programmed using a variety of techniques, including conventional masking, laser direct write masking, laser direct deposition, laser induced reaction, laser connection, electron-beam direct write masking, and the like. Referring now to Figs. 16A-C, a method for formin pre-laid-out interlayer and (optional) intralayer connectio points will be described. The latter will be programmable using masking techniques, including conventional or a laser direct write masking, or electron-beam direct write masking

As shown in Fig. 16A, a first interconnect layer 1301 is first patterned, then a dielectric layer 1302 is formed. This may be accompanied by optional planarization steps, if necessary. After formation of the dielectric layer, the second interconnect layer 1303 is deposited.

Interlayer connection point sites (e.g., sites 1304, 1305) are formed by removing both the second interconnect layer and the dielectric by via-hole masking techniques. This step is followed by the deposition of a plug metal layer 1306, which preferably includes a refractory metal such as Ti, W, or TiW alloy. Next, the combined plug metal layer and second interconnect layer is then patterned and etched.

Referring now to Fig. 16B, the optional step of forming intralayer connection points is shown. In this variation, a masking step is included so that the plug met is removed at the pre-laid-out intralayer connection point sites, such as sites 1311, 1312.

Referring now to Fig. 16C, a method for programming a gate array in accordance with the present invention is shown. A layer of photoresist 1321 (or other masking material) is coated and patterned by masking technique. In this manner, protective spots are formed on the intralayer connection points and (optional) interlayer connection points to be connected. Next, a two-step etchi is performed. First, the second interlayer (e.g., layer 1303 from Fig. 16A) is (optionally) removed; the plug meta layer (e.g., layer 1306 from Fig. 16A) is left intact, however. This step forms an open intralayer connection point. Next, the plug metal layer is removed while leavin the second interconnect layer. This step forms an open interlayer connection point. The second interconnect laye may be protected by an optional layer of dielectric (not shown) which is deposited on top of the second interconnect layer before formation of the via-holes. Construction of both the first and second interconnect layers may be accomplished using a variety of metals, including conventional aluminum alloys, refractory metal, refractory metal silicide, refractory metal nitride, and/or a multiple layer combination thereof.

Referring now to Figs. 17A-C, an alternative method of construction in accordance with the present invention is illustrated. The processes of Figs. 17A-C are similar to those of 13A-C, with the following exception. The steps of forming pre-laid-out interlayer and (optional) intralayer connection points are programmed using energy imparting techniques. Suitable energy means include laser- induced chemical reaction, laser-induced chemical deposition, laser-induced vaporization or cutting, focused ion beam-induced chemical reaction, focused ion beam deposition, focused .ion beam cutting, and the like. In this manner, no masking step is required for programming the connection points.

As shown in Fig. 17A, a first interconnection layer is patterned (shown with optional barrier metal layer 1402) , then a dielectric layer 1403 is formed; planarization steps may be added at this point, if desired. Next, a second interconnect layer 1404 is deposited. Using via-hole masking technique, interlayer connection points (e.g., points 1405, 1406 are formed; the second -interconnect layer 1404 and the dielectric layer 1403 are also* removed. This is followed by deposition of an antifuse layer. The antifuse lay may be formed from a variety of materials including amorphous silicon, oxide, silicon-rich oxide, and the like. A plug metal layer, preferably constructed of a refractory metal, refractory metal alloy, or the like, is then formed. Finally, the combined plug metal layer 1407, antifuse layer 1408, and second interconnect layer 1404 is then patterned and etched. Referring now to Fig. 17B, an optional method for forming the intralayer connection points is illustrated. I this alternative method, a masking step is used to remove the plug metal layer and (optionally) the antifuse layer everywhere except at the interlayer and intralayer connection point sites.

Referring now to Fig. 17C, the programming steps are shown. Employing energy techniques, a shorted interlayer connection point is created through energy induced reactions between the plug metal, the barrier metal and the antifuse layer. Additional energy applying techniques, including energy induced cutting/removing processes, may be used to create opened intralayer connection points. Depending on the process employed, certain layers may be omitted. For example, the plug metal layer may be omitted when the interlayer connection point is to be shorted using energy-induced chemical conversion process, i.e., where the antifuse layer is chemically converted into conducting material locally when energy is applied.

Additionally, both the plug metal layer and the antifuse layer may be omitted when energy-induced direct deposition processes are used to program the interlayer connection points. In this case, only opened via-holes are needed to allow energy-induced direct deposition to connect the first and second interconnect layers inside the via-holes. Furthermore, an optional layer of dielectric may be deposited on top of the second interconnect layer (e.g., layer 1407) before forming the via-holes, thus providing an etch stop for the second interconnect layer. As before, th first and second interconnect layers in Figs. 17A-C may be constructed using conventional aluminum alloys, refractory metal, refractory metal silicide, refractory metal nitride, and/or a multi-layer combination thereof. Referring now to Figs. 18A-C, yet another variation of the process of Figs. 17A-C are shown. In particular, the technique provides self-aligned features by confining the energy-induced reactions/conversions to specific locations. As shown in Fig. 18A, after the first interconnect layer 1501 (shown with optional barrier metal layer 1502) is patterned, a dielectric layer 1503 is formed (with optional planarization steps, if necessary) . This is followed by a via-hole forming step and then the deposition of an antifuse layer 1504 and a barrier metal layer 1505. As before, the antifuse layer 1504 may be formed from a variety of materials (as set forth hereinabove) . Similarly, the barrier metal layers 1502, 1505 may be formed from any of the previously described alloys. Finally, the combined antifuse layer 1504, barrier metal layer 1505, and second interconnect layer 1506 is then patterned and etched.

Referring now to Fig. 18B, an optional method for forming the intralayer connection points is illustrated. As shown, a masking step is used to remove the second interconnect layer 1515, at the interlayer and intralayer connection point sites 1501, 1502.

Referring now to Fig. 18C, the process of programming is illustrated. Using an energy technique, a shorted interlayer connection point 1521 is created through energy-induced reactions between the barrier metal 1525 and the antifuse layer 1524. An alternative energy technique may be employed to create an opened intralayer connection point, for example, employing energy-induced cutting/removal processes.

The process has particularly advantageous features. By selecting the appropriate material combinations with different absorption characteristics (to the energy means used) , for example, selective energy absorption will occur only at the desired locations. This produces a much improved controlled reaction-conversion and requires less stringent alignment accuracies for positioning the energy source. In Fig. 18C, for example, the top surface of the second interlayer 1526 may be less absorbing (or even reflecting) while the barrier metal layer 1505 is more absorptive of the energy source. Thus employing this technique of the present invention, the process may be adapted to accommodate different energy programming sources or means.

Again, depending on the process employed, certain layers may be omitted. If the interlayer connection point is to be shorted using energy-induced chemical conversion process, for example, then the top barrier metal layer may be omitted. Furthermore, an optional layer of dielectric (not shown) may be deposited on top of the second interconnect layer (e.g., layer 1526 of Fig. 18C) before programming, thus providing protection for the second interconnect layer.

While the invention is described in some detail with specific reference to a preferred embodiment and certain alternatives, there is no intent to limit the invention to that particular embodiment or those specific alternatives. The true scope of the invention is defined not by the foregoing description but by the following claims.

Claims

WHAT IS CLAIMED IS:

1. A programmable gate array device comprising: a substrate having a plurality of cells, each of said cells including at least one semiconductor device; a first plurality of links for connecting togethe selected ones of the semiconductor devices; a second plurality of links; and a plurality of connection points, for connecting together selected ones of the first plurality of links to selected ones of the second plurality of links.

2. The device of claim 1, wherein at least one of said second plurality of links is shared between at least two cells.

3. The device of claim 1, wherein each of said cells includes a first pair of n-channel and p-channel transistors and a second pair of n-channel and p-channel transistors.

4. The device of claim 3, wherein transistors within a pair are connected in a gate-to-gate fashion.

5. The device of claim 1, wherein each of said cells includes a pair of n-channel and p-channel transistors, and wherein each of said transistors includes a drain node selectively connectable to at.least one drain node of another cell.

6. The device of claim 1, wherein said first plurality of links is disposed within a first layer of the substrate, and wherein said second plurality of links in disposed within a second layer of the substrate.

7. The device of claim 1, wherein selected ones of said second plurality of links include at least one intralayer connection point for interrupting conduction within a link.

8. A method for fabricating a programmable gate array device having connection points, the method comprising:

(a) providing a substrate;

(b) depositing and etching, according to a pattern, a first interconnect layer on the substrate; (c) depositing a dielectic layer;

(d) depositing a second interconnect layer;

(e) forming interlayer connection points by removing selected portions of the second interconnect layer and the dielectric; (f) depositing a plug metal layer; and

(g) etching the second interconnect layer and the plug metal layer according to a pattern.

9. The method of claim 8, wherein step (f) includes depositing an antifuse layer and a plug metal layer.

10. The method of claim 8, further comprising: forming intralayer connection points by masking selected sites.

11. The method of claim 9, further comprising: (h) forming intralayer connection points by masking selected sites.

12. A method for fabricating a programmable gate array device having connection points, the method comprising:

(a) providing a substrate; (b) depositing, according to a pattern, a first interconnect layer on the substrate;

(c) depositing a dielectric layer; (e) forming via hole; and

(f) depositing, according to a pattern, an antifuse layer and a second interconnect layer.

13. The method of claim 12, further comprising: selectively removing portions of the second interconnect layer to create regions which are more energy absorbing.

14. In a programmable gate array device, the improvement comprising: a plurality of horizontal tracks in a first interconnect layer; a plurality of vertical tracks in a second interconnect layer, whereby a cross-over point occurs wherever a horizontal track lies over a vertical track; and a plurality of interlayer connection points, whereby each interlayer connection point is selectively located at one cross-over point.

15. The device of claim 14, further comprising: a plurality of intralayer connection points located in selected ones of the horizontal tracks and the vertical tracks.

16. The device of claim 14, wherein the programmable gate array device is directly gate-to-gate and transistor-to-transistor compatible with standard gate array devices.