WO1992006433A1 - Universal processor interface component - Google Patents

Universal processor interface component Download PDF

Info

Publication number
WO1992006433A1
WO1992006433A1 PCT/US1991/006968 US9106968W WO9206433A1 WO 1992006433 A1 WO1992006433 A1 WO 1992006433A1 US 9106968 W US9106968 W US 9106968W WO 9206433 A1 WO9206433 A1 WO 9206433A1
Authority
WO
WIPO (PCT)
Prior art keywords
control
buses
generic
bus
data
Prior art date
Application number
PCT/US1991/006968
Other languages
French (fr)
Inventor
Grenville Hughes
Massoud Taraghi
Original Assignee
Allied-Signal Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Allied-Signal Inc. filed Critical Allied-Signal Inc.
Publication of WO1992006433A1 publication Critical patent/WO1992006433A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Definitions

  • the present invention relates to interface circuits. More specifically, it relates to microprocessor interfaces.
  • microprocessors When designing microprocessor-based electronic systems, there are a variety of microprocessors available. By way of example only, there are the Motorola 68000 family, Intel 8086 family and MIL-STD-1750 family of microprocessors. The choice of a microprocessor in a particular situation is dependent upon factors such as architecture, system requirements, processing speeds for particular algorithms, bus interfaces, characteristics of instruction sets and available development systems.
  • peripheral components must be interfaced with he microprocessor. Therefore a microprocessor interface must be designed in accordance with the selected microprocessor. This task, however, involves significant effort and cost. Needed is an interface component which provides peripheral functions independent of the selected microprocessor.
  • the present invention is a component for selectably providing an interface to one of a plurality of microprocessors.
  • the component includes a bus interface and one or more peripherals.
  • the bus interface converts information on address, data and control buses from one of the microprocessors to information on a generic address bus, a generic data bus and a generic control bus.
  • the peripherals are connected to the generic buses.
  • FIG. 1 is a block diagram of an interface component in accordance with a preferred embodiment of the present invention.
  • FIG. 2 is a block diagram of the bus interface illustrated in FIG. 1.
  • FIG. 1 illustrates an interface component 10.
  • a microprocessor 12 is connected to a bus interface 14 through an address bus 16, a data bus 17 and a control bus 18.
  • the buses 16 to 18 carry information in accordance with the protocol of the particular microprocessor 12. By way of example only, the information can be organized in accordance with a 68000 protocol, an 80386 protocol or the protocol of any other microprocessor.
  • the bus interface 14 converts the information on the buses 16 to 18 to information on generic buses 19 to 21.
  • Generic bus 19 is a control bus that provides control signals that coordinate the use of the generic buses 19 to 21.
  • Generic bus 20 is an address bus and generic bus 21 is a data bus.
  • a microprocessor clock signal is provided to the bus interface 14 on a line 22 so as to allow the bus interface 14 to synchronize the information on the generic buses 19 to 21 to the information on the microprocessor buses 16 to 18.
  • Peripheral 24 is a Programmable Memory Decoder which defines the microprocessor address space occupied by various memory devices, such as random access memory (RAM) and read only memory (ROM) or by I/O devices.
  • RAM random access memory
  • ROM read only memory
  • I/O devices I/O devices.
  • the Programmable Memory Decoder 24 monitors the address bus 20 and the control bus 19 and generates the chip selects for the various memory devices at the appropriate times. Such a device is well known to one skilled in the art of microprocessor design.
  • Peripheral 25 is a Programmable Wait State
  • the Wait State Generator 25 which monitors the generic address bus 20 to determine which device is being addressed by the microprocessor 12. The speed of the device being addressed is stored in the Wait State Generator 25 so that a READY signal can be generated to the microprocessor 12. The READY signal specifies when information is ready for transfer. The Wait State Generator 25, therefore, allows slower devices to communicate with the microprocessor 12. Such a device is well known to one skilled in the art.
  • Peripheral 26 is a Universal Asynchronous Receiver Transmitter (UART) which provides a serial communication channel for the microprocessor 12.
  • UART Universal Asynchronous Receiver Transmitter
  • a UART such as the 16550 available through National Semiconductor can be utilized if the bus interface 14 is a separate component. If, as in a preferred embodiment, the UART 26 is included on a single substrate with the bus interface 14, the UART 26 can be designed by one skilled in the art.
  • Peripheral 27 is a Direct Memory Access (DMA) Controller which controls data transfers between memory or peripheral devices independent of the microprocessor 12.
  • DMA Direct Memory Access
  • a device such as the 82258 available through Intel can be utilized if the bus interface 14 is a separate component. If, as in a preferred embodiment, the DMA Controller 27 is included on a single substrate with the ° bus interface 14, it can be designed by one skilled in the art.
  • Peripheral 30 is a Bus Arbitration and Control circuit and is related to the DMA Controller 27.
  • the DMA Controller 27 When the DMA Controller 27 is transferring data between 5 devices, it needs to control the generic buses 19 to 21 The microprocessor 12, therefore, loses control of the generic buses 19 to 21 during such a transfer.
  • the Bus Arbitration and Control circuit 30 is informed of a direct memory access on the line 32 and then controls the 0 generic buses 19 to 21 and locks out the microprocessor 12 at the appropriate times. Such a device is well known to one skilled in the art.
  • Peripheral 28 is a Programmable Interval Timer which solves the timing control problems common in
  • a device such as the 8254 available through Intel can be utilized if the bus interface 14 is a separate component. If, as in a preferred embodiment, the Programmable Interval Timer 28 is included on the same substrate as the bus interface
  • Peripheral 29 is a Priority Interrupt Controller (PIC) which provides a multi-level interrupt system for the microprocessor 12.
  • PIC Priority Interrupt Controller
  • a device such as the 8259 available through Intel can be utilized if the bus interface 14 is a separate component. If, as in the preferred embodiment, the PIC 29 is included on the same substrate as the bus interface 14, it can be designed by one skilled in the art.
  • peripherals can also be utilized in the component 10 if desired or needed. Any differences in speed between peripherals is accommodated by the Wait State Generator 25.
  • a preferred embodiment of the bus interface 14 includes a Select MUX 40, a Memory Read Sequencer 41, a Memory Write Sequencer 42, a System Data Enable and Direction Sequencer 43, an I/O Read Sequencer 44, an I/O Write Sequencer 45 and an I/O Data Enable and Direction Sequencer 46.
  • the address bus 17 and the data bus 18 from the microprocessor 12 are output from the bus interface 14 as the generic address bus 20 and the generic data bus 21, respectively. These buses 17, 18 are used by the various peripherals 24 to 30.
  • the Select MUX 40 receives three control buses 16A, 16B and 16C corresponding to the 68000 control bus, the 80386 control bus and the 1750 control bus, respectively. In alternate embodiments, however, other microprocessor control buses can be provided. Additionally, any number of microprocessor interfaces could be provided. Pins 48 and 50 are hardwired to select the proper control bus 16A, 16B or 16C in accordance with the selected microprocessor 12. The selected control signals are output from the Select MUX
  • the address bus 17 and the data bus 18 from the microprocessor 12 are also input to the devices 41 to 46.
  • the microprocessor clock signal is input to the devices 41 to 46 on the line 22 to allow synchronization of the control signals on the bus 19.
  • the signals outputted by the devices 41 to 46 form the generic control bus 19 which is used to control the various peripherals 24 to 30.
  • the Memory Write Sequencer 42 outputs a signal MEMWR at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock signal so as to control memory write cycles for the peripherals 24 to 30.
  • the System Data Enable and Direction Sequencer 43 outputs signals SYSDEN and SYSDTR at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock signal so as to control the enabling of data transfer and the direction of data transfer, respectively, for the peripherals 24 to 30.
  • the I/O Read Sequencer 44 outputs a signal IORD at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock so as to control I/O read cycles for the peripherals 24 to 30.
  • the I/O Write Sequencer 45 outputs a signal IOWR at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock signal so as to control I/O write cycles for the peripherals 24 to 30.
  • the I/O Data Enable and Direction Sequencer 46 outputs signals IODEN and IODTR at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock signal so as to control the enabling of data transfer and the direction of data transfer to I/O devices in the peripherals 24 to 30, respecti ely.
  • bus interface 14 can be implemented as a separate component which is interfaced to the various peripherals, it is preferred to implement the bus interface 14, the various peripherals 24 to 30 as well as any other desired peripherals on a single substrate, as illustrated in FIG. 1. Alternatively, any combination of the peripherals 24 to 30 or any other peripherals can be included with the bus interface 14. It is further preferred to provide the generic buses 19 to 21 at external pins of the single substrate, thereby allowing the use of additional peripherals not originally included on the single substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

A component (10) for selectably providing an interface to one (12) of a plurality of microprocessors includes a bus interface (14) and one or more peripheral components (24, 25, 26, 27, 28, 29, 30). The bus interface (14) converts information on address, data and control buses (16, 17, 18) to information on a generic address bus (20), a generic data bus (21) and a generic control bus (14). The peripheral components (24, 25, 26, 27, 28, 29, 30) are connected to each of the generic buses (19, 20, 21).

Description

UNIVERSAL PROCESSOR INTERFACE COMPONENT
TECHNICAL FIELD
The present invention relates to interface circuits. More specifically, it relates to microprocessor interfaces.
BACKGROUND ART
When designing microprocessor-based electronic systems, there are a variety of microprocessors available. By way of example only, there are the Motorola 68000 family, Intel 8086 family and MIL-STD-1750 family of microprocessors. The choice of a microprocessor in a particular situation is dependent upon factors such as architecture, system requirements, processing speeds for particular algorithms, bus interfaces, characteristics of instruction sets and available development systems.
Regardless of the microprocessor selected, peripheral components must be interfaced with he microprocessor. Therefore a microprocessor interface must be designed in accordance with the selected microprocessor. This task, however, involves significant effort and cost. Needed is an interface component which provides peripheral functions independent of the selected microprocessor.
DISCLOSURE OF THE INVENTION
The present invention is a component for selectably providing an interface to one of a plurality of microprocessors. The component includes a bus interface and one or more peripherals. The bus interface converts information on address, data and control buses from one of the microprocessors to information on a generic address bus, a generic data bus and a generic control bus. The peripherals are connected to the generic buses.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an interface component in accordance with a preferred embodiment of the present invention; and
FIG. 2 is a block diagram of the bus interface illustrated in FIG. 1.
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 illustrates an interface component 10. A microprocessor 12 is connected to a bus interface 14 through an address bus 16, a data bus 17 and a control bus 18. The buses 16 to 18 carry information in accordance with the protocol of the particular microprocessor 12. By way of example only, the information can be organized in accordance with a 68000 protocol, an 80386 protocol or the protocol of any other microprocessor. The bus interface 14 converts the information on the buses 16 to 18 to information on generic buses 19 to 21. Generic bus 19 is a control bus that provides control signals that coordinate the use of the generic buses 19 to 21. Generic bus 20 is an address bus and generic bus 21 is a data bus. A microprocessor clock signal is provided to the bus interface 14 on a line 22 so as to allow the bus interface 14 to synchronize the information on the generic buses 19 to 21 to the information on the microprocessor buses 16 to 18.
In a preferred embodiment, there are a plurality of peripherals 24 to 30 connected to the generic buses 19 to 21. Peripheral 24 is a Programmable Memory Decoder which defines the microprocessor address space occupied by various memory devices, such as random access memory (RAM) and read only memory (ROM) or by I/O devices. The Programmable Memory Decoder 24 monitors the address bus 20 and the control bus 19 and generates the chip selects for the various memory devices at the appropriate times. Such a device is well known to one skilled in the art of microprocessor design.
Peripheral 25 is a Programmable Wait State
Generator which monitors the generic address bus 20 to determine which device is being addressed by the microprocessor 12. The speed of the device being addressed is stored in the Wait State Generator 25 so that a READY signal can be generated to the microprocessor 12. The READY signal specifies when information is ready for transfer. The Wait State Generator 25, therefore, allows slower devices to communicate with the microprocessor 12. Such a device is well known to one skilled in the art.
Peripheral 26 is a Universal Asynchronous Receiver Transmitter (UART) which provides a serial communication channel for the microprocessor 12. A UART such as the 16550 available through National Semiconductor can be utilized if the bus interface 14 is a separate component. If, as in a preferred embodiment, the UART 26 is included on a single substrate with the bus interface 14, the UART 26 can be designed by one skilled in the art.
Peripheral 27 is a Direct Memory Access (DMA) Controller which controls data transfers between memory or peripheral devices independent of the microprocessor 12. A device such as the 82258 available through Intel can be utilized if the bus interface 14 is a separate component. If, as in a preferred embodiment, the DMA Controller 27 is included on a single substrate with the ° bus interface 14, it can be designed by one skilled in the art.
Peripheral 30 is a Bus Arbitration and Control circuit and is related to the DMA Controller 27. When the DMA Controller 27 is transferring data between 5 devices, it needs to control the generic buses 19 to 21 The microprocessor 12, therefore, loses control of the generic buses 19 to 21 during such a transfer. The Bus Arbitration and Control circuit 30 is informed of a direct memory access on the line 32 and then controls the 0 generic buses 19 to 21 and locks out the microprocessor 12 at the appropriate times. Such a device is well known to one skilled in the art.
Peripheral 28 is a Programmable Interval Timer which solves the timing control problems common in
-- microprocessor-based systems. A device such as the 8254 available through Intel can be utilized if the bus interface 14 is a separate component. If, as in a preferred embodiment, the Programmable Interval Timer 28 is included on the same substrate as the bus interface
30 14, it can be designed by one skilled in the art. Peripheral 29 is a Priority Interrupt Controller (PIC) which provides a multi-level interrupt system for the microprocessor 12. A device such as the 8259 available through Intel can be utilized if the bus interface 14 is a separate component. If, as in the preferred embodiment, the PIC 29 is included on the same substrate as the bus interface 14, it can be designed by one skilled in the art.
Other peripherals can also be utilized in the component 10 if desired or needed. Any differences in speed between peripherals is accommodated by the Wait State Generator 25.
Referring to FIG. 2, a preferred embodiment of the bus interface 14 includes a Select MUX 40, a Memory Read Sequencer 41, a Memory Write Sequencer 42, a System Data Enable and Direction Sequencer 43, an I/O Read Sequencer 44, an I/O Write Sequencer 45 and an I/O Data Enable and Direction Sequencer 46.
The address bus 17 and the data bus 18 from the microprocessor 12 are output from the bus interface 14 as the generic address bus 20 and the generic data bus 21, respectively. These buses 17, 18 are used by the various peripherals 24 to 30.
The Select MUX 40 receives three control buses 16A, 16B and 16C corresponding to the 68000 control bus, the 80386 control bus and the 1750 control bus, respectively. In alternate embodiments, however, other microprocessor control buses can be provided. Additionally, any number of microprocessor interfaces could be provided. Pins 48 and 50 are hardwired to select the proper control bus 16A, 16B or 16C in accordance with the selected microprocessor 12. The selected control signals are output from the Select MUX
40 to the devices 41 to 46. The address bus 17 and the data bus 18 from the microprocessor 12 are also input to the devices 41 to 46. The microprocessor clock signal is input to the devices 41 to 46 on the line 22 to allow synchronization of the control signals on the bus 19.
The signals outputted by the devices 41 to 46 form the generic control bus 19 which is used to control the various peripherals 24 to 30. The Memory Read Sequencer
41 outputs a signal MEMRD at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock signal so as to control memory read cycles for the various peripherals 24 to 30. The Memory Write Sequencer 42 outputs a signal MEMWR at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock signal so as to control memory write cycles for the peripherals 24 to 30.
The System Data Enable and Direction Sequencer 43 outputs signals SYSDEN and SYSDTR at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock signal so as to control the enabling of data transfer and the direction of data transfer, respectively, for the peripherals 24 to 30.
The I/O Read Sequencer 44 outputs a signal IORD at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock so as to control I/O read cycles for the peripherals 24 to 30. The I/O Write Sequencer 45 outputs a signal IOWR at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock signal so as to control I/O write cycles for the peripherals 24 to 30.
The I/O Data Enable and Direction Sequencer 46 outputs signals IODEN and IODTR at the appropriate times as indicated by the control lines from the Select MUX 40 and the microprocessor clock signal so as to control the enabling of data transfer and the direction of data transfer to I/O devices in the peripherals 24 to 30, respecti ely.
While the bus interface 14 can be implemented as a separate component which is interfaced to the various peripherals, it is preferred to implement the bus interface 14, the various peripherals 24 to 30 as well as any other desired peripherals on a single substrate, as illustrated in FIG. 1. Alternatively, any combination of the peripherals 24 to 30 or any other peripherals can be included with the bus interface 14. It is further preferred to provide the generic buses 19 to 21 at external pins of the single substrate, thereby allowing the use of additional peripherals not originally included on the single substrate.

Claims

WE CLAIM;
1. Apparatus (10) for selectably providing an interface with address, data and control buses (16, 17, 18) of one (12) of a plurality of microprocessors, said apparatus (10) characterized by:
generic control, address and data buses (19, 20, 21); and
bus interface means (14) for converting information on the data, address and control buses (16, 17, 18) of said one microprocessor (12) to information on said generic control, address and data buses (19, 20, 21).
2. Apparatus (10) according to Claim 1, wherein said bus interface means (14) is supplied with a plurality of control buses (16A, 16B, 16C) from said plurality of microprocessors (12), and wherein said bus interface means (14) is characterized by:
selecting means (40) for selecting one of said plurality of microprocessor control buses (16A, 16B, 16C); and
control signal means (41, 42, 43, 44, 45, 46), responsive to an output of said selecting means (40), for generating a plurality of control signals, which are supplied to said generic control bus (19).
3. Apparatus (10) according to Claim 2, characterized in that said control signal means includes a plurality of circuits (41, 42, 43, 44, 45, 46), each circuit generating a control signal in response to said output of said selecting means (40), outputs of said plurality of circuits (41, 42, 43, 44, 45, 46) being 5 supplied to said generic control bus (19).
4. Apparatus (10) according to Claim 3, characterized in that said plurality of circuits (41, 42,
1043, 44, 45, 46) generate a plurality of control signals including Memory Read Sequence, Memory Write Sequence, System Data Enable, System Direction Sequence, I/O Read Sequence, I/O Write Sequence I/O Data Enable and I/O Direction Sequence.
15
5. Apparatus (10) according to Claim 1, further characterized by a programmable wait state generator (25) connected to each of said generic buses (19, 20, 21).
0 6. Apparatus (10) according to Claim 5, further characterized by the following peripherals connected to each of said generic buses (19, 20, 21): a memory decoder (24), UART (26), DMA controller (27), programmable interval timer (28) and PIC controller (29). 5
7. Apparatus (10) for selectably providing an interface to address, data and control buses (16, 17, 18) of one (12) of a plurality of microprocessors, said apparatus (10) characterized by: 0 generic control, address and data buses (19, 20, 21);
5 selecting means (40) for selecting one of said plurality of microprocessor control buses (16A, 16B, 16C);
control signal means (41, 42, 43, 44, 45, 46), responsive to an output of said selecting means (40), for generating a plurality of control signals, which are supplied to said generic control bus (19);
means for coupling said microprocessor address and data buses (16, 17) to said generic address and data buses (20, 21); and
a programmable wait state generator (25) connected to each of said generic buses (19, 20, 21).
PCT/US1991/006968 1990-10-03 1991-09-25 Universal processor interface component WO1992006433A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59240490A 1990-10-03 1990-10-03
US592,404 1990-10-03

Publications (1)

Publication Number Publication Date
WO1992006433A1 true WO1992006433A1 (en) 1992-04-16

Family

ID=24370514

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1991/006968 WO1992006433A1 (en) 1990-10-03 1991-09-25 Universal processor interface component

Country Status (1)

Country Link
WO (1) WO1992006433A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613936A (en) * 1983-02-25 1986-09-23 International Business Machines Corporation Centralized generation of data transfer acknowledge pulses for microprocessors
EP0333318A2 (en) * 1988-03-14 1989-09-20 Advanced Micro Devices, Inc. Microprocessor interface circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613936A (en) * 1983-02-25 1986-09-23 International Business Machines Corporation Centralized generation of data transfer acknowledge pulses for microprocessors
EP0333318A2 (en) * 1988-03-14 1989-09-20 Advanced Micro Devices, Inc. Microprocessor interface circuits

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
EDN ELECTRICAL DESIGN NEWS. vol. 31, no. 20, October 1986, NEWTON, MASSACHUSETTS US pages 187 - 192; ARTHUR KHU: 'FPCs and PLDs simplify VME Bus control' see page 187, right column see page 190, right column, paragraph 3 - page 192, right column SA 52243 030see figure 1 *
ELECTRONIC DESIGN. vol. 30, no. 26, December 1982, HASBROUCK HEIGHTS, NEW JERSEY pages 169 - 175; ROLAND HOAR: 'uC chip with UART champions multiprocessor systems' see page 169, right column, paragraph 2 - page 170, left column, paragraph 1 see figure 1 *
ELECTRONIC DESIGN. vol. 32, no. 16, August 1984, HASBROUCK HEIGHTS, NEW JERSEY pages 209 - 222; ALEX GOLDBERGER ET AL.: 'Dual-UART chip assumes broader processing role in asynchronous systems' see page 209, right column, paragraph 2 see page 211, right column, paragraph 2 - page 212, left column, paragraph 1 SA 52243 030see figure 2 *

Similar Documents

Publication Publication Date Title
EP0233373B1 (en) Programmable communication card
EP0167827B1 (en) Interrupt level sharing circuit
US5101498A (en) Pin selectable multi-mode processor
US4534011A (en) Peripheral attachment interface for I/O controller having cycle steal and off-line modes
KR930008039B1 (en) Bus master interface circuit with transparent preemption of a data transfer operation
EP0518488A1 (en) Bus interface and processing system
CA2050129A1 (en) Dynamic bus arbitration with grant sharing each cycle
WO1996000940A1 (en) Pci to isa interrupt protocol converter and selection mechanism
GB2302744A (en) PCMCIA card with communications and memory functions
JPH09212447A (en) Interruption common use technology on pcmcia card
US5465333A (en) Apparatus for programming the speed at which an expansion card generates ready signals to insure compatibility with the speed of an attached bus
JPH04350754A (en) Workstation including interface for data channel or similar data processing system
WO2000034878A1 (en) Programmable pull-up for a universal serial bus interface
JPH052552A (en) Workstation having burst mode capacity
EP0473455B1 (en) Work station having burst mode data transfer
WO2005083577A2 (en) Integrated circuit with two different bus control units
EP0473280B1 (en) Communication control system for a computer and peripheral devices
EP0473453B1 (en) Work station having a selectable CPU
US6052746A (en) Integrated circuit having programmable pull device configured to enable/disable first function in favor of second function according to predetermined scheme before/after reset
WO1992006433A1 (en) Universal processor interface component
EP0079140A1 (en) Multiple computing systems and communication bus structure therefor
JPH04350753A (en) Workstation having direct memory access controller and interface device for data channel
JPH0343804A (en) Sequence controller
EP0130471A3 (en) Interface controller for connecting multiple asynchronous buses and data processing system including such controller
EP0330110B1 (en) Direct memory access controller

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IT LU NL SE

122 Ep: pct application non-entry in european phase