WO1992001284A1

WO1992001284A1 - Track counting arragement and method

Info

Publication number: WO1992001284A1
Application number: PCT/US1991/004837
Authority: WO
Inventors: Noboru Kimura; Ronald G. Vitullo
Original assignee: Most Research Corporation
Priority date: 1990-07-12
Filing date: 1991-07-10
Publication date: 1992-01-23

Abstract

A system (10B) for controlling the movement of a head (10), in an optical disc system, wherein the velocity of track crossing of the head (10), is determined and compensated for signals that occur too fast or are missing. The number of tracks actually crossed is compared with the determined number to be crossed, and a signal corresponding to the desired speed of the head (10) is generated therefrom. This signal is compared with the velocity of the track crossings to produce an error signal for controlling a traversing mechanism for the head (10). A circuit (12) is provided for more precisely controlling the direction and velocity of the head (10) in response to an overshoot or an undershoot of the head (10) with respect to the track on which the head (10) is to be set. The system also includes focusing systems (106) for focusing a laser (200) in the head (10), a drive control system (201) for controlling the laser (200) drive, and a PLL controll circuit (400) responsible to signals from the head (10).

Description

TRACK COUNTING ARRANGEMENT AND METHOD

Background of the Invention

This invention is directed to the provision of a method and apparatus for controlling the adjustment of a sensing head with respect to the tracks of a disc, such as an optical disc.

Summary of the Invention

The present invention is directed to the provision of an improved circuit enabling the detection of track crossing under noisy signal environment conditions. In accordance with the invention, track crossing signals from the detector are applied to a velocity counter via a window or gate. The signals passing the gate are also directed to a track counter that counts down in response to the output of the gate, the track counter having been initially set to the number of tracks to be crossed. A track crossing signal to the track counter is deleted if multiple transitions are detected during the count of an early counter. A track crossing signal is inserted in the track counter when a track crossing signal is not detected after the count of a missing counter timer has elapsed.

The output of the track counter is applied to a PROM to obtain a signal corresponding to the velocity that the head should have in view of the number of tracks remaining to be crossed. This signal is combined with the output of the velocity counter PROM to obtain an error signal fo controlling the speed of the head traversing mechanism. The invention also provides a system for mor accurately controlling the movement of the head upon th overshoot or undershoot of the track on which the head i to be set.

The invention further includes means for controllin the focus of a laser employed in the head, and means fo controlling the drive of the laser.

Brief Description of the Drawing

In order that the invention may be more clearly understood, it will now be disclosed in greater detail with reference to the accompanying drawing, wherein: FIG. 1 is a block diagram illustrating a portion of a track crossing counting system in accordance with the invention;

FIG. 2 is a circuit diagram of one embodiment of a digital tracking filter that may be employed in the system of FIG. 1;

FIG. 3 illustrates various waveforms in the circuit of FIG. 2;

FIG. 4 is a block diagram illustrating another portion of a track crossing counting system in accordance with the invention;

FIG. 5 is a block diagram of one embodiment of a track follower logic correction circuit that may be employed for the logic circuit of FIG. 4;

FIG. 6 illustrates various waveforms in the circuit of FIG. 5;

FIG. 7 is a block diagram of a laser diode control circuit; and

FIG. 8 is a block diagram of a control circuit for the PLL in a system of the type of the invention.

Detailed Description of the Invention

Referring now to FIG. 1, in accordance with th invention, a conventional sensing head or detector 1 includes a laser diode and a photo detector positioned t sense light reflected from an optical disc. Optical disc have a plurality of concentric tracks upon which data i optically stored. The detector 10 is mounted upon traversing mechanism 10A of conventional form, and a conventional control system 10B is provided fo controlling the detector to be moved transversely of th tracks of the disc. The control system may comprise processor that also controls further functions of th system.

The detector 10 senses tracks on the optical disc as it crosses them. The output of the detector 10, as it is moved transversely of the tracks, as well as other signals which will be considered here to constitute noise. I accordance with the invention, it is necessary to separate the track crossing signals from the noise signals to as great an extent as possible. For this purpose, the output of the detector is applied to a low pass filter 11 having a pass range that to filter out high freguency noise. The filter 11 thus has a cutoff frequency just higher than the maximum rate at which the head crosses the tracks. The filter 11 amplifies the signals and filters high frequency noise. The output of the filter 11 is applied to a shaping circuit 12 which converts the analog signal to a digital signal corresponding to "raw track crossings".

The output of the shaping circuit 12 is applied to a digital tracking filter 13 having an equivalent cutoff frequency that is varied as a function of the velocity of movement of the head, since it is not permissible to filter out noise of a frequency that corresponds to the track crossing frequency. This filter 13 is basically a counter that is used as a retriggerable one shot whose delay is proportional to the count of the velocity counter. The digital tracking filter 13 serves to eliminate the effects of noise present on the raw track crossing signal. This noise may be caused by media defects, external signals inductively transduced into the system, and the like. Referring to FIG. 2, the filter includes an edge generator 200 connected to receive the raw track crossing signal and a digital counter 202 such as a 74191, which receives a scaled down value of the velocity count. The velocity count is scaled down by means of a decoder 204 which operates to reduce the velocity count by a specifically chosen factor which in turn determines the delayed time T of output signals at the delay output of counter 202. Thus, if it is desired to filter out noise for the first 12 1/2% of the time of the leading edge of the raw track crossing signal, the decoder is set to scale down the velocity counter by 12 1/2%. This is the preferred value, but it will be apparent that other values may be selected, using a decoder to scale the count. The same effect may be achieved by choosing an appropriately valued clock signal. For example, if a nominal clock signal at CLKL is 5.66 MHz, then a 12 1/2% sealer value for delay purposes may be achieved by setting the clock value at eight times 5.66 MHz and selecting a pulse output designed to scale down from the value by 12 1/2%. Since this would require a clock signal generator of over 40 MHz, it is preferable to modify the delay be modifying decoder 204 instead. The delayed signal is then applied as a strobe for a D-flip-flop 206, to which the raw track crossing signal is applied at the D input. The final filtered output thus generates a clean pulse unaffected by noise levels occurring anywhere inside the raw track crossing envelope within the 12 1/2% time scale. Samples of the pulse waveforms at various locations of Fig. 2 are illustrated in Fig. 3. Thus, line A of Fig. 3 shows a typical raw track crossing signal, with noise thereon. Line B illustrates the pulsatory output of the edge generator 200. Line C illustrates the DELAY output of the counter 202, and line illustrates the output of the flip flop 206.

The digital tracking filter filters out as man signals as possible that correspond to false trac crossing signals, since this signal is used to count th number of tracks that have been crossed, as well as t determine the velocity of the detector head. Since th frequency of track crossings varies with the velocity o the head, a simple low pass filter can be employed onl to filter out signals higher than the maximum trac crossing frequency. The digital tracking filter therefor serves to vary the filter frequency as a function of trac crossing frequency (velocity) , to provide improve filtering of the signal. The output of the filter 13 is applied to a gate o window circuit 14, an early counter 15, and a missin counter 17. An output of the window 14 is applied to velocity counter 18 for producing an output digital signa corresponding to the velocity of track crossing. Th velocity counter 18 counts the number of high frequenc clock pulse CLK1 that occur during each track crossin interval, so that the output of this counter is a digita signal corresponds to the velocity of the head. Th output of the counter 18 is thus employed to control th tracking filter 13, to thereby filter out signals of frequency that differ, within a given range, of th current track crossing frequency.

A clock generator 19 is provided for outputting th clock signal CLK1 for clocking the velocity counter 18, so that the output of this counter corresponds to th number of clock pulses that occur between adjacent trac crossing signals output from the tracking filter 13. Th window circuit 14 is controlled for the transmission o signals by the early counter 15 and the missing counte 17, to prevent the passage of false track crossing signals so that the velocity counter 18 is not triggered b outputs of the tracking filter that occur at times that could not correspond to actual track crossings, e.g. considering maximum acceleration and deceleration of the head.

The early counter is clocked continuously by a clock signal CLK2 that is faster than CLK1, and the missing counter is clocked continuously by a clock signal CLK3 that is slower than CLK1. The early and missing counters produce outputs in response to predetermined counts therein. These counts are preset corresponding to the output of the velocity counter by the output of the tracking filter. The preset counts hence correspond to the last count of the velocity counter 18.

The early counter is preset to approximately 50% of the velocity counter. If two or more pulses are received from the tracking filter during the 50% window, these pulses will be inhibited from passing the velocity counter and to the track counter.

The output of the window is also applied to a track counter 20, which compares the count of the number of track crossing signals received from the window 14 with a count set therein that has been received from a source 21 of a count corresponding to the number of tracks to be crossed to reach a predetermined track. The source 21 may thus be a part of the control processing system that has stored the present track position, and calculates the number of tracks that must be crossed to reach a track for reading or writing data. The counter 20 thus may be preset by the output of the source 21, to count down in response to counts that have passed the window 14. This output os the track counter 20 hence corresponds to the number of tracks that must still be crossed to reach the desired track position.

It is evident that the output of the track counter 20 will not correctly represent the number of track crossings that must be made when a dropout occurs. Therefore, in accordance with the invention, a missing counter 17 is provided to apply a count to the track counter via window 14. The missing counter is set to th count output corresponding to 2.0 times of the velocit counter 18. The missing counter 17 will generate a trac crossing signal to the track counter 20 if no pulse i received from the tracking filter when it reaches thi terminal count of 2.0 times the velocity count.

As illustrated in Fig. 4, the velocity count outpu of the velocity counter 18 is applied as an address to velocity prom 30, to provide a scaled output, and thi output is converted to analog form in the D/A converte 31. For example, the output of the velocity counter ma be a 12 bit count, whereby the velocity prom 30 ma convert this value to an 8 bit value for the D/A converte 31. The difference count from the track counter 20 i applied as an address to a velocity profile prom 32. Th profile prom translates the difference signa corresponding to the number of tracks still to be crossed, to a stop profile corresponding to the desired velocit of the detector head when the head has that many track still to be crossed. This output is converted to analo form in the D/A converter 33. The outputs of the two D/ converters 31, 33 are applied to a summing amplifier 34 to provide an error voltage output. This error voltag is an analog voltage having a value corresponding to th difference between the actual velocity and the desire velocity.

If the tracks of the optical disc are not centere with the axis of the disc, it is evident that the trac crossing rate may vary as a function of the angula displacement of the disc at the time that the trac crossing was detected. In accordance with the invention, this effected may be compensated by providing a signal fo application to the sum amplifier 34 corresponding to the velocity component due to an out of round condition of th disc.

Referring still to Fig. 4, when the disc is initially inserted in the system the tracking servo is locked onto a track. The output of the head at this time, during rotation of the disc, due to off center positioning of the disc, is converted to digital form in an A/D converter 50 and stored (with respect to an index position) in a memory 51. For this purpose, an index pulse may be provided responsive to a given alignment of the disc for setting an address counter 52 to a reference address, the address output of the counter 52 being stepped in response to a clock signal corresponding to a given angular displacement of the disc. A write pulse is supplied by the processor of the system at predetermined intervals. The memory 51 thus stores values corresponding to the eccentricity of the disc at each angular displacement thereof with respect tot the index. At each instant that a measurement is made of the track crossings, the relative radial displacement of the track at the position of the head, with respect to the position it would have if the disc were perfectly concentric, is read out of the memory 51. This signal is converted to analog form in the D/A converter 53, and applied to the sum amplifier 34 as a correction factor for the eccentricity of the disc.

In an optical servo system, the track following mode must capture the track within +/- 1/4 of a track. The system in accordance with one embodiment of the invention is designed to extend this capture range to +/- one track by sampling the sum signal immediately following a seek. If the sum signal crosses the baseline following a seek, the correction logic automatically does a RESEEK to the target track by sensing the corrected direction. This will prevent a seek error due to excessive overshoot or undershoot.

Referring to Fig. 4, the logic circuit 60 comprises a track follower correction logic circuit for correcting the positioning signal after completion of initial positioning of the head. In this circuit, a polarity switch 62 is connected to receive the output of the sum amplifier 34, and responds to a corrected direction signal from the logic circuit 60 to reverse the head directio of an overshoot has occurred, or to continue correctio in the same direction if an undershoot has occurred. Th logic circuit 60 responds to an END OF SEEK signal to tes the head position and to issue a RESEEK signal along lin 64 to gate 66. The presence of the RESEEK signal permit the proper polarity error voltage correction to pass gat 66 to finalize the head position.

As illustrated in Fig. 1, the END OF SEEK signal i derived from the counter 20, and is output by the counte when the difference count from this counter reaches zero

A preferred embodiment of the track follower logi correction circuit 60 is illustrated in Fig. 5. A illustrated in this figure, the outputs of the detecto 10 are also applied to a summing circuit 210. The outpu of the summing circuit 210 is shaped in a shaping circui

212, and the output of the shaping circuit is applied a a signal SSQ to the D input of a D-flip-flop 216. The SS signal is also applied as the signal input to a zer crossover detector 220. The END OF SEEK signal is applie to the detector 220, and is also applied as a clock signa to the flip-flop 216. The output of the zero crossove detector comprises the RESEEK signal. The output of th flip-flop 216 is compared with the initial directio signal (output from the count source 21 of Fig. 1 and th start of a seek), in the comparator 218, to provide th direction correction signal for controlling the polarit switch 62 of Fig. 4.

In the logic circuit of Fig. 5, when a zero crossin is detected after the END OF SEEK, a RESEEK signal i generated. The direction (e.g. logic level) of RESEEK i determined by the polarity of the output SSQ of th shaping circuit 212 and the time of occurrence of the EN OF SEEK signal. When the difference output of track counter 20 (Fig.

1) goes to 0, then the system goes into track followe mode, by generating an END OF SEEK signal on line 214. Count source 21 of Fig. 1 also provides an initial seek signal and an initial direction signal when the system starts to seek a new track. The sum signal SSQ, corresponding to the shaped output of the detector 10, is monitored in the circuit of Fig. 5, so that its polarity just prior to crossing of the base line is determined upon the occurrence of an END OF SEEK signal, unless the zero crossover occurs substantially at the time of the END OF SEEK signal. Fig. 6A illustrates a condition wherein the zero crossover P of the signal SSQ occurs after the transition of the END OF SEEK signal, and was positive just prior to this time. This condition implies that the head has gone beyond a +/- 1/4 track capture range. Accordingly, the correction logic circuit responds to the positive polarity of SSQ prior to zero crossing to reverse the initial direction signal and to simultaneously generate a RESEEK signal.

When the sum signal SSQ crosses the baseline from a negative direction after the END OF SEEK signal, as illustrated in Fig. 6B, a track undershoot condition has occurred. In this instance, the direction correction signal does not change its polarity, since the previous direction of movement is still correct. A RESEEK signal is also generated at this time.

If the SSQ signal remains above the baseline after the END OF SEEK signal, as illustrated in Fig. 6C, then no further track crossings have occurred in either direction and no RESEEK signal is generated. The logic that controls the direction correction output and the RESEEK output is implemented by flip-flop 216, comparator 218 and zero crossing detector 220. In the event of an overshoot, as shown in Fig. 6A, the flip- flop 216 detects a positive SSQ waveform at the END OF SEEK to provide a polarity reversing direction correction signal for the circuit of Fig. 4. In the event of an undershoot, as illustrated in Fig.

6B, the logic detects the negative waveforms at the tim of the END OF SEEK transition, to maintain the previou direction correction signal. In the case of correct hea position, as illustrated in Fig. 6C, since there is n zero crossing following the END OF SEEK signal, no RESEE signal is generated.

The system of the invention also includes a arrangement for controlling the focus of the lase employed in the head. The focus adjustment controls th effective diameter of the laser beam. When the laser bea is not properly focused, the detectors will not have a maximum output at a predetermined rf wavelength since the beam will be irradiating too large a region on the disc, whereby the rf amplitude of the signals detected by the detector is decreased. In accordance with the invention, the laser beam is focused, by conventional focusing means lst/2nd then in order to maximize the rf output of the detector, in a predetermined rf wavelength, in response to sensing of the preformat region of the disc. Referring again to Fig. 1, the output of the detector 10 is applied to a band pass filter 100. This signal is then amplified and rectified in circuit 101 and sampled in a sample and hold circuit 102. The signal is sampled at the time the detector is scanning the preformat region of the disc, under the control of the control processor 10B. The output of the sample and hold circuit is converted to digital form in the A/D 103, and then applied to the processor 10B. The processor 10B outputs a control signal to the D/A circuit 105 for controlling a focus servo 106 to adjust the focus offset (beam diameter) of the laser in the head until the output of the band pass filter 100, and hence the output of the A/D 103, is maximized.

The filter 100 is tuned to the band of the highest possible frequency recorded in the preformat region of the disc which, in one arrangement employing a 3T pattern, is about 3.86 MHz, i.e., corresponding in 2-7 code to the shortest spacing 100100.

In a further feature of the invention, a circuit is also provided for calibration of the laser diode. A laser diode under normal operation, for example, reading a disc, operates in an analog close-looped circuit. Thus, referring to Fig. 7, the laser circuit convention includes a laser 200 connected to be energized by a current drive 201, the laser diode and current drive being encased with a monitor photo diode 202. The monitor diode monitors the direct light output of the laser, and the output of this diode is amplified in a voltage amplifier 203 and fed back to the current drive 201.

In order to compensate for drift of the laser output with temperature and age, as well as to compensate for variations in different lasers, in accordance with the invention the output of the amplifier is applied to a A/D 205, and thence to the processor 34. The program of the processor outputs a control signal to the laser diode drive, via the D/A 207, in order to maintain the output of the amplifier 203 constant. The current drive 201 is also controlled by the processor 34 to control its output. The calibration of the laser in the above manner is preferably effected only each time a new disc is inserted. There are four calibrations, i.e. read, write bottom, write peak and erase.

In accordance with a further embodiment of the invention. Fig. 8 illustrates a circuit in accordance with the invention for preventing unwanted pulses from being applied to the PLL 400, in order to filter out certain types of defects, and also to allow the read channel to operate properly under less than ideal conditions. The PLL 400 is employed to synchronize the clock frequencies in the circuit of the invention, as above discussed, in conventional manner. The pulses read from the disc will by varying in frequency and depending upon the number of zeros spaced in between the ones, there will be a pattern of alternating low and high frequencies. If they is long string of zeros between the ones, a low frequenc pattern will result. It's very easy for the drive unde low frequency pattern. In this case the signal wil basically always have a large amplitude. It doesn' require high resolution to detect such a signal. When th frequency is increased, the pattern may start to decreas in amplitude. In order to recover timing information, ideally it is desirable to have one pulse applied to th PLL for each peak recorded on the disc. A 3T pattern suc as discussed above may have a less than 50% resolution, i.e., the difference in amplitude between the lowest an highest frequency patterns. There are two channels fo the read signal. One of the channels includes differentiator 401 which outputs a pulse for each pea detected in the signal, whether it be positive o negative. The other channel includes a zero crossin detector 402 having some hysteresis for noise rejectio around the base line. The output of the zero crossin detector is either at logic high or low with respect t the base line.

The output of the differentiator 401 is ANDED wit the positive output of the zero crossing detector, in th AND gate 405. Normally the output of the AND gate may go directly to a PLL 400 without a filter. When the tw signals are ANDED as above discussed, the flip flop is set, it can no longer be set again until it is reset, s this pulse will be held. The delay line 411 resets th flip flop after a predetermined time. This circuit prevents any type of noise above the highest frequency from being applied to the PLL and also effectively increases the high frequency resolution. So, typically on the outside of the disc, the high frequency pattern will almost have the same amplitude as the low frequency pattern. This circuit thereby prevents unwanted pulses from being applied to the PLL. This filter is also desirable since on the inside tracks, the high frequency signal may not go below the baseline. The filter also filters out "garbage".

While the invention has been disclosed and described with reference to a single embodiment, it will be apparent that variations and modification may be made therein, and it is therefore intended in the following claims to cover each such variation and modification as falls within the true spirit and scope of the invention.

Claims

What Is Claimed Is;

1.. A track counting system for counting the number of tracks of an optical disk that have been traversed by a reading head, comprising a track crossing detector for producing track crossing pulses, a gate connected to receive said pulses, a velocity counter connected to receive said pulses via said gate, to produce a signal corresponding to the velocity of said head, a track counter connected to receive said pulses via said gate for outputting a signal corresponding the number of tracks that have been crossed, means for deleting pulses occurring at a rate faster than the head could pass said tracks, and means for applying additional pulses to said track counter when pulses from said detector are missing.

2. A tracking counter system for producing an accurate track count for accurately tracking across a recording media, said recording media including a plurality of tracks arranged about a central point, said system comprising a transducing mechanism movable across said tracks and including a track detecting means for producing pulse corresponding to track crossings; a velocity counting means counting at a first rate for providing a reference count representing the velocity of said transducing mechanism relative to its passage across said tracks; first counting means coupled to receive said pulses and counting a rate greater than said reference rate for producing a first count; second counting means counting at said reference rate; gating means for applying pulses from said track detecting means to said velocity counting means; track counting means coupled to count the output of said gating means, said second counting means being coupled to receive said pulse for applying an additional count to said track counting means if no pulse is output from said track detecting means within a predetermined time following the last output of said gating means; and said track counting means thereby producing an accurate track crossing count.

3. The tracking counter system of claim 2 wherein said track detecting means includes a digital tracking filter, and means responsive to said reference count for controlling the pass frequency of said digital tracking filter.

4. The tracking counter system of claim 3 wherein said digital tracking filter comprises a pulse generator means connected to receive the output of said detecting means, decoding means connected to provide an output that is less by a predetermined amount than said reference count, and a delay circuit for delaying the output of said pulse generator means in response to the output of said decoding means, to produce said pulses.

5. The tracking counter system of claim 4 wherein said delay means comprises a digital counter, and wherein said digital tracking filter further comprises a D flip flop connected to be set in response to the output of said detecting means and clocked by the output of said digital counter, for producing said pulses.

6. The tracking counter system of claim 2 comprising means for resetting said first, second and third counters with the output of said velocity counter, and means for triggering said first and second c. inters with the output of said detector.

7. The tracking counter system of claim 2 furthe comprising a source of signals corresponding to a numbe of tracks to be crossed, for resetting said track counter wherein the output of said track counter corresponds t the number of tracks that remain to be crossed.

8. The tracking counter system of claim 7 furthe comprising signal conversion means connected to the outpu of said track counter for generating a signa corresponding to the desired head velocity of said head and means for comparing the output of said signa conversion means and said velocity counter for producin an error signal for controlling the movement of said head

9. The tracking counter system of claim 7 furthe comprising signal conversion means connected to the outpu of said track counter for generating a signa corresponding to the desired head velocity of said head means for comparing the output of said signa conversion means and said velocity counter for producin an error signal; track follower logic means responsive to sai error signal and to said pulses from said detecting mean for correcting said error signal to compensate fo overshoot and undershoot conditions; and means responsive to the output of said trac follower logic means for controlling the movement of sai head.

10. The tracking counter system of claim 9 wherein said track counting means comprises means for producing an END OF SEEK signal upon a predetermined count, and wherein said track follower logic means comprises means for detecting the polarity of said pulses prior to zero crossovers thereof that occur after said END OF SEEK signal; and means responsive to said polarity for modifying said error signal to produce a corrected error signal for controlling the movement of said head.

11. The tracking counter system of claim 10 wherein said means for detecting said polarity comprises a D flip flop connected to be clocked by said END OF SEEK signal; means responsive to said pulses for setting said flip flop; and means for comparing the output of said flip flop for controlling the direction of movement of said head.

12. The tracking counter system of claim 10 wherein said track follower logic means further comprises means for detecting a zero crossover of said pulse for producing a gating signal; and means responsive to said gating signal for gating said corrected error signal, whereby further movement of said head will occur only in the event of an undershoot or overshoot thereof.

13. A method for counting the crossing of tracks by a head in an optical disk system, wherein the system includes a reading head, and a track crossing detector for producing track crossing pulses, said method comprising counting pulses from said head to produce a velocity signal, counting pulses from said head to produce a signal corresponding the number of tracks that have been crossed, said counting of pulses to produce velocity and number of track signals including inhibiting the counting of pulses when said pulses occur at a rate faster than the head could pass, and counting additional pulses to produce said number of track signals when pulses from said detector are missing.

14. A system for producing error signals for controlling the velocity and direction of movement of a head adapted to cross recording tracks, for an arrangement having a head adapted to be moved across said tracks, to correct for overshoot and undershoot of said head, said system comprising a source of track crossing pulses corresponding to the crossing of tracks by said head; a source of an END OF SEEK signal responsive to the crossing by said head of a given track; a source of a difference signal responsive to the difference between the actual velocity of movement of said head and a predetermined velocity; means for selectively reversing the polarity of said difference signal, for producing said error signals; and logic means for controlling said polarity reversing means in response to the polarity of said pulses upon the occurrence of an END OF SEEK signal.

15. The system of claim 14 wherein said logic means comprises means for controlling said polarity reversing means to reverse the polarity of said error signal only when said logic means detects a first polarity of said pulses upon the occurrence of said END OF SEEK signal.

16. The system of claim 15 wherein said means for controlling said polarity reversing means comprises a D flip flop connected to be clocked by said END OF SEEK signal; means inputting said pulses to said D flip flop whereby the logic level of the output of said flip flop at the time of said END OF SEEK signal corresponds to the polarity of said pulse; and means for comparing the output of said flip flop with a signal of predetermined polarity for producing a signal for controlling said polarity reversing means.

17. The system of claim 14 further comprising gating means for selectively blocking the output of said polarity reversing means; and a zero crossing detector for detecting a zero crossing of said pulses following an END OF SEEK signal for controlling said gating means, whereby said gate is inhibited from passing said error signal in the absence of detection of a zero crossover.