WO1992000564A1

WO1992000564A1 - Circuit for alternately connecting one of several data lines to a common data read line

Info

Publication number: WO1992000564A1
Application number: PCT/EP1991/001160
Authority: WO
Inventors: Howard Peter Flowers; Gerry Meek
Original assignee: Ferguson Limited
Priority date: 1990-06-30
Filing date: 1991-06-22
Publication date: 1992-01-09
Also published as: CN1057933A; GB2246257A; GB9014608D0; AU8060291A; GB9113345D0

Abstract

Within data processing systems, for example in the NICAM decoder of a television receiver, data signals on a plurality of input lines have to be read and fed sequentially to a serial data bus. Normally for this purpose expensive integrated circuits with several inputs and ouputs are needed. It is an object of the invention to simplify this operation and to use a bus device which is less expensive than devices used up to now. A device having outputs only (for example OP1, OP2) is used for reading the said input lines sequentially. This is achieved by a diode/resistor matrix which is connected between each data input L1, L2, the outputs OP1, OP2 and the common DATA READ line RL. Thus an inexpensive device or devices having outputs only can be used for sequentially reading signals from a number of input lines.

Description

CIRCUIT FOR ALTERNATELY CONNECTING ONE OF SEVERAL DATA LINES TO A COMMON DATA READ LINE Within data handling systems e.g. in a NICAM de¬ coder of a television receiver, signals on different data input lines are usually read sequentially and fed to a common DATA READ line. This DATA READ line forms a serial bus and may be connected to a microprocessor. Normally for said purpose IC's with several outputs and inputs are needed which generally are very expensive.

It is an object of the invention to simplify said circuit by using a cheap bus device. According to the invention a device having port outputs only is pro¬ vided and a diode resistor matrix is connected between each data input line, the port output and the READ line in such a way that with a port output at high level, diodes connect the corresponding input line to the READ line whereas with port outputs at low level, di¬ odes disconnect the input line from the READ line.

Integrated circuits with outputs only are not normally able to read information. By the use of the invention, however, an IC having outputs only can read signals on different input lines and feed them sequen¬ tially to a common READ line. The main advantage lies in the fact that such IC's with outputs only are cheap¬ er than devices having both outputs and inputs. The reading process of the different signals at several input lines is controlled by the ports at the outputs of the output only device. Said ports can be controlled according to software in such a way that the signals at the different input lines are fed sequentially to the common READ line or serial data bus connected to a further microprocessor. Dedicated expensive integrated circuits are not needed, and multiple conducting paths together with corresponding multiple ports on the μP are eliminated.

The invention may be used to communicate data from peripheral devices via a single conductor to a μP using simple bus expansion. For example the invention may be used to communicate NICAM data signals via a sin¬ gle track/port to a microprocessor, either associated with, or within, a television receiver for further processing.

In one embodiment of the invention each input line is connected to the anodes of two diodes, the cath¬ odes of which are connected to the port outputs and to the READ line respectively. In operation the port outputs of the output only device are switched to high level sequentially for serial data transmission via the said READ line. In one form of the invention the device having outputs only is a normal inexpensive serial shift register.

In order that the invention may more readily by understood a description is now given by way of example only, reference being made to the sole Figure showing a circuit with two input lines according to the invention.

In the Figure, at terminal LI a first data signal is available symbolically indicated by switch SI, and resistor Rl. At input line L2 a second data signal is provided, symbolically indicated by switch S2, and resistor R3. The data signals at input lines LI and L2 are to be serially connected to common output line RL which may be a serial data bus connected to a microprocessor which is not shown. That means that a sequential reading process must be performed for the data signals at input lines LI and L2. Said reading pro¬ cess is effected by the output only device having two ports P1,P2 with outputs 0P1 and 0P2. Input line LI is connected via diode Dl to output 0P1 and via D2 to READ line RL whereas input line L2 is connected via diode D3 to output 0P2 and via diode D4 to the same READ line RL. Diodes are further biased by resistor R5 connected to ground. The operation of the circuit shown is as follows. Output OP1 is turned to high level (typically +5 V) by turning on the upper transistor and turning off lower transistor. High level at 0P1 appears at the cathode of Dl so that diode Dl is turned off. That means that input line LI is disconnected from 0P1 so that positive going data signal from input LI is fed Via turned on diode D2 to READ line RL. During this time output OP2 of port P2 is connected to low level by turning off the upper transistor and turning on the lower transistor. That means that output 0P2 is connect¬ ed to ground. The positive going data signal at input line L2 is suppressed by D3 and the lower transistor of port P2 both being turned on. As anode of D3 is connect¬ ed to ground diode D4 is turned off. Therefore, the data signal at input line L2 is not fed to READ line RL.

Within the next interval of serial data transmis¬ sion, output 0P1 is switched to low level so that the data signal at input line LI is disconnected from READ line RL. During this same interval output OP2 is turned to high level so that now the data signal at input line L2 is connected to READ line RL.

As can be seen by this simple example a sequen¬ tial reading of data signals at input lines L1,L2 is effected although the switching device has outputs only which normally cannot perform a reading process.

The output only device will usually have a great¬ er number of ports than P1,P2 for feeding sequentially a corresponding larger number of separate data signals each on a separate input line to the common READ line RL. The input lines L1,L2 might be realized by a special pin, for example pin 8 of a SCART cable. The output only device shown in the Figure may be an output port or a microprocessor or a port expander connected to a microprocessor via a serial or parallel bus or otherwise unused output ports on a device that would normally be present for another purpose , or for exam¬ ple in the form of a shift register of the type MC14094.

The output configuration of the output only de¬ vice shows a push-pull output transistor combination, but the devices can be of any appropriate technology, such as FET, also the output configuration could be open collector type, with a pull-up resistor.The only requirement is that the lower device can sink suffi¬ cient current via the input resistors Rl, R3, to pre¬ vent the diodes connecting the input data to the READ line (D2, D4) from switching on.

The polarity of the entire circuit can be inverted by appropriately reconfiguring the components therein.

Claims

CLAIMS 1. Circuit for alternately connecting one of sever¬ al data input lines to a common DATA READ line, characterized by a device having outputs only, and by a diode/resistor matrix connected between each data input line, the port output, and the READ line in such a way that with port output at high level diodes con¬ nect input line to READ line whereas with port output at low level diodes disconnect input line from READ line.

2. Circuit according to claim 1, characterized in that each input line is connected to the anodes of two diodes the cathodes of which are connected to the port output and to the READ line respectively.

3. Circuit according to claim 1, characterized in that the port outputs are turned to high level sequen¬ tially for serial data transmission via said READ line.

4. Circuit according to claim 1, characterized in that the output switching device is a microprocessor, a port expander connected to a microprocessor via a serial or parallel bus, or some otherwise unused ports on a device which is present for another purpose, or a shift register.

5. Circuit according to Claim 1, characterized in that the polarity of the circuit is inverted by reconfiguring the components therein.

6. Circuit as described within the specification and the drawing.