WO1990003066A1

WO1990003066A1 - Subranging analog-to-digital converter without delay line

Info

Publication number: WO1990003066A1
Application number: PCT/US1989/003872
Authority: WO
Inventors: Henry T. Tsuei
Original assignee: Analog Devices, Inc.
Priority date: 1988-09-07
Filing date: 1989-09-07
Publication date: 1990-03-22

Abstract

A subranging converter employing a flash converter and a current-summing DAC which produces a current output. The DAC has a set of 2n - 1 current sources and 2n - 1 digital switches. Each switch channels its associated current source output either to the common output summing node or to ground. Each DAC switch, other than the first switch, takes its control input directly from an associated comparator in the flash converter. The direct connection between the comparators and the DAC eliminates the need for a video delay line and provides a fast conversion process.

Description

SUBRANGING ANALOG-TO-DIGITAL CONVERTER WITHOUT DELAY LINE

Field of the Invention

This invention relates to analog-to-digital converters and, more particularly, to converters of the subranging type as well as to integrated analog-to-digital and digital-to-analog converters.

Background of the Invention

The present invention relates to high speed, high resolution analog-to-digital converters, ("A/D converters," or "ADC's"), including ADC's which are combined with digital-to-analog converters ("DAC's"). "High speed" refers to converters capable of operating on video signals, for converting data at a rate of at least 10 MHz. "High resolution" refers to the need for full accuracy conversion at, for example, a resolution of 10 bits or more.

A typical A/D converter architecture used for such applications is the multi-stage digitally corrected subranging A/D converter. Subranging converters are based upon the use of multiple parallel or "flash" converters. A good reference text on A/D converters and particularly subranging converters is Analog Devices, Inc., Analog Digital Conversion Handbook, Prentice-Hall, Inc., Englewood Cliffs, NJ (1986), including specifically Chapter 12 thereof. Fig. 1 shows the basic structure of a flash converter. The flash converter 10 comprises a voltage divider 12 driven by a reference source v f applied at terminal 14 and N = 2ⁿ - 1 comparators 16,—¹⁶w' ^where n represents the number of bits desired in the resolution of the digital output. The comparators are biased 1 LSB apart, starting with +1/2 LSB. The analog input voltage V. is applied to terminal 18, which is connected in parallel to one input of each of the comparators 16i. The other input of each comparator is connected to a respective one of the voltage divider taps. With V. = 0, all comparators are off. As the input ii creases, it causes an 'increasing number of comparators to switch state. The set of outputs of the comparators produce what is referred to as a "thermometer code" — that is, for a given value of V. , all comparator outputs "above" a corresponding point should be at logical zero and all comparator outputs "below" that point should be at logical one, which is analogous tj the mercury in a liquid thermometer. The thermometer code is applied to an encoder 20 which provides a corresponding set of bit values defining a digital word which represents the analog input voltage, (while the term "encoder" has been used for element 20, ther term "decoder" is also used in the art. Most frequently, encoder 20 is implemented with a read-only memory, or "ROM".) The principal advantage of flash converters is speed: their comparators all operate in parallel, providing a conversion which occurs in parallel. Speed is limited primarily by the switching times of the comparators and of the encoder. Unfortunately, the number of components in a flash converter (and, thus, power consumption and integrated circuit area) increases geometrically with resolution.

A modification to the full parallel approach of the flash converter, typically involving considerably less complexity for the same resolution and improved speed over the successive-approximation conversion technique, is the scheme known as digitally corrected subranging. This technique combines parallel conversion for moderate numbers of bits with iteration. For example, six or seven bits of flash conversion may be performed in two successive conversions to obtain, e.g., twelve bit resolution. Subranging converters, also called multi-stage converters, are generally used instead of flash-type converters whenever higher resolution and/or less complexity are required for the conversion function.

Fig. 2 illustrates a typical 12-bit subranging A/D converter 30 constructed with two encoders having resolutions that add up to 13 bits (6 bits and 7 bits, respectively, in this example). The analog signal from the track and hold circuit 32 is applied simultaneously to a video delay line 34 through an appropriate buffer 36 and to a 6-bit flash converter 38 via a buffer 42. The 6-bit flash converter converts the analog signal to a binary form, producing the six most significant bits of the result. These bits are stored in a register 44 and are also applied to a 6-bit D/A converter 46 having an accuracy of at least 12 bits. The output of the D/A converter 46 is inverted and subtracted from the delayed track and hold output by a summation network at the inverting input of amplifier 48, to form a "residue" signal. Amplifier 48 supplies gain to cause the amplitude of the residue signal to cover the full scale span of the 7-bit flash converter 50-. The 7-bit flash converter supplies additional digital output corresponding to the value of the residue (i.e., less-significant portion of the analog input value) . The outputs of the 6-bit holding register 44 (via register 51) and the 7-bit flash converter 50 are then combined in an output register 52 to yield a 12-bit parallel binary out ut .

Timing is extremely important in subranging converters, as each element in the conversion process must settle to its optimum point before the required strobe signals are applied by the timing generator. It is not unusual for subranging converters to exhibit differential-linearity -5-

discontinuities, particularly around the transition points between the stages, due to mismatch between the stages. However, in converters employing digitally corrected subranging, these discontinuities are largely eliminated by the use of digital correction logic, such as is indicated at 54, since the information to accurately characterize the MSB transition of the first conversion is already present in digital form because of the accurate D/A conversion and summing, and the LSB in the second conversion. Un ortunately, fast 6-bit DAC's with better than 12-bit accuracy are not easy to make, nor are fast subtracting amplifiers with, adequate dynamic linearity. The voltages at the summing junction at the inverting input of amplifier 4^*8, and at the output of that amplifier, must settle before the second conversion can be completed. Delay line 34 is used to ensure that the first conversion is complete when the second conversion begins — i.e., that the correct subtraction occurs at summing node 49. Thus, the delay line imposes a speed limitation on the overall conversion process.

A further limitation is imposed by the need to use a delay line. The size of a video delay line is large enough to influence the overall size of a subranging converter. Typical video delay lines are 1 to 1-1/2 inches in their largest dimension. This limits such converters to board-level or hybrid packaging. A principal object of the invention, therefore, is to provide a high-speed, high-resolution analog-to-digital converter.

Another object of the invention is to provide a subranging A/D converter architecture which does not require a delay line.

Still another object of the invention is to provide a subranging converter architecture with a reduced complexity.

Yet another object is to provide a high-speed high resolution A/D converter suitable for monolithic fabrication.

Summary of the Invention

These and other objects are achieved in a subranging converter wherein the DAC is of the current-summing type which produces a current output. Conceptually, such an N-bit DAC consists of a set of 2ⁿ - 1 current sources and 2ⁿ - 1 switches. The switches are digitally controlled, with one control bit required for each switch. Each switch channels its associated current source output either to the common output summing node or to ground. In the present invention, each of the DAC switches, with the exception of the first switch, takes its control input directly from an associated one of the comparator outputs in the first stage flash A/D converter. This direct connection between the comparators and the DAC eliminates the need for a video delay line and provides a considerably faster conversion process.

These and other features and advantages of the present invention will become more readily apparent from the detailed description provided below, which should be read in conjunction with the accompanying drawing. The detailed description will be understood as exemplary only; the invention is limited only by the claims appended to the end thereto, and their equivalents.

Brief Description of the Drawing

In the drawing,

Fig. 1 is a block diagram of a typical prior art flash converter;

Fig. 2 is a functional block diagram of a conventional prior art two-stage flash converter with digitally corrected subranging;

Fig. 3 is a functonal block diagram of an analog-to-digital converter according to the present invention; and Fig. 4 is a partially-block, partially- simplified-schematic circuit diagram of the converter of Fig. 3.

Detailed Description

The architecture of the present invention is shown in Fig. 3. A track and hold amplifier 62 receives the analog input signal at terminal 64 and supplies sampled, or held, values to both a flash converter 66 and via resistor 68 to a summing node 70 at the input to an inverting amplifier 72. The flash converter 66 supplies P most significant bits of the digital output value, on bus 74. Flash converter 66 also directly drives tht input of a DAC 7& from the flash converter's comparator outputs '(not shown). The output of DAC 76 also drives summing node 70. A resistor 71 is connected between the output of amplifier 72 and the summing node 70, to provide feedback controlling the gain of that amplifier. Thus, the signal supplied by amplifier 70 represents the difference, or residue, between the value of rhe analog input signal and the value of the P most significant bits. Amplifier 70 scales this difference by a gain factor, causing the residue to span the full-scale range of a second analog-to-digital converter 78, which supplies a digital word of Q bits to represent the least significant bits of the output. The P bits from converter 66 and the Q bits from converter 78 are assembled together by a CMOS gate array 80 to provide a P + Q bit output. The connection between first flash converter 66 and DAC 76 is more fully illustrated in Fig. 4. As shown there, the first flash converter 66 more particularly comprises N = 2 - 1 comparators 16. through 16_N, a voltage divider 12 and an encoder 20. The voltage divider spans two reference voltages, labelled V-^p-^ and ^^, and in the illustration is formed by a series string of 2ⁿ - 1 identical resistors labelled R. through R... Each comparator provides a pair of complementary outputs which shall be identified as the uninverted and inverted outputs. The encoder 20 provides a binary word comprising the five most significant bits (MSB's) of the digital output. For purposes of this invention, the details of the encoder 20 are unimportant and any appropriate encoder may be used, several of which are known in the prior art.

The DAC 76 comprises a series of transistor switches, each formed of a pair of emitter-coupled transistors 80. and 82. whose bases are driven by the noninverted and inverted outputs, respectively, of a corresponding one of comparators 16.. The collectors of the switch transistors 80. , whose bases are driven by the inverted comparator outputs, are all connected to digital ground, while the collectors of the switch transistors 82., whose bases are driven by the noninverted comparator outputs, are connected in parallel to the output node 84 of the DAC. Each of coupled emitters of the transistor switches 80., 82. is connected to a current source, shown for simplicity as a single transistor 86. whose collector is connected to the coupled emitters and whose emitter is connected in series with a resistor 88. to supply voltage V_EE. Bias for the bases of transistors 86. is supplied by a single bias voltage applied at terminal 90. Each of the transistor switches can contribute the same amount of current to the output. The DAC 76 further includes a pair of emitter coupled transistors connected as a "dummy cell." The dummy cell is used in a feedback loop to control the bias voltage, V_glA_S' applied at terminal 90. The collector of transistor 92 is connected to one input of an operational amplifier, not shown, for sensing the collector current. The output of the operational amplifier generates the ^V _BIAS voltage to bias the current sources to a desired operating current. Deviations in collector current produce offsetting changes in V_BIAg, to servo the collector current to the intended value.

In practice, of course, the circuitry is likely to be somewhat more complex than appears from the functional diagrams. The functional diagrams do not show, for example, bias circuitry for the bases of the DAC switches. Also, the current sources on the emitters of the DAC switches are shown only figuratively. Further, though the details of-the circuit design of the comparators is not part of the invention, and many acceptable circuit designs appear in the prior art, it is preferable to use comparators which can change state only in response to a clock signal.

Having thus described the invention, various implementations, alterations, modifications, and improvements will readily occur to those skilled in the art to which this invention pertains. Accordingly, the foregoing description presents the invention by way of example only; that is, it is intended to be illustrative but not limiting. Such modifications, alterations, and improvements as will occur to those skilled in the art are, in fact, intended to be suggested hereby. Thus, the invention is limited only as required by the following claims and equivalents thereto.

What is claimed is:

Claims

1. For use in an analog-to-digital converter, a subassembly comprising:

an n-bit flash converter having

(a) 2 - 1 comparators, each comparator having inverted and non-inverted outputs, and

(b) encoding means for providing from the comparator outputs an n-bit binary word corresponding to the set of comparator outputs; and

2ⁿ - 1 electronic switches, each operable in response to the state of the outputs of an associated one of said comparators for connecting a current source to a current summing node at which an analog output current is provided.

2. The apparatus of claim 1 wherein each of the electronic switches has a first control input and a second control input, the first control input being connected to receive the non-inverted output of the associated comparator and the second control input being connected to receive the inverted output of the associated comparator.

3. An analog-to-digital converter comprising:

an n-bit flash converter having an input port for receiving an analog input voltage to be digitized and providing n-bit digital words corresponding to successive sample values of the analog input voltage;

the flash converter including 2ⁿ - l comparators, each providing an output;

a digital-to-analog converter (DAC) providing an analog output and having 2ⁿ - 1 inputs, each such input being connected to a respective one of the comparator outputs;

means for generating an m-bit digital word respresenting the value of the difference between the output of the DAC and the analog input voltage; and

means responsive to the m-bit digital word and the n-bit digital words for generating a digital word representing the amplitude of each analog sample value.