UST100501I4 - Integrated circuit layout utilizing separated active circuit and wiring regions - Google Patents
Integrated circuit layout utilizing separated active circuit and wiring regions Download PDFInfo
- Publication number
- UST100501I4 UST100501I4 US06/058,360 US5836079A UST100501I4 US T100501 I4 UST100501 I4 US T100501I4 US 5836079 A US5836079 A US 5836079A US T100501 I4 UST100501 I4 US T100501I4
- Authority
- US
- United States
- Prior art keywords
- insulating layer
- apertures
- sets
- exposed
- cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
- 238000000151 deposition Methods 0.000 abstract 2
- 238000003491 array Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11801—Masterslice integrated circuits using bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
In the method for fabricating a semiconductor substrate integrated circuit layout including: forming a plurality of spaced-apart circuit cells in columnar arrays within said substrate; forming a first insulating layer above said substrate, said layer having apertures therein to expose selected active regions of said selected cells; the improvement comprising: depositing first and second sets of elongated conductors in substantially parallel relationship atop said first insulating layer in said columnar direction; said first set being disposed directly atop said exposed cells to make selected contact with selected ones of said exposed active regions through said apertures in said first insulating layer; said second set being disposed in areas between said exposed cells; forming a second insulating layer above said first and second sets of conductors, said second insulating layer having apertures therein to expose selected ones of said first and second sets; and depositing a third set of substantially parallel, elongated conductors atop said second insulating layer, orthogonally with respect to said columnar direction, to make selected contact with said exposed ones of said first and second sets through said apertures in said second insulating layer.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US83071577A | 1977-09-06 | 1977-09-06 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US83071577A Continuation | 1977-09-06 | 1977-09-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
UST100501I4 true UST100501I4 (en) | 1981-04-07 |
Family
ID=25257547
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06/058,360 Pending UST100501I4 (en) | 1977-09-06 | 1979-07-17 | Integrated circuit layout utilizing separated active circuit and wiring regions |
Country Status (5)
Country | Link |
---|---|
US (1) | UST100501I4 (en) |
EP (1) | EP0001209A1 (en) |
JP (1) | JPS5441088A (en) |
CA (1) | CA1102009A (en) |
IT (1) | IT1110167B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10878158B2 (en) * | 2018-07-16 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4249193A (en) * | 1978-05-25 | 1981-02-03 | International Business Machines Corporation | LSI Semiconductor device and fabrication thereof |
JPS55138865A (en) * | 1979-04-17 | 1980-10-30 | Nec Corp | Semiconductor device |
JPS55163859A (en) * | 1979-06-07 | 1980-12-20 | Fujitsu Ltd | Manufacture of semiconductor device |
FR2524206B1 (en) * | 1982-03-26 | 1985-12-13 | Thomson Csf Mat Tel | PREDIFFUSED INTEGRATED CIRCUIT, AND METHOD FOR INTERCONNECTING CELLS OF THIS CIRCUIT |
JPH0758761B2 (en) * | 1983-12-30 | 1995-06-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Semiconductor integrated circuit chip |
US4737836A (en) * | 1983-12-30 | 1988-04-12 | International Business Machines Corporation | VLSI integrated circuit having parallel bonding areas |
DE3584102D1 (en) * | 1984-03-08 | 1991-10-24 | Toshiba Kawasaki Kk | INTEGRATED SEMICONDUCTOR CIRCUIT DEVICE. |
JPS6288337A (en) * | 1985-10-15 | 1987-04-22 | Nec Corp | Semiconductor integrated circuit device |
JP2685756B2 (en) * | 1987-07-20 | 1997-12-03 | 株式会社東芝 | Design method of semiconductor integrated circuit device |
JPH04340252A (en) * | 1990-07-27 | 1992-11-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit device, arrangement and wiring method of cell |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3808475A (en) * | 1972-07-10 | 1974-04-30 | Amdahl Corp | Lsi chip construction and method |
CA1024661A (en) * | 1974-06-26 | 1978-01-17 | International Business Machines Corporation | Wireable planar integrated circuit chip structure |
US4006492A (en) * | 1975-06-23 | 1977-02-01 | International Business Machines Corporation | High density semiconductor chip organization |
CA1091360A (en) * | 1975-12-29 | 1980-12-09 | Takao Uehara | Normalized interconnection patterns |
-
1978
- 1978-06-14 CA CA305,463A patent/CA1102009A/en not_active Expired
- 1978-07-25 JP JP9006178A patent/JPS5441088A/en active Pending
- 1978-08-16 EP EP78100654A patent/EP0001209A1/en not_active Withdrawn
- 1978-08-25 IT IT27013/78A patent/IT1110167B/en active
-
1979
- 1979-07-17 US US06/058,360 patent/UST100501I4/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10878158B2 (en) * | 2018-07-16 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same |
US11409937B2 (en) | 2018-07-16 | 2022-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same |
US11797746B2 (en) | 2018-07-16 | 2023-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor device having more similar cell densities in alternating rows |
Also Published As
Publication number | Publication date |
---|---|
IT7827013A0 (en) | 1978-08-25 |
JPS5441088A (en) | 1979-03-31 |
CA1102009A (en) | 1981-05-26 |
IT1110167B (en) | 1985-12-23 |
EP0001209A1 (en) | 1979-04-04 |
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