USRE46949E1 - Non-volatile semiconductor storage device - Google Patents
Non-volatile semiconductor storage device Download PDFInfo
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- USRE46949E1 USRE46949E1 US14/961,516 US201514961516A USRE46949E US RE46949 E1 USRE46949 E1 US RE46949E1 US 201514961516 A US201514961516 A US 201514961516A US RE46949 E USRE46949 E US RE46949E
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H01L27/11565—
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- H01L27/11578—
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- H01L27/11582—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Definitions
- the present invention relates to an electrically rewritable non-volatile semiconductor storage device.
- LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate.
- the dimension for each device must be reduced (refined) to increase memory storage capacity
- recent years are facing challenges in such refinement from the viewpoint of cost and technology.
- Such refinement requires further improvements in photolithography technology.
- ArF immersion lithography technology for example, the resolution limit has been reached around the 40 nm design rule and so EUV exposure devices have to be introduced for further refinement.
- the EUV exposure devices are expensive and infeasible in view of the costs.
- physical improvement limit such as in breakdown voltage between devices, would be reached unless driving voltage can be scaled. That is, it is likely that difficulties would be encountered in device operation itself.
- Patent Document 1 Japanese Patent Laid-Open No. 2007-266143
- Patent Document 2 U.S. Pat. No. 5,599,724
- Patent Document 3 U.S. Pat. No. 5,707,885
- One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with a cylinder-type structure (see, Patent Documents 1 to 3).
- Those semiconductor storage devices using transistors with the cylinder-type structure are provided with multiple laminated conductive layers corresponding to gate electrodes and pillar-like columnar semiconductors.
- Each of the columnar semiconductors serves as a channel (body) part of each of the transistors.
- Memory gate insulation layers that can accumulate electric charges are provided around the columnar semiconductors.
- Such a configuration including laminated conductive layers, columnar semiconductors, and memory gate insulation layers is referred to as a “memory string”.
- One aspect of the present invention provides a non-volatile semiconductor storage device comprising: a plurality of memory strings, each having a plurality of electrically rewritable memory cells connected in series; and a plurality of first selection transistors connected to one ends of the respective memory strings, each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround a side surface of the columnar portion as well as the first electric charge storage layer, the first conductive layer functioning as a control electrode of a respective one of the memory cells, each of the first selection transistors comprising: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround a side surface of the second semiconductor layer as well as the second electric charge storage layer, the second
- a non-volatile semiconductor storage device comprising: a plurality of memory strings, each having a plurality of electrically rewritable memory cells connected in series; and a plurality of first selection transistors connected to one ends of the respective memory strings, each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround a side surface of the columnar portion as well as the first electric charge storage layer, the first conductive layer functioning as a control electrode of a respective one of the memory cells, each of the first selection transistors comprising: a second semiconductor layer extending downward from a bottom surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround a side surface of the second semiconductor layer as well as the second electric charge storage layer, the second conductive
- FIG. 1 is a block diagram of a non-volatile semiconductor storage device 100 according to a first embodiment of the present invention
- FIG. 2 is a schematic perspective view of a memory cell array 11 ;
- FIG. 3 is an enlarged view of FIG. 2 ;
- FIG. 4 is a cross-sectional view of FIG. 3 ;
- FIG. 5 is a circuit diagram of the non-volatile semiconductor storage device 100 ;
- FIG. 6 is a timing chart illustrating a write operation of the non-volatile semiconductor storage device 100 according to the first embodiment
- FIG. 7 is a timing chart illustrating a read operation of the non-volatile semiconductor storage device 100 according to the first embodiment
- FIG. 8 is a timing chart illustrating an erase operation of the non-volatile semiconductor storage device 100 according to the first embodiment
- FIG. 9 is a flowchart illustrating an operation to be performed before and after the read operation in the non-volatile semiconductor storage device 100 according to the first embodiment
- FIG. 10 illustrates “Case 1 ” of the pre-programming at step S 101 ;
- FIG. 11 illustrates “Case 2 ” of the pre-programming at step S 101 ;
- FIG. 12 illustrates “Case 3 ” of the pre-programming at step S 101 ;
- FIG. 13 is a timing chart illustrating the pre-programming operation (step S 101 );
- FIG. 14 is a timing chart illustrating the pre-programming erase operation (step S 103 );
- FIG. 15 is a cross-sectional view of one memory block MBa according to a second embodiment
- FIG. 16 is a flowchart illustrating an operation to be performed before and after the read operation in the non-volatile semiconductor storage device according to the second embodiment
- FIG. 17 illustrates “Case 4 ” of the pre-programming at step S 201 ;
- FIG. 18 illustrates “Case 5 ” of the pre-programming at step S 201 ;
- FIG. 19 illustrates “Case 6 ” of the pre-programming at step S 201 ;
- FIG. 20 is a timing chart illustrating the pre-programming operation (step S 201 );
- FIG. 21 is a timing chart illustrating the pre-programming erase operation (step S 203 );
- FIG. 22 is a cross-sectional view of one memory block MBb according to the third embodiment.
- FIG. 23 is a circuit diagram of memory blocks MBc in a non-volatile semiconductor storage device according to a fourth embodiment
- FIG. 24 is a schematic perspective view of one memory block MBc in the non-volatile semiconductor storage device of the fourth embodiment.
- FIG. 25 is an enlarged cross-sectional view of a part of FIG. 24 .
- FIG. 1 is a block diagram of the non-volatile semiconductor storage device 100 according to the first embodiment of the present invention.
- the non-volatile semiconductor storage device 100 of the first embodiment comprises: a memory cell array 11 ; row decoders 12 and 13 ; a sense amplifier 14 ; a column decoder 15 ; and a control signal generation unit (high-voltage generation unit) 16 .
- the memory cell array 11 has memory transistors MTr for electrically storing data.
- the row decoders 12 and 13 decode captured block address signals and gate address signals.
- the row decoders 12 and 13 also control the memory cell array 11 .
- the sense amplifier 14 reads data from the memory cell array 11 .
- the column decoder 15 decodes column address signals and controls the sense amplifier 14 .
- the control signal generation unit 16 boosts a reference voltage to generate a high voltage that is required at the time of write and erase operations. Furthermore, The control signal generation unit 16 generates a control signal to control the row decoders 12 and 13 , the sense amplifier 14 , and the column decoder 15 .
- FIG. 2 is a schematic perspective view of a memory cell array 11 .
- FIG. 3 is an enlarged view of FIG. 2 .
- FIG. 4 is a cross-sectional view of FIG. 3 .
- the row direction represents a direction orthogonal to the lamination direction and the column direction represents another orthogonal to the lamination direction and the row direction. Note that interlayer insulation layers provided between wirings are omitted from FIG. 3 .
- the memory cell array 11 has a plurality of memory blocks MB.
- the memory blocks MB are arranged in the column direction on a semiconductor substrate Ba (not illustrated). In other words, one memory block MB is formed for each certain region on the semiconductor substrate Ba.
- each memory block MB comprises a plurality of memory strings MS, source-side selection transistors SSTr, and drain-side selection transistors SDTr.
- Each memory string MS includes memory transistors MTr 1 to MTr 4 connected in series.
- Each drain-side selection transistor SDTr is connected to one end (a memory transistor MTr 4 ) of a respective memory string MS.
- Each source-side selection transistor SSTr is connected to the other end (a memory transistor MTr 1 ) of a respective memory string MS.
- each memory block MB has multiple rows and four columns of memory strings MS provided therein.
- each memory string MS may include four or more memory transistors.
- four or more columns of memory strings MS may be provided in each memory block MB.
- each memory block MB the control gates of the memory transistors MTr 1 arranged in a matrix form are commonly connected to a word line WL 1 .
- the control gates of the memory transistors MTr 2 are commonly connected to a word line WL 2 .
- the control gates of the memory transistors MTr 3 are commonly connected to a word line WL 3 .
- the control gates of the memory transistors MTr 4 are commonly connected to a word line WL 4 .
- the word lines WL 1 to WL 4 are controlled by independent signals.
- each memory block MB the control gates of the drain-side selection transistors SDTr arranged in the row direction are commonly connected to a drain-side selection gate line SGD.
- Each drain-side selection gate line SGD is formed to extend in the row direction across a plurality of memory blocks MB.
- a plurality of drain-side selection gate lines SGD, which are provided in the column direction, are controlled by independent signals.
- the other ends of the drain-side selection transistors SDTr arranged in the column direction are commonly connected to a bit line BL.
- Each bit line BL is formed to extend in the column direction across the memory blocks MB.
- a plurality of bit lines BL which are provided in the row direction, are controlled by independent signals.
- each memory block MB the control gates of the source-side selection transistors SSTr arranged in the row direction are commonly connected to a source-side selection gate line SGS.
- Each source-side selection gate line SGS is formed to extend in the row direction across a plurality of memory blocks MB.
- a plurality of source-side selection gate lines SGS, which are provided in the column direction, are controlled by independent signals.
- the other ends of the source-side selection transistors SSTr arranged in the column direction are commonly connected to a source line SL.
- Each memory block MB has a source-side selection transistor layer 20 , a memory transistor layer 30 , and a drain-side selection transistor layer 40 that are sequentially laminated on the semiconductor substrate Ba.
- the source-side selection transistor layer 20 is a layer that functions as source-side selection transistors SSTr.
- the memory transistor layer 30 is a layer that functions as memory strings MS (memory transistors MTr 1 to MTr 4 ).
- the drain-side selection transistor layer 40 is a layer that functions as drain-side selection transistors SDTr.
- the source-side selection transistor layer 20 has source-side first insulation layers 21 , source-side conductive layers 22 , and source-side second insulation layers 23 that are sequentially formed on the semiconductor substrate Ba.
- Each source-side conductive layer 22 is formed to extend in the row direction.
- an interlayer insulation layer 24 is formed on the sidewall of each source-side conductive layer 22 .
- the source-side first insulation layers 21 and the source-side second insulation layers 23 are composed of, e.g., silicon oxide (SiO 2 ) or silicon nitride (SiN).
- the source-side conductive layers 22 are composed of, e.g., polysilicon (p-Si).
- the source-side selection transistor layer 20 also has source-side holes 25 that are formed to penetrate the source-side first insulation layers 21 , the source-side conductive layers 22 , and the source-side second insulation layers 23 .
- the source-side holes 25 are formed in a matrix form in the row and column directions.
- the source-side selection transistor layer 20 has source-side gate insulation layers 26 and source-side columnar semiconductor layers 27 that are sequentially formed on the sidewalls of the source-side holes 25 .
- the source-side gate insulation layers 26 are formed with a certain thickness on the sidewalls of the source-side holes 25 .
- the source-side columnar semiconductor layers 27 are formed to fill up the source-side holes 25 .
- Each source-side columnar semiconductor layer 27 is formed in a columnar shape extending in the lamination direction.
- the top surfaces of the source-side columnar semiconductor layers 27 are formed in contact with the bottom surfaces of respective memory columnar semiconductor layers 35 described below.
- the source-side columnar semiconductor layers 27 are formed on a diffusion layer Ba 1 on the semiconductor substrate Ba.
- the diffusion layer Ba 1 functions as a source line SL.
- the source-side gate insulation layers 26 are composed of, e.g., silicon oxide (SiO 2 ).
- the source-side columnar semiconductor layers 27 are composed of, e.g., polysilicon (p-Si).
- the source-side conductive layers 22 function as the control gates of the source-side selection transistors SSTr.
- the source-side conductive layers 22 also function as source-side selection gate lines SGS.
- the memory transistor layer 30 has first to fifth insulation layers between word lines 31 a to 31 e and first to fourth word-line conductive layers 32 a to 32 d that are sequentially laminated on the source-side selection transistor layer 20 .
- the first to fourth word-line conductive layers 32 a to 32 d are formed to expand in a two-dimensional manner (in a plate-like form) in the row and column directions.
- the first to fourth word-line conductive layers 32 a to 32 d are separated for each memory block MB.
- the first to fifth insulation layers between word lines 31 a to 31 e are composed of, e.g., silicon oxide (SiO 2 ).
- the first to fourth word-line conductive layers 32 a to 32 d are composed of, e.g., polysilicon (p-Si).
- the memory transistor layer 30 also has memory holes 33 that are formed to penetrate the first to fifth insulation layers between word lines 31 a to 31 e and the first to fourth word-line conductive layers 32 a to 32 d.
- the memory holes 33 are formed in a matrix form in the row and column directions.
- the memory holes 33 are formed at positions matching the source-side holes 25 .
- the memory transistor layer 30 has block insulation layers 34 a, electric charge storage layers 34 b, tunnel insulation layers 34 c, and memory columnar semiconductor layers 35 that are sequentially formed on the sidewalls of the memory holes 33 .
- the block insulation layers 34 a are formed with a certain thickness on the sidewalls of the memory holes 33 .
- the electric charge storage layers 34 b are formed with a certain thickness on the sidewalls of the block insulation layers 34 a.
- the tunnel insulation layers 34 c are formed with a certain thickness on the sidewalls of the electric charge storage layers 34 b.
- the memory columnar semiconductor layers 35 are formed to fill up the memory holes 33 .
- Each memory columnar semiconductor layer 35 is formed in a columnar shape extending in the lamination direction.
- the bottom surfaces of the memory columnar semiconductor layers 35 are formed in contact with the top surfaces of the respective source-side columnar semiconductor layers 27 .
- the top surfaces of the memory columnar semiconductor layers 35 are formed in contact with the bottom surfaces of respective drain-side columnar semiconductor layers 47 described below.
- the block insulation layers 34 a and the tunnel insulation layers 34 c are composed of, e.g., silicon oxide (SiO 2 ).
- the electric charge storage layers 34 b are composed of, e.g., silicon nitride (SiN).
- the memory columnar semiconductor layers 35 are composed of, e.g., polysilicon (p-Si).
- the first to fourth word-line conductive layers 32 a to 32 d function as the control gates of the memory transistors MTr 1 to MTr 4 .
- the first to fourth word-line conductive layers 32 a to 32 d also function as parts of the word lines WL 1 to WL 4 .
- the drain-side selection transistor layer 40 has drain-side first insulation layers 41 , drain-side conductive layers 42 , and drain-side second insulation layers 43 that are sequentially laminated on the memory transistor layer 30 .
- the drain-side conductive layers are formed immediately above where the memory columnar semiconductor layers 35 are formed.
- the drain-side conductive layers 42 are formed to extend in the row direction. Note that interlayer insulation layers 44 are formed on the sidewalls of the drain-side conductive layers 42 .
- the drain-side first insulation layers 41 and the drain-side second insulation layers 43 are composed of, e.g., silicon oxide (SiO 2 ) or silicon nitride (SiN).
- the drain-side conductive layers 42 are composed of, e.g., polysilicon (p-Si).
- the drain-side selection transistor layer 40 also has drain-side holes 45 that are formed to penetrate the drain-side first insulation layers 41 , the drain-side conductive layers 42 , and the drain-side second insulation layers 43 .
- the drain-side holes 45 are formed in a matrix form in the row and column directions.
- the drain-side holes 45 are formed at positions matching the memory holes 33 .
- the drain-side selection transistor layer 40 has block insulation layers 46 a, electric charge storage layers 46 b, tunnel insulation layers 46 c, and the drain-side columnar semiconductor layers 47 that are sequentially formed on the sidewalls of the drain-side holes 45 .
- the block insulation layers 46 a are formed with a certain thickness on the sidewalls of the drain-side holes 45 .
- the electric charge storage layers 46 b are formed with a certain thickness on the sidewalls of the block insulation layers 46 a.
- the tunnel insulation layers 46 c are formed with a certain thickness on the sidewalls of the electric charge storage layers 46 b.
- the drain-side columnar semiconductor layers 47 are formed to fill up the drain-side holes 45 .
- Each drain-side columnar semiconductor layer 47 is formed in a columnar shape extending in the lamination direction.
- the bottom surfaces of the drain-side columnar semiconductor layers 47 are formed in contact with the top surfaces of the memory columnar semiconductor layers 35 .
- Bit line layers 51 are formed on the top surfaces of the drain-side columnar semiconductor layers 47 .
- the bit line layers 51 are formed to extend in the column direction at a certain pitch in the row direction.
- the bit line layers 51 function as bit lines BL.
- the block insulation layers 46 a and the tunnel insulation layers 46 c are composed of, e.g., silicon oxide (SiO 2 ).
- the electric charge storage layers 46 b are composed of, e.g., silicon nitride (SiN).
- the drain-side columnar semiconductor layers 47 are composed of, e.g., polysilicon (p-Si).
- the drain-side conductive layers 42 function as the control gates of the drain-side selection transistors SDTr.
- the drain-side conductive layers 42 also function as parts of drain-side selection gate lines SGD.
- FIG. 5 is a circuit diagram of the non-volatile semiconductor storage device 100 .
- a row decoder 12 has a NAND circuit 121 , a NOT circuit 122 , and a voltage conversion circuit 123 for each memory block MB.
- Each NAND circuit 121 receives an address signal Address from the control signal generation unit 16 and outputs it to the NOT circuit 122 .
- the NOT circuit 122 receives the signal from the NAND circuit 121 and outputs it to the voltage conversion circuit 123 .
- the voltage conversion circuit 123 converts the voltage of the signal received from the NOT circuit 122 , and then outputs the converted signal to a control gate of a first transfer transistor 124 a described below.
- the row decoder 12 also has a pair of first and second transfer transistors 124 a and 124 b for memory strings MS connected to the same drain-side selection gate line SGD.
- One end of the first transfer transistor 124 a receives a signal Sg SGD from the control signal generation unit 16 .
- the signal Sg SGD is a signal for driving a particular drain-side selection gate line SGD.
- the other end of each first transfer transistor 124 a is connected to a drain-side selection gate line SGD.
- the control gate of each first transfer transistor 124 a receives a signal from the voltage conversion circuit 123 .
- each second transfer transistor 124 b receives a signal Sg SGDOFF from the control signal generation unit 16 .
- the signal Sg SGDOFF is a signal for disabling a drain-side selection gate line SGD.
- the other end of each second transfer transistor 124 b is connected to a drain-side selection gate line SGD.
- the control gate of each second transfer transistor 124 b receives a signal from the NAND circuit 121 .
- the row decoder 12 also has third and fourth transfer transistors 124 c and 124 d for each memory block MB.
- One ends of the third and fourth transfer transistors 124 c and 124 d receive signals Sg WL3 and Sg WL4 , respectively, from the control signal generation unit 16 .
- the signals Sg WL3 and Sg WL4 are signals for driving the word lines WL 3 and WL 4 .
- the other ends of the third and fourth transfer transistors 124 c and 124 d are connected to the word lines WL 3 and WL 4 .
- the control gates of the third and fourth transfer transistors 124 c and 124 d receive signals from the voltage conversion circuit 123 .
- a row decoder 13 has a NAND circuit 131 , a NOT circuit 132 , and a voltage conversion circuit 133 for each memory block MB.
- Each NAND circuit 131 receives an address signal Address from the control signal generation unit 16 and outputs it to the NOT circuit 132 .
- the NOT circuit 132 receives a signal from the NAND circuit 131 and outputs it to the voltage conversion circuit 133 .
- the voltage conversion circuit 133 converts the voltage of the signal received from the NOT circuit 132 , and then outputs the converted signal to a control gate of a first transfer transistor 134 a described below.
- the row decoder 13 also has pair of first and second transfer transistors 134 a and 134 b for memory strings MS connected to the same source-side selection gate line SGS.
- One end of the first transfer transistor 134 a receives a signal Sg SGS from the control signal generation unit 16 .
- the signal Sg SGS is a signal for driving a particular source-side selection gate line SGS.
- the other end of each first transfer transistor 134 a is connected to a source-side selection gate line SGS.
- the control gate of each first transfer transistor 134 a receives a signal from the voltage conversion circuit 133 .
- each second transfer transistor 134 b receives a signal Sg SGSOFF from the control signal generation unit 16 .
- the signal Sg SGSOFF is a signal for disabling a source-side selection gate line SGS.
- the other end of each second transfer transistor 134 b is connected to a source-side selection gate line SGS.
- the control gate of each second transfer transistor 134 b receives a signal from the NAND circuit 131 .
- the row decoder 13 also has third and fourth transfer transistors 134 c and 134 d for each memory block MB.
- One ends of the third and fourth transfer transistors 134 c and 134 d receive signals Sg WL1 and Sg WL2 , respectively, from the control signal generation unit 16 .
- the signals Sg WL1 and Sg WL2 are signals for driving the word lines WL 1 and WL 2 .
- the other ends of the third and fourth transfer transistors 134 c and 134 d are connected to the word lines WL 1 and WL 2 .
- the control gates of the third and fourth transfer transistors 134 c and 134 d receive signals from the voltage conversion circuit 133 .
- FIGS. 6 to 8 write, read, and erase operations of the non-volatile semiconductor storage device 100 of the first embodiment will be described below.
- the operations illustrated in FIGS. 6 to 8 are performed by the control signal generation unit 16 .
- FIG. 6 is a timing chart illustrating a write operation of the non-volatile semiconductor storage device 100 according to the first embodiment
- FIG. 7 is a timing chart illustrating a read operation thereof
- FIG. 8 is a timing chart illustrating an erase operation thereof.
- the word lines WL 1 to WL 4 are denoted by “word lines WL”.
- One of the word lines WL 1 to WL 4 that is selected for write, read, or erase operations is denoted by a “selected word line WL (sel)”.
- one of the word lines WL 1 to WL 4 that is not selected for such operations is denoted by an “unselected word line WL (n-sel)”.
- One of the drain-side selection gate lines SGD that is selected for write, read, or erase operations is denoted by a “selected drain-side selection gate line SGD (sel)”.
- drain-side selection gate lines SGD that is not selected for such operations is denoted by an “unselected drain-side selection gate line SGD (n-sel)”.
- One of the source-side selection gate lines SGS that is selected for write, read, or erase operations is denoted by a “selected source-side selection gate line SGS (sel)”.
- one of the source-side selection gate lines SGS that is not selected for such operations is denoted by an “unselected source-side selection gate line SGS (n-sel)”.
- one of the memory blocks MB that is selected for write, read, or erase operations is denoted by a “selected memory block MB (sel)”.
- one of the memory blocks MB that is not selected for such operations is denoted by an “unselected memory block MB (n-sel)”.
- One of the memory strings MS that is selected for write, read, or erase operations is denoted by a “selected memory string MS (sel)”.
- one of the memory strings MS that is not selected for such operations is denoted by an “unselected memory string MS (n-sel)”.
- One of the drain-side selection transistors SDTr that is selected for write, read, or erase operations is denoted by a “selected drain-side selection transistor SDTr (sel)”. Meanwhile, one of the drain-side selection transistors SDTr that is not selected for such operations is denoted by an “unselected drain-side selection transistor SDTr (n-sel)”.
- One of the source-side selection transistors SSTr that is selected for write, read, or erase operations is denoted by a “selected source-side selection transistor SSTr (sel)”. In contrast, one of the source-side selection transistors SSTr that is not selected for such operations is denoted by an “unselected source-side selection transistor SSTr (n-sel)”.
- the source line SL is initially set at a voltage Vdd, while the others set at a ground voltage Vss. Then, in writing “1” at time t 11 , the bit line BL is boosted to the voltage Vdd. Alternatively, in writing “0” at time t 11 , the bit line BL is maintained at the ground voltage Vss. In addition, at time t 11 , a selected word line WL (sel) and unselected word lines WL (n-sel) are boosted to the voltage Vdd. Furthermore, at time tll, a selected drain-side selection gate line SGD (sel) is boosted to a voltage Vsg.
- the voltage Vdd is, e.g., on the order of 3V to 4V.
- the voltage Vsg is, e.g., on the order of 4V.
- unselected drain-side selection gate lines SGD (n-sel) and unselected source-side selection gate lines SGS (n-sel) are set at the ground voltage Vss.
- the word lines WL in unselected blocks MB (n-sel) are set in a floating state.
- the selected drain-side selection gate line SGD (sel) is dropped to the voltage Vdd.
- the selected word line WL (sel) and the unselected word lines WL (n-sel) are boosted to a voltage Vpass.
- the selected word line WL (sel) is boosted to a voltage Vpgm.
- the voltage Vpass is, e.g., 10V.
- the voltage Vpgm is, e.g., 18V.
- the selected word line WL (sel), the unselected word lines WL (n-sel), and the selected drain-side selection gate line SGD (sel) are dropped to the ground voltage Vss.
- the bit line BL, the source line SL, the selected word line WL (sel), the unselected word lines (n-sel), the selected drain-side selection gate line SGD (sel), and the selected source-side selection gate line SGS (sel) are initially set at the ground voltage Vss.
- the unselected drain-side selection gate lines SGD (n-sel) and the unselected source-side selection gate lines SGS (n-sel) are set at the ground voltage Vss.
- Each word line WL in an unselected memory block MB (n-sel) is set in a floating state.
- the bit line BL is boosted to a voltage Vpre.
- the voltage Vpre is, e.g., on the order of 1V.
- the unselected word lines WL are boosted to a voltage Vread.
- the voltage Vread is, e.g., on the order of 4V.
- the selected drain-side selection gate line SGD is boosted to the voltage Vsg.
- the selected source-side selection gate line SGS is boosted to the voltage Vsg.
- the source line SL, the word line WL, the selected drain-side selection gate line SGD (sel), and the selected source-side selection gate line SGS (sel) are initially set at the ground voltage Vss.
- the bit line BL is set in a floating state.
- the unselected drain-side selection gate lines SGD (n-sel) and the unselected source-side selection gate lines SGS (n-sel) are set in a floating state.
- each word line WL in the unselected block MB (n-sel) is set in a floating state.
- the source line SL is boosted to a voltage Vera.
- the selected drain-side selection gate line SGD (sel) and the selected source-side selection gate line SGS (sel) are boosted to a voltage Verasg.
- the voltage Vera is on the order of 20V.
- the voltage Verasg is on the order of 15V.
- the source line SL is dropped to the ground voltage Vss.
- the selected drain-side selection gate line SGD (sel) and the selected source-side selection gate line SGS (sel) are dropped to the ground voltage Vss.
- GIDL Gate Induced Drain Leak
- FIG. 9 is a flowchart illustrating an operation to be performed before and after the read operation of the non-volatile semiconductor storage device 100 of the first embodiment.
- pre-programming is first performed on the unselected drain-side selection transistor SDTr (n-sel) that is connected to an unselected memory string MS (n-sel) (step S 101 ).
- the pre-programming is performed by accumulating electric charges in an electric charge storage layer 46 b of the drain-side selection transistor layer 40 . This pre-programming increases the threshold voltage of the drain-side selection transistor SDTr.
- step S 102 data is read from the memory transistors MTr 1 to MTr 4 in the selected memory string MS (sel) (step S 102 ).
- the pre-programming of the unselected drain-side selection transistor SDTr (n-sel) connected to the unselected memory string MS (n-sel) is erased (step S 103 ).
- the pre-programming erase is performed by discharging electric charges from the electric charge storage layer 46 b of the drain-side selection transistor layer 40 . This pre-programming erase decreases the threshold voltage of the drain-side selection transistor SDTr.
- the above-mentioned pre-programming at step S 101 is performed on unselected drain-side selection transistors SDTr (n-sel) that are connected to unselected memory strings MS (n-sel) in an unselected memory block MB (n-sel), as illustrated in “Case 1 ” of FIG. 10 .
- the pre-programming is also performed on unselected drain-side selection transistors SDTr (n-sel) that are connected to unselected memory strings MS (n-sel) in a selected memory block MB (sel).
- the above-mentioned pre-programming at step S 101 is only performed on unselected drain-side selection transistors SDTr (n-sel) that are connected to unselected memory strings MS (n-sel) in a selected memory block MB (sel).
- the above-mentioned pre-programming at step S 101 is only performed on unselected drain-side selection transistors SDTr (n-sel) in an unselected memory block MB (n-sel).
- FIG. 13 is a timing chart illustrating the pre-programming operation.
- one of the drain-side selection gate lines SGD that is subject to the pre-programming operation is hereinafter denoted by a “target drain-side selection gate line SGD (tar)”.
- One of the drain-side selection gate lines SGD that is not subject to the pre-programming operation is denoted by a “non-target drain-side selection gate line SGD (n-tar)”.
- one of the source-side selection gate lines SGS that is subject to the pre-programming operation is denoted by a “target source-side selection gate line SGS (tar)”.
- One of the source-side selection gate lines SGS that is not subject to the pre-programming operation is denoted by a “non-target source-side selection gate line SGS (n-tar)”.
- drain-side selection transistors SDTr unlike the word lines WL 1 to WL 4 , data cannot be selectively written to a plurality of drain-side selection transistors SDTr that are connected to a selected drain-side selection gate line SGD (sel). Thus, “0” data is collectively written to all of the drain-side selection transistors SDTr. As such, all of the bit lines BL are set at the ground voltage Vss.
- a bit line BL, a source line SL, a word line WL, a target drain-side selection gate line SGD (tar), a non-target drain-side selection gate line SGD (n-tar), and a source-side selection gate line SGS are initially set at the ground voltage Vss. Then, at time t 41 , the target drain-side selection gate line SGD (tar) is boosted to the voltage Vdd. Then, at time t 42 , the target drain-side selection gate line SGD (tar) is boosted to the voltage Vpass. Subsequently, at time t 43 , the target drain-side selection gate line SGD (tar) is boosted to the voltage Vpgm.
- the target drain-side selection gate line SGD (tar) is dropped to the ground voltage Vss. Meanwhile, the above-mentioned operation is restated as follows: the target drain-side selection gate line SGD (tar) is boosted in a step-like manner.
- FIG. 14 is a timing chart illustrating the pre-programming erase operation.
- the source line SL, the target source-side selection gate line SGS (tar), the target drain-side selection gate line SGD (tar), and the non-target drain-side selection gate line SGD (n-tar) are initially set at the ground voltage Vss.
- the word lines WL are set in a floating state.
- Each word line WL and non-target source-side selection gate line SGS (n-tar) in an unselected block MB (n-sel) are set in a floating state.
- the source line SL is boosted to the voltage Vera.
- the target source-side selection gate line SGS (tar)
- the target drain-side selection gate line SGD (tar)
- the non-target drain-side selection gate line SGD (n-tar) are boosted to the voltage Verasg.
- the target drain-side selection gate line SGD (tar) is dropped to the ground voltage Vss.
- the source line SL, the target source-side selection gate line SGS (tar), and the non-target drain-side selection gate line SGD (n-tar) are dropped to the ground voltage Vss.
- GIDL Gate Induced Drain Leak
- the non-volatile semiconductor storage device 100 of the first embodiment may achieve high integration.
- each layer corresponding to respective memory transistors MTr, source-side selection transistors SSTr, and drain-side selection transistors SDTr may be manufactured in a certain number of lithography steps, irrespective of the number of laminated layers. That is, the non-volatile semiconductor storage device 100 may be manufactured at a lower cost.
- the non-volatile semiconductor storage device 100 is configured to be able to control the threshold voltages of the drain-side selection transistors SDTr. Accordingly, prior to reading data, the non-volatile semiconductor storage device 100 may control the threshold voltage to be a high value for an unselected drain-side selection transistor SDTr (n-sel) connected to an unselected memory string MS (n-sel). Therefore, when reading data, the non-volatile semiconductor storage device 100 may suppress the leakage current that would flow from a bit line BL to a source line SL through an unselected memory string MS (n-sel). That is, the non-volatile semiconductor storage device 100 allows for more accurate read operation.
- FIG. 15 is a cross-sectional view of one memory block MBa according to the second embodiment. Note that the same reference numerals represent the same components as the first embodiment, and description thereof will be omitted in the second embodiment.
- the non-volatile semiconductor storage device has memory blocks MBa different from the first embodiment.
- Each memory block MBa has a source-side selection transistor layer 20 A and a drain-side selection transistor layer 40 A that are different from the first embodiment.
- the source-side selection transistor layer 20 A has block insulation layers 26 a, electric charge storage layers 26 b, and tunnel insulation layers 26 c, instead of the source-side gate insulation layers 26 .
- the block insulation layers 26 a are formed with a certain thickness on the sidewalls of the source-side holes 25 .
- the electric charge storage layers 26 b are formed with a certain thickness on the sidewalls of the block insulation layers 26 a.
- the tunnel insulation layers 26 c are formed with a certain thickness on the sidewalls of the electric charge storage layers 26 b.
- the block insulation layers 26 a and the tunnel insulation layers 26 c are composed of, e.g., silicon oxide (SiO 2 ).
- the electric charge storage layers 26 b are composed of, e.g., silicon nitride (SiN).
- the drain-side selection transistor layer 40 A has drain-side gate insulation layers 46 , instead of the block insulation layers 46 a, the electric charge storage layers 46 b, and the tunnel insulation layers 46 c.
- the drain-side gate insulation layers 46 are formed with a certain thickness on the sidewalls of the drain-side holes 45 .
- the drain-side gate insulation layers 46 are composed of, e.g., silicon oxide (SiO 2 ).
- FIG. 16 is a flowchart illustrating an operation to be performed before and after the read operation of the non-volatile semiconductor storage device according to the second embodiment.
- pre-programming is first performed on an unselected source-side selection transistor SSTr (n-sel) that is connected to an unselected memory string MS (n-sel) (step S 201 ).
- the pre-programming is performed by accumulating electric charges in an electric charge storage layer 26 b of the source-side selection transistor layer 20 A.
- the pre-programming increases the threshold voltage of the unselected source-side selection transistor SSTr (n-sel).
- step S 202 data is read from the memory transistors MTr 1 to MTr 4 in the selected memory string (sel) (step S 202 ).
- the pre-programming of the unselected source-side selection transistor SSTr (n-sel) connected to the unselected memory string (n-sel) is erased (step S 203 ).
- the pre-programming erase is performed by discharging electric charges from the electric charge storage layer 26 b of the source-side selection transistor layer 20 . This pre-programming erase decreases the threshold voltage of the unselected source-side selection transistor SSTr (n-sel).
- the above-mentioned pre-programming at step S 201 is performed on unselected drain-side selection transistors SDTr (n-sel) that are connected to unselected memory strings MS (n-sel) in an unselected memory block MB (n-sel), as illustrated in “Case 4 ” of FIG. 17 .
- the pre-programming is also performed on unselected drain-side selection transistors SDTr (n-sel) that are connected to unselected memory strings MS (n-sel) in a selected memory block MB (sel).
- the above-mentioned pre-programming at step S 201 is only performed on unselected drain-side selection transistors SDTr (n-sel) that are connected to unselected memory strings MS (n-sel) in a selected memory block MB (sel).
- the above-mentioned pre-programming at step S 201 is only performed on unselected drain-side selection transistors SDTr (n-sel) in an unselected memory block MB (n-sel).
- FIG. 20 is a timing chart illustrating the pre-programming operation.
- all lines are initially set at the ground voltage Vss. Firstly, at time t 61 , the target source-side selection gate line SGS (tar) is boosted to the voltage Vdd. Then, at time t 62 , the target source-side selection gate line SGS (tar) is boosted to the voltage Vpass. Subsequently, at time t 63 , the target source-side selection gate line SGS (tar) is boosted to the voltage Vpgm. Thereafter, at time t 64 , the target source-side selection gate line SGS (tar) is dropped to the ground voltage Vss. Note that the above-mentioned operation is restated as follows: the target source-side selection gate line SGS (tar) is boosted in a step-like manner.
- FIG. 21 is a timing chart illustrating the pre-programming erase operation.
- the source line SL, the target source-side selection gate line SGS (tar), the non-target source-side selection gate line SGS (n-tar), and the target drain-side selection gate line SGD (tar) are initially set at the ground voltage Vss.
- the word line WL is set in a floating state.
- the non-target drain-side selection gate line SGD (n-tar) is set in a floating state.
- the source line SL is boosted to the voltage Vera.
- the target drain-side selection gate line SGD (tar), the non-target source-side selection gate line SGS (n-tar), and the target source-side selection gate line SGS (tar) are boosted to the voltage Verasg.
- the target source-side selection gate line SGS (tar) is dropped to the ground voltage Vss.
- the source line SL, the non-target source-side selection gate line SGS (n-tar), and the target drain-side selection gate line SGD (tar) are dropped to the ground voltage Vss.
- GIDL Gate Induced Drain Leak
- the non-volatile semiconductor storage device according to the second embodiment is configured to be able to control the threshold voltages of the source-side selection transistors SSTr. Accordingly, prior to reading data, the non-volatile semiconductor storage device may control the threshold voltage to be a high value for an unselected source-side selection transistor SSTr (n-sel) connected to an unselected memory string MS (n-sel). Therefore, the non-volatile semiconductor storage device may suppress the leakage current that would flow from a bit line BL to a source line SL through an unselected memory string MS (n-sel). That is, as in the first embodiment, the non-volatile semiconductor storage device according to the second embodiment allows for more accurate read operation.
- FIG. 22 is a cross-sectional view of one memory block MBb according to the third embodiment. Note that the same reference numerals represent the same components as the first and second embodiments, and description thereof will be omitted in the third embodiment.
- the non-volatile semiconductor storage device of the third embodiment has memory blocks MBb different from the first embodiment.
- Each memory block MBb has the source-side selection transistor layer 20 A, the memory transistor layer 30 , and the drain-side selection transistor layer 40 as described in the first and second embodiments.
- control signal generation unit 16 performs operations as illustrated in FIG. 9 according to the first embodiment (step S 101 to 5103 ) and in FIG. 16 according to the second embodiment (step S 201 to S 203 ).
- the non-volatile semiconductor storage device of the third embodiment has the characteristics according to the first and second embodiments. Accordingly, the non-volatile semiconductor storage device of the third embodiment has the same advantages as the first and second embodiments.
- FIG. 23 is a circuit diagram of memory blocks MBc in the non-volatile semiconductor storage device of the fourth embodiment.
- FIG. 24 is a schematic perspective view of one memory block MBc.
- FIG. 25 is an enlarged cross-sectional view illustrating a part of FIG. 24 . Note that the same reference numerals represent the same components as the first to third embodiments, and description thereof will be omitted in the fourth embodiment.
- each memory block MBc comprises a plurality of memory strings MSb, source-side selection transistors SSTrb, and drain-side selection transistors SDTrb.
- Each memory string MSb includes memory transistors MTrb 1 to MTrb 8 connected in series and a back gate transistor BTr.
- Each back gate transistor BTr is connected between a memory transistor MTrb 4 and a memory transistor MTrb 5 .
- Each drain-side selection transistor SDTrb is connected to one end (a memory transistor MTrb 8 ) of a memory string MSb.
- Each source-side selection transistor SSTrb is connected to the other end (a memory transistor MTrb 1 ) of a memory string MSb.
- each memory block MBc the control gates of the memory transistors MTrb 1 arranged in the row direction are commonly connected to a word line WLb 1 .
- the control gates of the memory transistors MTrb 2 to MTrb 8 arranged in the row direction are commonly connected to respective word lines WLb 2 to WLb 8 .
- the control gates of the back gate transistors BTr arranged in a matrix form in the row and column directions are commonly connected to a back gate line BG.
- each memory block MBc the control gates of the respective drain-side selection transistors SDTrb arranged in the column direction are commonly connected to a drain-side selection gate line SGDb.
- Each drain-side selection gate line SGDb is formed to extend in the row direction across a plurality of memory blocks MBb.
- the other ends of the drain-side selection transistors SDTrb arranged in the row direction are commonly connected to a bit line BLb.
- Each bit line BLb is formed to extend in the column direction across a plurality of memory blocks MBb.
- each memory block MBc the control gates of the respective source-side selection transistors SSTrb arranged in the column direction are commonly connected to a source-side selection gate line SGSb.
- Each source-side selection gate line SGSb is formed to extend in the row direction across a plurality of memory blocks MBc.
- the other ends of the source-side selection transistors SSTrb arranged in the row direction are commonly connected to a source line SLb.
- the neighboring source-side selection transistors SSTrb in the column direction are connected to a common source line SLb.
- Each source line SLb is formed to extend in the row direction across a plurality of memory blocks MBc.
- Each memory block MBc has a back gate transistor layer 20 B, a memory transistor layer 30 B, and a selection transistor layer 40 B that are sequentially laminated on a semiconductor substrate Baa.
- the back gate transistor layer 20 B functions as back gate transistors BTr.
- the memory transistor layer 30 B functions as memory strings MSb (memory transistors MTrb 1 to MTrb 8 ).
- the selection transistor layer 40 B functions as source-side selection transistors SSTrb and drain-side selection transistors SDTrb.
- the back gate transistor layer 20 B has a back gate conductive layer 21 B.
- the back gate conductive layer 21 B is formed over a certain region so as to expand in the row and column directions.
- the back gate conductive layer 21 B is separated for each memory block MBc.
- Each back gate conductive layer 21 B is composed of, e.g., polysilicon (p-Si).
- the back gate transistor layer 20 B also has a back gate hole 22 B that is formed to dig into the back gate conductive layer 21 B.
- Each back gate hole 22 B is formed to extend in the column direction.
- the back gate holes 22 B are formed in a matrix form in the row and column directions.
- the back gate transistor layer 20 B has a block insulation layer 23 Ba, an electric charge storage layer 23 Bb, a tunnel insulation layer 23 Bc, and a bottom semiconductor layer 24 B within each back gate hole 22 B.
- Each block insulation layer 23 Ba is formed with a certain thickness on the sidewall of a back gate hole 22 B.
- Each electric charge storage layer 23 Bb is formed with a certain thickness on the sidewall of a block insulation layer 23 Ba.
- Each tunnel insulation layer 23 Bc is formed with a certain thickness on the sidewall of an electric charge storage layer 23 Bb.
- Each bottom semiconductor layer 24 B is formed to fill up a back gate hole 22 B.
- Each bottom semiconductor layer 24 B is formed to extend in the column direction.
- the block insulation layers 23 Ba and the tunnel insulation layers 23 Bc are composed of, e.g., silicon oxide (SiO 2 ).
- the electric charge storage layers 23 Bb are composed of, e.g., silicon nitride (SiN).
- the bottom semiconductor layers 24 B are composed of, e.g., polysilicon (p-Si).
- each back gate conductive layer 21 B functions as the control gate of a back gate transistor BTr.
- each back gate conductive layer 21 B functions as a part of a back gate line BG.
- the memory transistor layer 30 B has word-line conductive layers 31 Ba to 31 Bh.
- the word-line conductive layers 31 Ba to 31 Bh are formed to extend in the row direction.
- the word-line conductive layers 31 Ba to 31 Bh are insulated and isolated from each other via interlayer insulation layers (not illustrated).
- the word-line conductive layers 31 Ba to 31 Bh are separated for each memory block MBc.
- the word-line conductive layer 31 Ba and the word-line conductive layer 31 Bb are formed on the first (bottom) layer.
- the word-line conductive layer 31 Bc and the word-line conductive layer 31 Bd are formed on the second layer.
- the word-line conductive layer 31 Be and the word-line conductive layer 31 Bf are formed on the third layer.
- the word-line conductive layer 31 Bg and the word-line conductive layer 31 Bh are formed on the fourth (top) layer.
- the word-line conductive layers 31 Ba to 31 Bh are composed of, e.g., polysilicon (p-Si).
- the memory transistor layer 30 B also has a memory hole 32 Ba that is formed to penetrate the word-line conductive layers 31 Ba, 31 Bc, 31 Be, and 31 Bg, and a memory hole 32 Bb that is formed to penetrate the word-line conductive layers 31 Bb, 31 Bd, 31 Bf, and 31 Bh.
- the memory holes 32 Ba and 32 Bb are formed in a matrix form in the row and column directions.
- the memory holes 32 Ba and 32 Bb are formed to match opposite ends in the column direction of the respective back gate holes 22 B.
- the memory transistor layer 30 B has a block insulation layer 33 Ba, an electric charge storage layer 33 Bb, a tunnel insulation layer 33 Bc, and memory columnar semiconductor layers 34 Ba and 34 Bb within respective memory holes 32 Ba and 32 Bb.
- Each block insulation layer 33 Ba is formed with a certain thickness on the sidewall of a memory hole 32 B.
- Each electric charge storage layer 33 Bb is formed with a certain thickness on the sidewall of a block insulation layer 33 Ba.
- Each tunnel insulation layer 33 Bc is formed with a certain thickness on the sidewall of an electric charge storage layer 33 Bb.
- the memory columnar semiconductor layers 34 Ba and 34 Bb are formed to fill up respective memory holes 32 Ba and 32 Bb.
- Each of the memory columnar semiconductor layers 34 Ba and 34 Bb is formed in a columnar shape extending in the lamination direction.
- the memory columnar semiconductor layers 34 Ba and 34 Bb are formed in contact with the top surface of a bottom semiconductor layer 24 B at opposite ends in the column direction. That is, each semiconductor layer included in a memory string MSb includes a pair of memory columnar semiconductor layers 34 Ba and 34 Bb (columnar portions) and a bottom semiconductor layer 24 B (a joining portion) that is formed to join the bottom ends of the memory columnar semiconductor layers 34 Ba and 34 Bb.
- Each semiconductor layer included in a memory string MSb is formed in a U-shape as viewed from the row direction.
- the block insulation layers 33 Ba and the tunnel insulation layers 33 Bc are composed of, e.g., silicon oxide (SiO 2 ).
- the electric charge storage layers 33 Bb are composed of, e.g., silicon nitride (SiN).
- the memory columnar semiconductor layers 34 B are composed of, e.g., polysilicon (p-Si).
- the word-line conductive layers 31 Ba to 31 Bh function as the control gates of the memory transistors MTrb 1 to MTrb 8 .
- the word-line conductive layers 31 Ba to 31 Bh function as parts of the word lines WLb 1 to WLb 8 .
- the selection transistor layer 40 B has a source-side conductive layer 41 B and a drain-side conductive layer 42 B. Each source-side conductive layer 41 B and drain-side conductive layer 42 B are formed to extend in the row direction. Each source-side conductive layer 41 B is formed above the top word-line conductive layer 31 Bg. Each drain-side conductive layer 42 B is formed above the top word-line conductive layer 31 Bh.
- the source-side conductive layers 41 B and the drain-side conductive layers 42 B are composed of, e.g., polysilicon (p-Si).
- the selection transistor layer 40 B also has a source-side hole 43 B that is formed to penetrate a source-side conductive layer 41 B, and a drain-side hole 44 B that is formed to penetrate a drain-side conductive layer 42 B.
- Each source-side hole 43 B is formed at a position matching a respective memory hole 32 Ba.
- Each drain-side hole 44 B is formed at a position matching respective a memory hole 32 Bb.
- the selection transistor layer 40 B has a block insulation layer 45 Ba, an electric charge storage layer 45 Bb, a tunnel insulation layer 45 Bc, and a source-side columnar semiconductor layer 46 B within each source-side hole 43 B.
- Each block insulation layer 45 Ba is formed with a certain thickness on the sidewall of a source-side hole 43 B.
- Each electric charge storage layer 45 Bb is formed with a certain thickness on the sidewall of a block insulation layer 45 Ba.
- Each tunnel insulation layer 45 Bc is formed with a certain thickness on the sidewall of an electric charge storage layer 45 Bb.
- Each source-side columnar semiconductor layer 46 B is formed to fill up a source-side hole 43 B.
- the source-side columnar semiconductor layers 46 B are formed in a matrix form in the row and column directions. Each source-side columnar semiconductor layer 46 B is formed in a columnar shape extending in the lamination direction. Each source-side columnar semiconductor layer 46 B is formed in contact with the top surface of the corresponding memory columnar semiconductor layer 34 Ba.
- the block insulation layers 45 Ba and the tunnel insulation layers 45 Bc are composed of, e.g., silicon oxide (SiO 2 ).
- the electric charge storage layers 45 Bb are composed of, e.g., silicon nitride (SiN).
- the source-side columnar semiconductor layers 46 B are composed of, e.g., polysilicon (p-Si).
- the selection transistor layer 40 B has a block insulation layer 47 Ba, an electric charge storage layer 47 Bb, a tunnel insulation layer 47 Bc, and a drain-side columnar semiconductor layer 48 B within each drain-side hole 44 B.
- Each block insulation layer 47 Ba is formed with a certain thickness on the sidewall of a drain-side hole 44 B.
- Each electric charge storage layer 47 Bb is formed with a certain thickness on the sidewall of a block insulation layer 47 Ba.
- Each tunnel insulation layer 47 Bc is formed with a certain thickness on the sidewall of an electric charge storage layer 47 Bb.
- Each drain-side columnar semiconductor layer 48 B is formed to fill up a drain-side hole 44 B.
- the drain-side columnar semiconductor layers 48 B are formed in a matrix form in the row and column directions. Each drain-side columnar semiconductor layer 48 B is formed in a columnar shape extending in the lamination direction. Each drain-side columnar semiconductor layer 48 B is formed in contact with the top surface of the corresponding memory columnar semiconductor layer 34 Bb.
- the block insulation layers 47 Ba and the tunnel insulation layers 47 Bc are composed of, e.g., silicon oxide (SiO 2 ).
- the electric charge storage layers 47 Bb are composed of, e.g., silicon nitride (SiN).
- the drain-side columnar semiconductor layers 48 B are composed of, e.g., polysilicon (p-Si).
- each source-side conductive layer 41 B functions as the control gate of a source-side selection transistor SSTrb.
- each source-side conductive layer 41 B functions as a part of a source-side selection gate line SGSb.
- Each drain-side conductive layer 42 B functions as the control gate of a drain-side selection transistor SDTrb.
- Each drain-side conductive layer 42 B also functions as a part of a drain-side selection gate line SGDb.
- a source-line conductive layer 51 B is formed on the top surfaces of the source-side columnar semiconductor layers 46 B aligned in the row direction. Each source-line conductive layer 51 B is formed to extend in the row direction. Each source-line conductive layer 51 B functions as a source line SLb.
- bit-line conductive layers 52 B are formed on the top surfaces of the drain-side columnar semiconductor layers 48 B aligned in the row direction. Each bit-line conductive layer 52 B is formed to extend in the column direction. Each bit-line conductive layer 52 B functions as a bit line BLb.
- the control signal generation unit 16 performs pre-programming on the control gates of an unselected drain-side selection transistor SDTrb (n-sel) and an unselected source-side selection transistor SSTrb (n-sel) that are connected to an unselected memory string MSb. As a result, it increases the threshold voltages of these control gates.
- control signal generation unit 16 of the fourth embodiment erases the pre-programming of the control gates of the unselected drain-side selection transistor SDTrb (n-sel) and the unselected source-side selection transistor SSTrb (n-sel). As a result, it decreases the threshold voltages of these control gates.
- non-volatile semiconductor storage device of the fourth embodiment operates in the same way as described in the third embodiment. Accordingly, the non-volatile semiconductor storage device of the fourth embodiment has the same advantages as the third embodiment.
- the non-volatile semiconductor storage device of the fourth embodiment may be configured to perform pre-programming only on unselected drain-side selection transistors SDTrb (n-sel) that are connected to a selected memory string MSb (sel).
- the non-volatile semiconductor storage device of the fourth embodiment may also be configured to perform pre-programming only on unselected source-side selection transistors SSTrb (n-sel) that are connected to a selected memory string MS (sel).
Abstract
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KR101036976B1 (en) | 2011-05-25 |
USRE45832E1 (en) | 2016-01-05 |
US7933151B2 (en) | 2011-04-26 |
US20100124116A1 (en) | 2010-05-20 |
TWI413239B (en) | 2013-10-21 |
TW201403797A (en) | 2014-01-16 |
JP2010118580A (en) | 2010-05-27 |
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TWI546941B (en) | 2016-08-21 |
KR20100054742A (en) | 2010-05-25 |
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