USRE44221E1 - Method for verifying mask pattern of semiconductor device - Google Patents
Method for verifying mask pattern of semiconductor device Download PDFInfo
- Publication number
- USRE44221E1 USRE44221E1 US13/507,529 US201213507529A USRE44221E US RE44221 E1 USRE44221 E1 US RE44221E1 US 201213507529 A US201213507529 A US 201213507529A US RE44221 E USRE44221 E US RE44221E
- Authority
- US
- United States
- Prior art keywords
- layout
- pattern
- wafer
- patterns
- designed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 230000007547 defect Effects 0.000 claims abstract description 35
- 230000003287 optical effect Effects 0.000 claims description 11
- 238000012937 correction Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000012795 verification Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
Definitions
- This patent relates to a method for fabricating a semiconductor device, and more particularly, to a method for verifying a pattern of a semiconductor device.
- One of a conventional method for verifying pattern defects has been suggested, where an image of patterns formed on an actual wafer is compared with an original layout and then different parts there between resulted from the comparison are detected as defects.
- the original layout may be modified several times so as to be favorable to wafer patterning while an actual wafer process is performed. Once the original layout is modified, different parts between patterns on the actual wafer and a modified layout are detected as defects in the verification of pattern defects. Parts modified from the original layout are detected as the defects. Therefore, it is difficult to detect defects occurring on the actual wafer, e.g., pattern bridges or pinch fails.
- a method for verifying a pattern of a semiconductor device includes: providing a designed layout of target patterns; transferring the designed layout on a wafer to form wafer patterns; obtaining a image contour of the wafer patterns; matching the image contour of the wafer patterns on the designed layout; extracting edge differences between the designed layout and image contour of the wafer patterns; obtaining a checking layout for detecting wafer pattern defects by adding the edge differences on the designed layout; and identifying defects on the checking layout.
- the designed layout may include one of an original layout for the target pattern or an optical proximity corrected layout of the original layout.
- the transferring the designed layout on a wafer may include: fabricating a photomask using the designed layout for the target pattern; and forming wafer patterns on the wafer using the fabricated photomask;
- the obtaining the image contour may include performing with the aid of a scanning electron microscope.
- the extracting edge differences may include: comparing an edge point of a pattern of the designed layout with an edge point of a wafer pattern of the image contour; converting differences between the edge points of the wafer pattern of the image contour and the edge point on a pattern the designed layout into a GDS data; and storing the GDS data.
- the obtaining a checking layout may include converting a critical dimension of a pattern of the designed layout into a critical dimension of a pattern of the checking layout by adding the edge difference in an edge point of the pattern of the designed layout.
- the identifying defects may include: dividing the checking layout into a line pattern region and a space region; and detecting of the defects in the line pattern region and in the space region.
- the detecting the line pattern region may include: providing a reference critical dimension value of the line pattern; and determining whether a critical dimension of a pattern in the checking layout deviates from the reference critical dimension value.
- the detecting the defects in the space region may include: providing a reference dispacing value between line patterns; and determining whether a dispacing between line patterns in the checking layout deviates from the reference dispacing value 10.
- the method may further include, after identifying defects, performing another optical proximity correction by feed back the detected defects on the designed layout.
- FIG. 1 is a flow chart illustrating a method for verifying a pattern of a semiconductor device according to an embodiment of the invention.
- FIGS. 2 to 6 are schematic plan views illustrating the method of FIG. 1 , in accordance with an embodiment of the invention.
- a designed layout 200 is provided for target patterns, as illustrated in FIG. 2 (S 10 ).
- a designer designs patterns using patterns to be realized on a wafer and data containing information.
- the layout 200 is designed in a layout editor such that it has the same shape as the wafer patterns which will be formed on an actual wafer.
- the layout 200 may be an original layout that a designer designs for the first time or an optical proximity corrected layout (OPC layout) for suppressing optical proximity effect on the original layout.
- OPC layout optical proximity corrected layout
- Wafer patterns is transferred on the actual wafer using the designed layout 200 (S 11 ). Specifically, a photomask having the same pattern configuration as the designed layout 200 for the target patterns is fabricated, and wafer patterns are then formed on the actual wafer using the fabricated photomask.
- the wafer patterns formed on the actual wafer are photographed with a scanning electron microscope (SEM), to obtain an image contour of the wafer patterns (S 12 ).
- SEM scanning electron microscope
- Other types of technique may be used.
- the image contour of wafer patterns on the designed layout are matched, as illustrated in FIG. 3 . (S 13 ). Thereafter, Edge differences between the designed layout 200 and the image contour of the wafer patterns are extracted (S 14 ). In detail, edge points of patterns the designed layout 200 are compared with those of the image contour of wafer patterns through a measuring apparatus (not shown). Edge differences between the edge points of the patterns of the designed layout 200 and the edge point on a wafer pattern image contour are converted into, for example, a GDS data and the GDS data are stored.
- the GDS data refers to a difference between critical dimensions d 1 (as depicted in FIG. 3 ) in the edge points of the image contour of wafer patterns and the patterns on the designed layout 200 .
- a checking layout 210 for detecting wafer pattern defects by adding the edge differences on the designed layout are obtained, as illustrated in FIG. 4 .
- (S 15 ) That is, the stored GDS data are reflected in the edge points of the designed layout 200 designed in the layout editor so that the critical dimension of the designed layout 200 can be converted into the critical dimension of the wafer patterns formed on the actual wafer.
- Defects on the checking layout 210 is identified to verify the patterns in view of processes before the preparation of a mask (S 16 ). At this time, the identify may be performed in such a manner than the checking layout 210 is divided into a line pattern region and a space region and the identify may be detecting of the line pattern region and in the space region, respectively.
- a reference critical dimension (CD) value of the line patterns it is provided a reference critical dimension (CD) value of the line patterns and determined whether or not critical dimensions d 2 of the line patterns in the checking layout 210 a deviate from the reference critical dimension, as illustrated in FIG. 5 .
- this point is detected as a weak point, e.g., a pinch fail 211 .
- a reference dispacing value between line patterns and determined whether or not a dispacing d 3 between the line patterns in the checking layout 210 b deviates from the reference dispacing value, as illustrated in FIG. 6 .
- this point is detected as a weak point e.g., a bridge defect 212 .
- the designed layout is corrected taking into account of how much the detected defects have an effect on a process window according to pattern verification results (S 16 ).
- the designed layout is performing another optical proximity correction by feed back the detected defects on the designed layout.
- the OPC process is performed in consideration of the detected defects.
- the OPC process may be re-executed
- a method for verifying a pattern of a semiconductor device the checking layout has the same shape as the wafer pattern formed on the wafer is obtained by adding the edge differences on the designed layout, and the checking layout is verified for detecting wafer pattern defects. Therefore, defects occurring on the wafer patterns, e.g., patterns bridges or pinch fail can be effectively detected. Moreover, the defects is accurate estimate before the fabrication of a mask can be effectively prevented re-adjustment or re-fabrication.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
Description
Claims (18)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/507,529 USRE44221E1 (en) | 2007-06-27 | 2012-07-05 | Method for verifying mask pattern of semiconductor device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070063926A KR100877105B1 (en) | 2007-06-27 | 2007-06-27 | Method for verifying pattern of semicondutor device |
KR10-2007-0063926 | 2007-06-27 | ||
US11/965,201 US7752584B2 (en) | 2007-06-27 | 2007-12-27 | Method for verifying mask pattern of semiconductor device |
US13/507,529 USRE44221E1 (en) | 2007-06-27 | 2012-07-05 | Method for verifying mask pattern of semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/965,201 Reissue US7752584B2 (en) | 2007-06-27 | 2007-12-27 | Method for verifying mask pattern of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE44221E1 true USRE44221E1 (en) | 2013-05-14 |
Family
ID=40162328
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/965,201 Active 2028-04-22 US7752584B2 (en) | 2007-06-27 | 2007-12-27 | Method for verifying mask pattern of semiconductor device |
US13/507,529 Active 2028-04-22 USRE44221E1 (en) | 2007-06-27 | 2012-07-05 | Method for verifying mask pattern of semiconductor device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/965,201 Active 2028-04-22 US7752584B2 (en) | 2007-06-27 | 2007-12-27 | Method for verifying mask pattern of semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (2) | US7752584B2 (en) |
KR (1) | KR100877105B1 (en) |
CN (1) | CN101334802B (en) |
TW (1) | TW200901277A (en) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7653892B1 (en) | 2004-08-18 | 2010-01-26 | Cadence Design Systems, Inc. | System and method for implementing image-based design rules |
US7570796B2 (en) | 2005-11-18 | 2009-08-04 | Kla-Tencor Technologies Corp. | Methods and systems for utilizing design data in combination with inspection data |
KR101296290B1 (en) * | 2007-12-07 | 2013-08-14 | 삼성전자주식회사 | Method of measuring MTT based on pattern area measurement and method of correcting photomask using the same |
US8381152B2 (en) | 2008-06-05 | 2013-02-19 | Cadence Design Systems, Inc. | Method and system for model-based design and layout of an integrated circuit |
KR101841897B1 (en) | 2008-07-28 | 2018-03-23 | 케이엘에이-텐코어 코오포레이션 | Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer |
JP2010087299A (en) * | 2008-09-30 | 2010-04-15 | Toshiba Corp | Process model evaluation method, process model generation method and process model evaluation program |
CN102193303B (en) * | 2010-03-05 | 2013-07-17 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method |
WO2012068323A2 (en) * | 2010-11-18 | 2012-05-24 | D2S, Inc. | Method for matching of patterns |
US9170211B2 (en) | 2011-03-25 | 2015-10-27 | Kla-Tencor Corp. | Design-based inspection using repeating structures |
US8669523B2 (en) * | 2011-05-25 | 2014-03-11 | Kla-Tencor Corporation | Contour-based defect detection using an inspection apparatus |
US9087367B2 (en) | 2011-09-13 | 2015-07-21 | Kla-Tencor Corp. | Determining design coordinates for wafer defects |
US8832621B1 (en) | 2011-11-28 | 2014-09-09 | Cadence Design Systems, Inc. | Topology design using squish patterns |
US9189844B2 (en) | 2012-10-15 | 2015-11-17 | Kla-Tencor Corp. | Detecting defects on a wafer using defect-specific information |
CN103018265B (en) * | 2012-11-28 | 2015-05-20 | 上海华力微电子有限公司 | Method for positioning defect of semiconductor |
US9053527B2 (en) | 2013-01-02 | 2015-06-09 | Kla-Tencor Corp. | Detecting defects on a wafer |
US9134254B2 (en) | 2013-01-07 | 2015-09-15 | Kla-Tencor Corp. | Determining a position of inspection system output in design data space |
US9311698B2 (en) * | 2013-01-09 | 2016-04-12 | Kla-Tencor Corp. | Detecting defects on a wafer using template image matching |
US9483819B2 (en) * | 2013-01-29 | 2016-11-01 | Kla-Tencor Corporation | Contour-based array inspection of patterned defects |
KR102019534B1 (en) | 2013-02-01 | 2019-09-09 | 케이엘에이 코포레이션 | Detecting defects on a wafer using defect-specific and multi-channel information |
US9865512B2 (en) | 2013-04-08 | 2018-01-09 | Kla-Tencor Corp. | Dynamic design attributes for wafer inspection |
US9310320B2 (en) | 2013-04-15 | 2016-04-12 | Kla-Tencor Corp. | Based sampling and binning for yield critical defects |
KR102310123B1 (en) * | 2014-09-05 | 2021-10-08 | 삼성전자주식회사 | Pattern analysis method of semiconductor device |
KR20160078032A (en) | 2014-12-24 | 2016-07-04 | 삼성전자주식회사 | Apparatus and method for electronic design automation |
CN106033171B (en) * | 2015-03-11 | 2019-12-17 | 中芯国际集成电路制造(上海)有限公司 | Failure analysis method for dead spots on wafer |
US9846934B2 (en) * | 2015-04-13 | 2017-12-19 | Anchor Semiconductor Inc. | Pattern weakness and strength detection and tracking during a semiconductor device fabrication process |
US10209628B2 (en) * | 2016-05-26 | 2019-02-19 | Kla-Tencor Corporation | System and method for defect classification based on electrical design intent |
KR102592599B1 (en) | 2016-05-12 | 2023-10-24 | 삼성전자주식회사 | Method for verifying a layout designed for semiconductor integrated circuit and a computer system perforing the same |
US10163733B2 (en) | 2016-05-31 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of extracting defects |
KR102595300B1 (en) * | 2016-07-04 | 2023-10-31 | 삼성전자주식회사 | Inspection method and system, and method of forming semiconductor package using the same |
KR102582665B1 (en) * | 2016-10-07 | 2023-09-25 | 삼성전자주식회사 | System and method for evaluating patterns of integrated circuit |
US10394116B2 (en) | 2017-09-06 | 2019-08-27 | International Business Machines Corporation | Semiconductor fabrication design rule loophole checking for design for manufacturability optimization |
US10621295B2 (en) | 2018-04-10 | 2020-04-14 | International Business Machines Corporation | Incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield |
KR102630568B1 (en) * | 2018-06-15 | 2024-01-29 | 삼성전자주식회사 | Method for manufacturing semiconductor device |
US10796065B2 (en) * | 2018-06-21 | 2020-10-06 | Kla-Tencor Corporation | Hybrid design layout to identify optical proximity correction-related systematic defects |
CN110889822B (en) * | 2018-08-17 | 2023-06-06 | 台湾积体电路制造股份有限公司 | Wafer design image analysis method, system and non-transitory computer readable medium |
TWI703535B (en) * | 2018-10-25 | 2020-09-01 | 南茂科技股份有限公司 | Method for detecting edge defects |
CN117348334B (en) * | 2023-12-04 | 2024-04-16 | 华芯程(杭州)科技有限公司 | Optical proximity correction method, device, equipment and medium |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0156792B1 (en) | 1994-09-16 | 1998-11-16 | 기다오까 다까시 | Device and method for correcting optical proximity and pattern |
KR0172558B1 (en) | 1995-03-22 | 1999-03-20 | 김주용 | A fabricating method of exposure mask |
KR20030014427A (en) | 2001-05-10 | 2003-02-17 | 소니 가부시끼 가이샤 | Rule base OPC evaluating method, and simulation base OPC model evaluating method |
US20050142455A1 (en) | 2003-12-26 | 2005-06-30 | Nec Electronics Corporation | Method for inspecting mask |
KR20060105847A (en) | 2005-04-04 | 2006-10-11 | 주식회사 하이닉스반도체 | Method of checking layout in photolithography process using anisotropy and asymmetric illumination |
KR100673014B1 (en) | 2005-10-28 | 2007-01-24 | 삼성전자주식회사 | Method of fabricating photomask |
US7194709B2 (en) | 2004-03-05 | 2007-03-20 | Keith John Brankner | Automatic alignment of integrated circuit and design layout of integrated circuit to more accurately assess the impact of anomalies |
US7254804B2 (en) | 2003-11-27 | 2007-08-07 | Kabushiki Kaisha Toshiba | Method of verifying corrected photomask-pattern results and device for the same |
US7275227B1 (en) | 2003-08-27 | 2007-09-25 | Anchor Semiconductor Inc. | Method of checking optical proximity correction data |
-
2007
- 2007-06-27 KR KR1020070063926A patent/KR100877105B1/en not_active IP Right Cessation
- 2007-12-27 US US11/965,201 patent/US7752584B2/en active Active
-
2008
- 2008-02-21 TW TW097106035A patent/TW200901277A/en unknown
- 2008-04-10 CN CN2008100886568A patent/CN101334802B/en not_active Expired - Fee Related
-
2012
- 2012-07-05 US US13/507,529 patent/USRE44221E1/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0156792B1 (en) | 1994-09-16 | 1998-11-16 | 기다오까 다까시 | Device and method for correcting optical proximity and pattern |
KR0172558B1 (en) | 1995-03-22 | 1999-03-20 | 김주용 | A fabricating method of exposure mask |
KR20030014427A (en) | 2001-05-10 | 2003-02-17 | 소니 가부시끼 가이샤 | Rule base OPC evaluating method, and simulation base OPC model evaluating method |
US7275227B1 (en) | 2003-08-27 | 2007-09-25 | Anchor Semiconductor Inc. | Method of checking optical proximity correction data |
US7254804B2 (en) | 2003-11-27 | 2007-08-07 | Kabushiki Kaisha Toshiba | Method of verifying corrected photomask-pattern results and device for the same |
US20050142455A1 (en) | 2003-12-26 | 2005-06-30 | Nec Electronics Corporation | Method for inspecting mask |
US7194709B2 (en) | 2004-03-05 | 2007-03-20 | Keith John Brankner | Automatic alignment of integrated circuit and design layout of integrated circuit to more accurately assess the impact of anomalies |
KR20060105847A (en) | 2005-04-04 | 2006-10-11 | 주식회사 하이닉스반도체 | Method of checking layout in photolithography process using anisotropy and asymmetric illumination |
KR100673014B1 (en) | 2005-10-28 | 2007-01-24 | 삼성전자주식회사 | Method of fabricating photomask |
US7475383B2 (en) | 2005-10-28 | 2009-01-06 | Samsung Electronics Co. Ltd. | Method of fabricating photo mask |
Also Published As
Publication number | Publication date |
---|---|
TW200901277A (en) | 2009-01-01 |
US7752584B2 (en) | 2010-07-06 |
KR100877105B1 (en) | 2009-01-07 |
US20090007052A1 (en) | 2009-01-01 |
CN101334802A (en) | 2008-12-31 |
KR20080114402A (en) | 2008-12-31 |
CN101334802B (en) | 2011-02-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
USRE44221E1 (en) | Method for verifying mask pattern of semiconductor device | |
US11120182B2 (en) | Methodology of incorporating wafer physical measurement with digital simulation for improving semiconductor device fabrication | |
TWI594067B (en) | System and method for discovering unknown problematic patterns in chip design layout for semiconductor manufacturing | |
US8121387B2 (en) | Mask pattern verifying method | |
JP4854319B2 (en) | Verification method of optical proximity correction using layout vs layout inspection method | |
CN106033171B (en) | Failure analysis method for dead spots on wafer | |
US9983154B2 (en) | Method for inspecting a pattern of features on a semiconductor die | |
KR101033225B1 (en) | Method for performing OPC on pattern layout | |
JP2007298856A (en) | Semiconductor mask correction device and semiconductor mask correction method | |
US20060039596A1 (en) | Pattern measuring method, pattern measuring apparatus, photo mask manufacturing method, semiconductor device manufacturing method, and computer program product | |
US20060206853A1 (en) | Method of producing mask inspection data, method of manufacturing a photo mask and method of manufacturing a semiconductor device | |
US8863043B1 (en) | Inspection data generator, inspection data generating method and pattern inspecting method | |
US11686998B2 (en) | Method for manufacturing a semiconductor device | |
JP2007081293A (en) | Inspection method, method of manufacturing semiconductor device and program | |
US8233695B2 (en) | Generating image inspection data from subtracted corner-processed design data | |
KR20100073374A (en) | Method for detecting defects of semiconductor device | |
JP2002323749A (en) | Method for discriminating defect of photomask and defect part having been corrected | |
KR20090071738A (en) | Method for verifying patterns by using multi - layout data | |
JP2007081292A (en) | Inspection method, inspection system and program | |
JP2006337668A (en) | Method for manufacturing semiconductor device, and production program of layout pattern | |
JP2010224114A (en) | Method for manufacturing mask and device for manufacturing semiconductor device | |
JP2004213030A (en) | Mask defect inspecting method | |
KR20070067253A (en) | Method of inspecting image in a semiconductor fabricating | |
KR20110001145A (en) | Method for fabricating mask | |
KR20110112722A (en) | Method of inspecting a semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |
|
AS | Assignment |
Owner name: SK HYNIX INC., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:HYNIX-SEMICONDUCTOR INC.;REEL/FRAME:067328/0814 Effective date: 20120730 |
|
AS | Assignment |
Owner name: MIMIRIP LLC, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SK HYNIX INC.;REEL/FRAME:067369/0832 Effective date: 20240311 |
|
AS | Assignment |
Owner name: SK HYNIX INC., KOREA, REPUBLIC OF Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE IS HYNIX SEMICONDUCTOR INC. NOT HYNIX-SEMICONDUCTOR INC. THERE IS NO HYPHEN IN THE NAME. PREVIOUSLY RECORDED ON REEL 67328 FRAME 814. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME;ASSIGNOR:HYNIX SEMICONDUCTOR INC.;REEL/FRAME:067412/0482 Effective date: 20120730 |