USRE40915E1 - Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter - Google Patents
Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter Download PDFInfo
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- USRE40915E1 USRE40915E1 US11/488,927 US48892706A USRE40915E US RE40915 E1 USRE40915 E1 US RE40915E1 US 48892706 A US48892706 A US 48892706A US RE40915 E USRE40915 E US RE40915E
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- current
- sensed
- correction
- sensed current
- compensating
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S323/00—Electricity: power supply or regulation systems
- Y10S323/907—Temperature compensation of semiconductor
Definitions
- the present invention relates in general to electronic circuits and components therefor, and is particularly directed to a new and improved current-sensing and correction circuit with a programmable, continuous compensation for temperature variations of an output switching MOSFET of a buck mode DC—DC converter.
- Electrical power for an integrated circuit is typically supplied by one or more direct current (DC) power sources, such as a buck-mode, pulse width modulation (PWM) based, DC—DC converter of the type diagrammatically shown in FIG. 1 .
- DC direct current
- a controller 10 supplies a PWM signal to a (MOSFET gate) driver 20 , for controlling the turn-on and turn-off of a pair of electronic power switching devices, to which a load is coupled.
- these power switching devices are depicted as an upper (or high side) power NMOSFET (or NFET) device 30 , and a lower (or low side) power NFET device 40 , having their drain-source current flow paths connected in series between a pair of power supply rails (e.g., VIN and ground (GND)).
- a pair of power supply rails e.g., VIN and ground (GND)
- the upper NFET device 30 is turned on and off by an upper gate switching signal UGATE being applied to its gate from driver 20
- the lower NFET device 40 is turned on and off by a lower gate switching signal LGATE from driver 20
- a common node 35 between the upper and lower NFETs is coupled through an inductor 50 (which may typically comprise a transformer winding) to a load reservoir capacitor 60 coupled to a reference voltage terminal (GND).
- a connection 55 between inductor 50 and capacitor 60 serves as an output node from which a desired (regulated) DC output voltage Vout is applied to a LOAD 65 (shown as coupled to GND).
- the output node connection 55 is also fed back to error amplifier circuitry (not shown) within the controller, the error amplifier being used to regulate the converter's output DC voltage relative to a reference voltage supply.
- the common node 35 is also coupled to current-sensing circuit 15 within controller 10 , in response to which the controller adjusts the PWM signal, as necessary, to maintain the converter's DC output within a prescribed set of parameters.
- the controller may incorporate a current-sensing circuit of the type described in U.S. Pat. No. 6,246,220, entitled: “Synchronous-Rectified DC to DC Converter with Improved Current Sensing,” issued Jun. 12, 2001, by R. Isham et al, assigned to the assignee of the present application and the disclosure of which is incorporated herein.
- the controller monitors the source-drain current flowing through the lower NFET 40 by way of a current-sensing or scaling resistor 37 electrically interconnected between node 35 and an current-sensing circuit 15 .
- the current-sensing circuit is operative to monitor the current I SENSE flowing through scaling resistor 37 .
- This current is the product of the output current I OUT flowing from the common node 35 to the inductor 50 times the ratio of the ON-resistance R DS40ON of the lower NFET 40 to the resistance R 37 of the scaling resistor 37 , and is thus proportionally representative of the output current I OUT .
- the load current I L namely the current I 50 flowing through the inductor 50 , is substantially equal to the output current I OUT minus the current I SENSE flowing through the scaling resistor 37 .
- the current I SENSE will be substantially smaller than the output current I OUT , so that the output current I OUT and the load current I L will have substantially similar magnitudes, making I SENSE representative of load current.
- the resistance of the scaling resistor 37 is selected to provide a prescribed value of current flow for the values of load current I L and/or the value of the ON-state resistance R DS40ON of the lower NFET 40 .
- the sensitivity or magnitude of, for example, voltage droop, current limiting or trip, and current balancing incorporated into the DC/DC converter is effectively ‘scaled’ by selecting resistor 37 relative to the value of the on-state resistance R DS40ON of the lower NFET 40 .
- the voltage drop across the on-state resistance R DS40ON of the lower NFET 40 (usually negative) is accommodated in the converter without a negative voltage supply.
- scaling resistor 37 since the ON-resistance R DS40ON of the lower NFET 40 varies with temperature, scaling resistor 37 must be selected to have a temperature coefficient which offsets the behavior of NFET 40 . This may be accomplished by replacing scaling resistor 37 with a network of resistors and positive temperature coefficient thermistors.
- the controller's current-sensing circuit 15 comprises a sense amplifier 200 having a first, non-inverting (+) input 201 coupled to a controller SENSE-port 11 , and a second, inverting ( ⁇ ) input 202 coupled to a controller SENSE+ port 12 .
- the SENSE-port 11 is coupled to the grounded termination of NFET 40
- the SENSE+ port 12 is coupled through scaling resistor 37 to common node 35 .
- the sense amplifier 200 has its output 203 coupled to the gate 213 of an NFET 210 , whose drain-source path is coupled between the SENSE+ port 12 and input terminal 221 of a sample-and-hold circuit 220 .
- Sample-and-hold circuit 220 includes PFETs 240 and 250 coupled with a capacitor 260 and input sampling switching circuitry.
- the sense amplifier 200 and NFET 210 (which serves as a controlled impedance) are operative to continuously drive the controller's SENSE+ port 11 toward ground potential. This forces the end of the current feedback resistor 37 which is connected to controller SENSE+ port 11 to be at ground potential and the end connected to common node 35 to have a negative voltage.
- the negative voltage at common output node 35 will be equal to the product of the output current I OUT and the on-state resistance R DS40ON between the drain and source of the lower NFET 40 .
- sampling control circuitry periodically supplies a sampling control signal to the sample-and-hold circuit 220 , when NFET 210 is in its ON (conducting) state.
- the sample-and-hold circuit 220 samples the current flowing through NFET 210 and stores the sampled value on capacitor 260 via node 236 .
- the sampled current value acquired by the sample-and-hold circuit 220 is also representative of load current I L .
- This sampled value of sensed current is coupled from the sample and hold circuit's output port 223 to the controller's error amplifier circuitry that monitors the output node 55 .
- the scaling resistor 37 that couples the common node 35 to the controller's SENSE+ port 11 must have a temperature coefficient that offsets the behavior of the on-state resistance R DS40ON of the lower NFET 40 (which varies with temperature and may be as high as forty percent over a typical operating range). As a result, it is customary to employ some form of complicated and costly feedback network in place of resistor 37 .
- the above-discussed temperature variation problem is successfully addressed by a new and improved current-sensing and correction circuit, containing programmable temperature compensation circuitry and being configured to be incorporated into a DC—DC converter, such as the buck mode architecture of the type shown in FIGS. 1 and 2 , described above.
- each embodiment of the invention includes sense amplifier, NFET and sample-and-hold components described above with reference to FIG. 2 .
- an auxiliary output of the sample-and-hold circuit supplies a copy of the sampled sense current to a programming resistor having a programmable resistance.
- the voltage produced across the programming resistor is coupled to respective high temperature compensation (HIGHtc) and low temperature compensation (LOWtc) auxiliary sense amplifiers.
- the output of the HIGHtc auxiliary sense amplifier controls a HIGHtc NFET, the drain-source path of which is coupled to a HIGHtc scaling resistor.
- the temperature coefficient of resistance of the HIGHtc scaling resistor is higher than that of a LOWtc scaling resistor in the source-drain path of a LOWtc NFET at the output of the LOWtc auxiliary sense amplifier.
- the source-drain path of the HIGHtc NFET is coupled to a current mirror, which supplies a copy of the current in the source-drain path of the HIGHtc NFET to summing node, that serves as the output of the current-sensing and correction circuit.
- the summing node combines the HIGHtc and LOWtc currents and the sensed current to produce a “temperature-corrected” output current that is coupled to the controller's error amplifier circuitry in place of the sensed current.
- the ratio of the resistance of the HIGHtc resistor to that of the programming resistor will have a larger slope with temperature than the ratio of the resistance of the LOWtc resistor to that of the programming resistor.
- the contribution of the HIGHtc current flowing into the output node will decrease with increasing temperature faster than the contribution of the LOWtc current flowing out of the output node, so that the composite corrected current will decrease with increase in temperature.
- the ratio of the corrected current to the sensed current will be less than 1.0; for temperatures below this current-equality temperature, the ratio of the corrected current to the sensed current will be greater than 1.0.
- the temperature-compensating relationship of the corrected current to the sensed current is such that the ratio of corrected current to sensed current follows a deterministic curve at temperatures other than said predetermined temperature. It should be noted that the amount of temperature compensation is set by the programming resistor.
- the first embodiment is modified to substitute an additional gain stage for the current mirror that supplies the replicated HIGHtc current to the output/summing node. This provides more temperature dependence for given values of thermal coefficients of resistance.
- FIG. 1 diagrammatically illustrates a conventional buck-mode, pulse width modulation (PWM) based, DC—DC converter;
- PWM pulse width modulation
- FIG. 2 diagrammatically illustrates a current-sensing circuit for the controller of the DC—DC converter of FIG. 1 ;
- FIG. 3 diagrammatically shows a current-sensing and programmable temperature-compensation circuit in accordance with a first embodiment of the present invention
- FIG. 4 graphically depicts the relationship between the ratio of temperature-compensated current I CORRECTED to sense current I SENSE over a temperature range ( ⁇ 20° C. to +125° C.), for a number of different resistance values R PROGRAM of the programming resistor of the embodiment of the current-sensing and programmable temperature-compensation circuit of FIG. 3 ;
- FIG. 5 diagrammatically shows a current-sensing and programmable temperature-compensation circuit in accordance with a second embodiment of the invention, in which the embodiment of FIG. 3 is modified to incorporate an additional gain stage in place of the current mirror circuitry that is used to supply the replicated current component I HIGHtc to the output node.
- FIG. 3 diagrammatically illustrates a first embodiment of a current-sensing and correction circuit in accordance with the present invention, containing programmable temperature compensation circuitry and being configured to be incorporated into a buck mode DC—DC converter of the type shown in FIGS. 1 and 2 , described above.
- the front end portion of the temperature compensated current sensing and correction circuit of FIG. 3 shown within broken lines 300 , contains the sense amplifier, NFET and sample-and-hold components shown in FIG. 2 , discussed above. As such, these components will not be redescribed, except as necessary to explain the architecture and operation of the invention.
- a sample value storage node 224 of the sample-and-hold circuit 220 is connected to a sampled value storage capacitor 260 , which is switchably coupled (via switching unit 231 ) to input node 221 , so that it may receive and store a sampled value of the sensed current.
- Node 224 is further coupled to the gate of an output PMOSFET 250 that supplies the sampled sense current I SENSE to the sample-and-hold output terminal 223 , and additionally to the gate of an auxiliary output PMOSFET 227 , that supplies a copy of the sample sense I SENSE current to an auxiliary output terminal 228 .
- This copy of the I SENSE current provided by the auxiliary output terminal 228 is coupled to a programming resistor 310 , referenced to ground and having a programmable resistance r PROGRAM .
- the temperature coefficient of the programming resistor 310 is zero or very close to zero.
- the programming resistor is used to change the slope of a deterministic curve, such as that shown in FIG. 4 , which represents the ratio of corrected or temperature-compensated current to the sensed current I SENSE .
- the voltage produced across the programming resistor 310 at node 228 is coupled to each of a first, non-inverting (+) input 321 of a first auxiliary sense amplifier 320 , and to a first, non-inverting (+) input 331 of a second auxiliary sense amplifier 330 .
- the first auxiliary sense amplifier 320 has its second, inverting ( ⁇ ) input 322 coupled to a node 324 between a first, ‘HIGHtc’ scaling resistor 325 and the source-drain current flow path of an NFET 340 .
- NFET 340 has its gate coupled to the output 323 of the first auxiliary sense amplifier 320 .
- Scaling resistor 325 which is coupled to ground, has a first prescribed scaling resistance value r HIGHtc , that serves to reduce the ratio of a composite, temperature compensated, or corrected, output current I CORRECTED to the I SENSE current at temperatures above a predetermined temperature.
- the temperature coefficient of resistance of the scaling resistance 325 is higher than the temperature coefficient of resistance of a second scaling resistor 335 , to be described.
- the source-drain path of NFET 340 is coupled to the source-drain path of a current mirror PFET 350 , which is referenced to the VCC voltage rail.
- NFET 340 is controlled by the first auxiliary sense amplifier 320 to produce a first fractional, or scaled, version of sense current I SENSE as a first temperature compensation current I HIGHtc , that is combined with the sense current I SENSE and a second temperature compensation current I LOWtc , to realize the temperature corrected, output current I CORRECTED , as will be described.
- PFET 350 is coupled in current-mirror configuration with PFET 360 , which has its source-drain path referenced to the VCC voltage rail, and coupled via an output node 365 to the source-drain path an NFET 370 .
- the source-drain path of current mirror PFET 360 mirrors the ‘high’ temperature coefficient compensation current I HIGHtc (flowing through the scaling resistor 325 and the source-drain path of PFET 350 ) and couples this current to the output node 365 .
- Output node 365 from which the ‘corrected’ sense current I CORRECTED is derived, is coupled in common with the output port 223 of the sample and hold circuit 220 .
- NFET 370 has its source-drain path coupled to a node 334 between a second, ‘LOWtc’ scaling resistor 335 and the source-drain current flow path of an NFET 370 .
- Scaling resistor 335 is coupled to ground.
- Node 334 is coupled to an inverting ( ⁇ ) input 332 of the second auxiliary amplifier 330 .
- the temperature coefficient of resistance of the scaling resistance 335 is lower than the temperature coefficient of resistance of a scaling resistor 325 .
- NFET 370 is controlled by the output of the second auxiliary sense amplifier 330 to produce a second scaled version of the sense current I SENSE as a second temperature compensation current I LOWtc .
- This second temperature compensation current is combined at output port 365 with the sense current I SENSE and the first temperature compensation current I HIGHtc , to realize the temperature corrected, output current I CORRECTED .
- the copy of the current I SENSE provided by auxiliary output 228 flows through programming resistor 310 to produce a voltage Vr PROGRAM across the programming resistor.
- This voltage is applied to the non-inverting (+) inputs of each of the auxiliary sense amplifiers 320 and 330 .
- the first auxiliary amplifier 320 drives the gate of NFET 340 , to produce a source-drain current I HIGHtc , that flows through scaling resistor 325 ; in a like manner, the second auxiliary amplifier 330 drives the gate of NFET 370 , to produce a source-drain current I LOWtc , that flows through scaling resistor 335 .
- the two currents I HIGHtc and I LOWtc are set at the same value for a particular operating temperature (such as 25° C.). Since current mirror PFET 360 is operative to mirror the temperature compensation current I HIGHtc in the source-drain path of PFET 350 in accordance with the operation of NFET 340 , the output node 365 is supplied with three current components: 1—the sense current I SENSE from port 223 of the sample and hold circuit 220 ; 2—the current I HIGHtc mirrored by PFET 360 ; and 3—the current I LOWtc produced by NFET 370 .
- This temperature-compensated current I CORRECTED is coupled to the controller's error amplifier circuitry in place of the sensed current I SENSE , as described above.
- FIG. 4 contains a family of deterministic curves, that graphically depict the temperature-compensating relationship (i.e., ratio) of the temperature-compensated or correction current I CORRECTED to the sense current I SENSE over a typical operational temperature range ( ⁇ 20° C. to +125° C.), for a number of different resistance values R PROGRAM of the programming resistor 310 , and with the two currents I HIGHtc and I LOWtc being the same at the above-referenced value of 25° C.
- a typical operational temperature range ⁇ 20° C. to +125° C.
- the ratio of the resistance of resistor 325 to the resistance of programming resistor 310 will increase with temperature faster than the ratio of the resistance of resistor 335 to the resistance of programming resistor 310 .
- the contribution of the current component I HIGHtc into node 365 will decrease faster than the contribution of the current I LOWtc away from node 365 , so that the composite current I CORRECTED will decrease.
- FIG. 5 diagrammatically shows a second embodiment of the current sensing circuit of the invention, in which the first embodiment of FIG. 3 is modified to incorporate an additional gain stage in place of the current mirror circuitry that is used to supply the replicated current component I HIGHtc to the output node.
- PFETs 350 and 360 of the first embodiment are replaced with a gain stage 500 having a third auxiliary amplifier 510 which drives a PFET 520 .
- Amplifier 510 has its non-inverting (+) input 512 coupled to a node 514 , which is connected in common to a scaling resistor 530 referenced to VCC and NFET 340 .
- Scaling resistor 530 has a resistance r LOWtc2 .
- Amplifier 510 has its inverting ( ⁇ ) input 511 coupled to a node 515 , which is connected in common to a scaling resistor 540 referenced to VCC and PFET 520 .
- Scaling resistor 540 has a resistance r HIGHtc2 .
- This modified architecture operates in the same manner as current mirror PMOSFETs 350 and 360 , but modifies the current output of PMOSFET 520 dependent on temperature.
- Resistance r HIGHtc2 has a higher thermal coefficient of resistance than resistance r LOWtc2 .
- some reference temperature such as the temperature at which resistance r HIGHtc and resistance r LOWtc are equal, as described above, resistance r HIGHtc2 and resistance r LOWtc2 are equal.
- the current through the resistance r HIGHtc 325 , and NMOSFET 340 into resistance r LOWtc2 530 is replicated by PMOSFET 520 through resistance r HIGHtc2 540 .
- the ratio of r HIGHtc2 /r LOWtc2 increases and, conversely, the current out of PMOSFET 520 decreases.
- the current out of PMOSFET 520 or I HIGHtc , becomes equal to: I SENSE *(R PROGRAM /R HIGHtc )*(R LOWtc2 /R HIGHtc2 ).
- the current out of NMOSFET 370 is I SENSE *(R PROGRAM /R LOWTC ).
- gain stage 500 may be added for additional increases in thermal gain.
- This temperature-compensated current I CORRECTED is coupled to the controller's error amplifier circuitry in place of the sensed current I SENSE , as described above.
- a corrected current can be derived as a combination of the sensed current and the controlled ‘hightc’ and ‘lowtc’ currents.
- I CORRECTED /I SENSE 1 ⁇ (r PROGRAM /r LOWtc )+(r PROGRAM /r HIGHtc ).
- an additional gain stage is inserted in place of the current mirror circuitry that is used to supply the replicated current component I HIGHtc to the output node, so that the output current of the PMOSFET is modified in dependence on temperature.
- the temperature-compensated current I CORRECTED is coupled to the controller's error amplifier circuitry to track the temperature variations in the drain-source resistance of the lower MOSFET of the converter.
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Abstract
Description
ICORRECTED=ISENSE−ILOWtc+iHIGHtc, or
ICORRECTED=ISENSE*(1−(rPROGRAM/rLOWtc)+(rPROGRAM/rHIGHtc)).
ISENSE(1+RPROGRAM(RLOWtc2/(RHIGHtc.RHIGHtc2.)−(1/RLOWtc)).
ISENSE(1+RPROGRAM((1/RHIGHtc)−(1/RLOWtc))).
ICORRECTED=ISENSE−ILOWtc+IHIGHtc or, in terms of the resistors, as:
ICORRECTED=ISENSE*(1-(rPROGRAM/rLOWtc)+(rPROGRAM/rHIGHtc)).
ICORRECTED/ISENSE=1−(rPROGRAM/rLOWtc)+(rPROGRAM/rHIGHtc).
ISENSE(1+RPROGRAM(RLOWtc2/(RHIGHtc.RHIGHtc2.)−(1/RLOWtc)).
ISENSE(1+RPROGRAM((1/RHIGHtc)−(1/RLOWtc))).
Claims (52)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US11/488,927 USRE40915E1 (en) | 2001-12-14 | 2006-07-18 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter |
US12/426,884 USRE42037E1 (en) | 2001-12-14 | 2009-04-20 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter |
Applications Claiming Priority (3)
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US34032401P | 2001-12-14 | 2001-12-14 | |
US10/304,245 US6765372B2 (en) | 2001-12-14 | 2002-11-26 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC Converter |
US11/488,927 USRE40915E1 (en) | 2001-12-14 | 2006-07-18 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter |
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US10/304,245 Reissue US6765372B2 (en) | 2001-12-14 | 2002-11-26 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC Converter |
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US10/304,245 Continuation US6765372B2 (en) | 2001-12-14 | 2002-11-26 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC Converter |
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USRE40915E1 true USRE40915E1 (en) | 2009-09-15 |
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US10/304,245 Ceased US6765372B2 (en) | 2001-12-14 | 2002-11-26 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC Converter |
US11/488,927 Expired - Lifetime USRE40915E1 (en) | 2001-12-14 | 2006-07-18 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter |
US12/426,884 Expired - Lifetime USRE42037E1 (en) | 2001-12-14 | 2009-04-20 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter |
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US10/304,245 Ceased US6765372B2 (en) | 2001-12-14 | 2002-11-26 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC Converter |
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US12/426,884 Expired - Lifetime USRE42037E1 (en) | 2001-12-14 | 2009-04-20 | Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter |
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US (3) | US6765372B2 (en) |
JP (1) | JP2005518174A (en) |
CN (2) | CN101335487A (en) |
AU (1) | AU2002366486A1 (en) |
DE (1) | DE10297493T5 (en) |
TW (1) | TWI232022B (en) |
WO (1) | WO2003052911A1 (en) |
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US7504816B2 (en) * | 2005-09-28 | 2009-03-17 | Intersil Americas Inc. | Circuit for multiplexing digital and analog information via single pin of driver for switched MOSFETs of DC-DC converter |
US7568117B1 (en) | 2005-10-03 | 2009-07-28 | Zilker Labs, Inc. | Adaptive thresholding technique for power supplies during margining events |
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Also Published As
Publication number | Publication date |
---|---|
AU2002366486A1 (en) | 2003-06-30 |
JP2005518174A (en) | 2005-06-16 |
AU2002366486A8 (en) | 2003-06-30 |
WO2003052911A1 (en) | 2003-06-26 |
WO2003052911A8 (en) | 2004-05-21 |
US20030111984A1 (en) | 2003-06-19 |
TW200304264A (en) | 2003-09-16 |
TWI232022B (en) | 2005-05-01 |
US6765372B2 (en) | 2004-07-20 |
CN1605148A (en) | 2005-04-06 |
CN101335487A (en) | 2008-12-31 |
USRE42037E1 (en) | 2011-01-18 |
CN100405722C (en) | 2008-07-23 |
DE10297493T5 (en) | 2004-12-23 |
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