USRE32708E - Semiconductor memory - Google Patents

Semiconductor memory Download PDF

Info

Publication number
USRE32708E
USRE32708E US06/252,786 US25278681A USRE32708E US RE32708 E USRE32708 E US RE32708E US 25278681 A US25278681 A US 25278681A US RE32708 E USRE32708 E US RE32708E
Authority
US
United States
Prior art keywords
data line
line portions
pair
word lines
memory cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US06/252,786
Inventor
Kiyoo Itoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of USRE32708E publication Critical patent/USRE32708E/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • This invention relates to a random access type memory arrangement for a semiconductor memory.
  • a data line is divided into two halves, each of which has a plurality of memory cells and a dummy cell, and a differential amplifier is connected between the left half and the right half of the data line.
  • the contents of a desired memory cell connected to one data line half are read out and, at the same time, the contents of a dummy cell connected to the other data line half are also read out.
  • the voltage on either one of the data line halves is detected through a switching element.
  • An object of the invention is to provide a random access type semiconductor memory which can operate at a high speed and at a stable condition.
  • this invention is characterized by arranging the data line halves so as to be adjacent each other.
  • FIG. 1 is a diagram showing part of a circuit construction of a prior art memory.
  • FIG. 2 is a diagram showing the entire circuit construction of a prior art memory.
  • FIG. 3 is a diagram showing an embodiment of a semiconductor memory according to this invention.
  • FIGS. 4a to 4c are diagrams showing various embodiments of a memory cell arrangement according to this invention.
  • FIGS. 5a and 5b are respective plane and sectional views showing an embodiment of memory arrangement according to this invention.
  • FIG. 6 is a plane view showing another embodiment of memory arrangement according to this invention.
  • At least one memory cell MC 0 and a dummy memory cell DM 0 are connected to the left half D 0 of a data line and at least one memory cell MC 1 and a dummy memory cell DM 1 are connected to the right half D 0 of a data line.
  • These data line halves D 0 and D 0 are connected to a pre-amplifier PA 0 using a differential amplifier.
  • Each of the memory cells MC 0 , MC 1 , DM 0 and DM 1 comprises a MOS (metal-oxide-semiconductor) transistor Q and a capacitor C 0 .
  • the gates of the MOS transistors Q in the memory cells MC 0 and DM 0 are connected to word lines W 0 and DW 0 which are orthogonal to data line half D 0 .
  • the gates of the MOS transistors Q in memory cells MC 1 and DM 1 are connected to word lines W 1 and DW 1 which are orthogonal to data line half D 0 .
  • MOS transistors Q in memory cells MC 0 , DM 0 and CM 0 , DM 1 are connected to data line halves D 0 and D 0 , respectively.
  • the capacitors C 0 in the respective memory cells are connected between the sources of the respective transistors Q and ground.
  • the preamplifier PA 0 has a pair of cross-coupled MOS transistors Q P1 and Q P2 connected between the data line halves D 0 and D 0 and MOS transistors Q P3 to Q P5 .
  • the drains and gates of MOS transistors Q P3 and Q P4 are connected to a power supply terminal V DD and a set signal terminal S 1 , respectively, and the sources thereof are connected to the drains of MOS transistors Q P1 and Q P2 .
  • the gate and source of MOS transistor Q P5 are connected to a set signal terminal S 2 and ground, respectively, and the drain thereof is connected to the sources of MOS transistors Q P1 and Q P2 .
  • pulses are applied to the corresponding work line W 0 and dummy word line DW 1 orthogonal to data line half D 0 .
  • Small signals on the data line halves D 0 and D 0 which have different valves with respect to each other are applied to the pre-amplifier PA 0 .
  • the small signals are amplified by the pre-amplifier PA 0 when the set signal is applied to terminals S 1 and S 2 .
  • an amplified signal on one of the data line halves D 0 and D 0 is detected, thereby detecting the information ("1" or "0") of a desired memory cell MC 0 .
  • the voltage across capacitor C 0 in dummy cell DM 1 is a voltage intermediate an information "1" voltage and an information "0" voltage across capacitor C 0 in memory cell MC 0 . Therefore, signal read out from dummy cell DM 1 to data line half D 0 has a value intermediate information "1" and "0" signals read out from memory cell MC 1 to data line half D 0 . Output signals which are of different polarities with respect to each other are obtained by the pre-amplifier PA 0 in response to the difference between signals on the data line halves D 0 and D 0 .
  • FIG. 2 shows a circuit of a large scale integrated (LSI) memory which employs the random access type memory circuit shown in FIG. 1.
  • LSI large scale integrated
  • MC 0 to MC 63 represent memory cells, DM 0 and DM 1 dummy cells, W 0 to W 63 and DW 0 and DW 1 word lines, D 0 to D 63 and D 0 to D 63 data line halves, A 0 to A 63 address signal terminals, MA a main amplifier, T 0 an output terminal, Q 0 to Q 63 MOS transistors and WD a word driving circuit.
  • address signals A 0 to A 63 are selectively applied to the gates of MOS transistors Q 0 to Q 63 .
  • MOS transistor Q 0 is made conductive by a signal from terminal A 0 . Therefore, a signal on data line half D 0 is applied to the main amplifier MA and an amplified signal is derived from the output terminal T 0 .
  • the contents of the memory cells MC 0 to MC 63 are read out by word signals on the word lines W 0 to W 63 .
  • the contents of dummy cell DM 0 or DM 1 are read out by a word signal on word line DW 0 or DW 1 .
  • These word signals are supplied from the word driving circuit WD. For example, when the information stored in memory cell MC 62 is read out, word signals are applied to word lines W 62 and DW 1 .
  • the prior art memory shown in FIGS. 1 and 2 has the following disadvantages.
  • FIG. 3 shows an embodiment of circuit construction of a semiconductor memory random access type according to this invention.
  • a pair of data line halves D 0 and D 0 are arranged at adjacent positions and in parallel.
  • Each of the memory cells MC 0 to MC 63 is connected between one of the word lines W 0 to W 63 which are orthogonal to the data line halves D 0 and D 0 and one of the data line halves D 0 and D 0 . That is, a memory cell is connected to only one of the cross points between each of the word lines W 0 to W 63 and the data line halves.
  • Memory cells MC 1 to MC 62 (even number) are connected between word lines W 0 to W 62 (even number) and data line half D 0 and memory cell MC 1 to MC 63 (odd number) are connected between word lines W 1 to W 63 (odd number) and data line half D 0 .
  • a dummy memory cell DM 0 is connected between a word line DW 0 and data line half D 0 and a dummy memory cell DM 1 is connected between a word line DW 1 and data line half D 0 .
  • the data line halves D 0 and D 0 are connected to a pre-amplifier, such as PA 0 shown in FIG. 1 and are further connected to the main amplifier MA through MOS transistors Q 0 and Q 0 , respectively.
  • An address signal from terminal A 0 is applied to MOS transistors Q 0 and Q 0 .
  • word signals are applied to memory cell MC 63 and dummy cell DM 0 which is connected to data line half D 0 .
  • Signals on the data line halves D 0 and D 0 are applied to the pre-amplifier PA 0 .
  • Signals amplified differentially by the pre-amplifier PA 0 are applied through transistors Q 0 and Q 0 to the main amplifier MA using a differential amplifier at the application of the address signal from terminal A 0 .
  • a signal amplified differentially by the main amplifier MA is derived from the output terminal T 0 .
  • FIGS. 4a to 4c show various embodiments of a random access type memory cell arrangement according to this invention.
  • a circle represents the presence of a memory cell and an X represents the absence of a memory cell.
  • Memory cells are arranged alternately one by one on the data line halves D 0 and D 0 in FIG. 4a. Memory cells are arranged alternately in pairs on the data line halves D 0 and D 0 in FIG. 4b. Furthermore, memory cells are arranged alternately in fours on the data line halves D 0 and D 0 in FIG. 4c.
  • FIG. 5a shows a plane view of an embodiment of a random access type memory arrangement according to the invention for realizing the memory arrangement shown in FIG. 4b by means of a silicon gate.
  • FIG. 5b shows a sectional view along line Vb-Vb' in FIG. 5a.
  • CP represents a storage capacitor forming electrode for forming storage capacitors C 0 in the memory cells.
  • 400 and 410 represent the drain and source (or source and drain) of transistor Q shown in FIG. 1, which are formed in a silicon substrate 600.
  • 100 represents a contact part between the data line halves D 0 , D 0 , etc., and a diffusion layer 400 forming a drain (or source).
  • 200 represents an insulating layer for separating word line W 59 from data line half D 1 .
  • Electrodes CP and word lines W 58 , W 59 , etc. are formed of polysilicon and data line halves D 0 , D 0 , etc. are formed of aluminum.
  • the storage capacitor C 0 is formed between a channel 500 and an electrode CP when a high voltage is applied to the electrode CP.
  • transistor Q comprising drain 400 and source 410 connected to the cross point between word line W 60 and data line half D 0 is made conductive. Therefore, the storing voltage of the storage capacitor C 0 beneath the data line half D 0 is read out so that this voltage is divided by the capacitance of the data line half D 0 and the storage capacitor C 0 . The storing voltage of the storage capacitor C 0 beneath the data line half D 0 is not read out, since there is no transistor connected to the cross point between word line W 60 and data line half D 0 . The voltage from a dummy cell (not shown in the figure) is present on data line half D 0 .
  • FIG. 6 shows a plane view of another embodiment of a random access type memory arrangement according to this invention for realizing the memory arrangement in FIG. 4c by means of a silicone gate.
  • FIG. 6 Since the construction and operation of a random access type memory arrangement shown in FIG. 6 are similar to those of memory arrangement shown in FIG. 5a except that memory cells are arranged alternately four by four on the data line halves D 0 and D 0 , a detailed description thereof will be omitted.
  • both signals on the data line halves D 0 and D 0 are differentially applied through MOS transistors Q 0 and Q 0 to the main amplifier, it is possible to detect the contents of a desired memory cell at a high speed.
  • the pre-amplifier PA 0 which has an area far greater than that of a memory cell, must be arranged between the data line halves D 0 and D 0 . Therefore, it is difficult to arrange such a pre-amplifier so as to maintain a desired pitch of a data line.
  • a memory of the invention shown in FIG. 3 since a pair of data line halves D 0 and D 0 are arranged in parallel on one side of pre-amplifier PA 0 , such a pre-amplifier can be arranged so as to maintain a desired pitch of a data line.
  • the pre-amplifier PA 0 may be arranged between MOS transistors Q 0 and Q 0 and the main amplifier MA. Furthermore, it can be arranged on the left terminal side, that is, the word line W 63 side. In such a case, it is possible to obviate the concentration of the control circuits (PA 0 , Q 0 , etc.), which arrangement is relatively difficult, on one side.
  • the pre-amplifiers which are provided for every pair of data line halves, may be arranged alternately on one side and the other sides.
  • each of the memory cells MC 0 to MC 63 , DM 0 and DM 1 can be constituted by a memory cell of various types in lieu of a circuit shown in FIG. 1.
  • dummy memory cells DM 0 and DM 1 can be eliminated since the data line halves D 0 and D 0 are arranged in parallel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

A random access type semiconductor memory comprises a pair of data line halves arranged in parallel, a plurality of word lines orthogonal to the data line halves, a multiplicity of memory cells, each of which is arranged at either one of the cross points between the data line halves and each of the word lines, a differential amplifier to which signals on the data line halves are differentially applied, and a main amplifier to which output signals on the data line halves are differentially applied, thereby detecting the content of a desired memory cell.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a random access type memory arrangement for a semiconductor memory.
2. Description of the Prior Art
In a prior art random access type semiconductor memory, a data line is divided into two halves, each of which has a plurality of memory cells and a dummy cell, and a differential amplifier is connected between the left half and the right half of the data line. The contents of a desired memory cell connected to one data line half are read out and, at the same time, the contents of a dummy cell connected to the other data line half are also read out. The voltage on either one of the data line halves is detected through a switching element.
However, such a prior art memory has the following disadvantages.
Since only the voltage on one of the digit line halves is detected, it is impossible to read out the data at a high speed and there is the possibility of erroneously detecting the contents of a memory cell due to an electrical imbalance of the data line halves.
Since the data line halves are not geometrically adjacent each other, unbalanced noise signals are produced on the data line halves, thereby causing the differential amplifier to operate erroneously.
SUMMARY OF THE INVENTION
An object of the invention is to provide a random access type semiconductor memory which can operate at a high speed and at a stable condition.
In order to attain such an object, this invention is characterized by arranging the data line halves so as to be adjacent each other.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing part of a circuit construction of a prior art memory.
FIG. 2 is a diagram showing the entire circuit construction of a prior art memory.
FIG. 3 is a diagram showing an embodiment of a semiconductor memory according to this invention.
FIGS. 4a to 4c are diagrams showing various embodiments of a memory cell arrangement according to this invention.
FIGS. 5a and 5b are respective plane and sectional views showing an embodiment of memory arrangement according to this invention.
FIG. 6 is a plane view showing another embodiment of memory arrangement according to this invention.
DETAILED DESCRIPTION OF THE PRIOR ART
At least one memory cell MC0 and a dummy memory cell DM0 are connected to the left half D0 of a data line and at least one memory cell MC1 and a dummy memory cell DM1 are connected to the right half D0 of a data line. These data line halves D0 and D0 are connected to a pre-amplifier PA0 using a differential amplifier.
Each of the memory cells MC0, MC1, DM0 and DM1 comprises a MOS (metal-oxide-semiconductor) transistor Q and a capacitor C0. The gates of the MOS transistors Q in the memory cells MC0 and DM0 are connected to word lines W0 and DW0 which are orthogonal to data line half D0. The gates of the MOS transistors Q in memory cells MC1 and DM1 are connected to word lines W1 and DW1 which are orthogonal to data line half D0. The drains of MOS transistors Q in memory cells MC0, DM0 and CM0, DM1 are connected to data line halves D0 and D0, respectively. The capacitors C0 in the respective memory cells are connected between the sources of the respective transistors Q and ground.
The preamplifier PA0 has a pair of cross-coupled MOS transistors QP1 and QP2 connected between the data line halves D0 and D0 and MOS transistors QP3 to QP5. The drains and gates of MOS transistors QP3 and QP4 are connected to a power supply terminal VDD and a set signal terminal S1, respectively, and the sources thereof are connected to the drains of MOS transistors QP1 and QP2. The gate and source of MOS transistor QP5 are connected to a set signal terminal S2 and ground, respectively, and the drain thereof is connected to the sources of MOS transistors QP1 and QP2.
In operation, where the contents of memory cell MC0 connected to data line half D0 are read out, pulses are applied to the corresponding work line W0 and dummy word line DW1 orthogonal to data line half D0. Small signals on the data line halves D0 and D0 which have different valves with respect to each other are applied to the pre-amplifier PA0. The small signals are amplified by the pre-amplifier PA0 when the set signal is applied to terminals S1 and S2.
Furthermore, an amplified signal on one of the data line halves D0 and D0 is detected, thereby detecting the information ("1" or "0") of a desired memory cell MC0.
In detail, the voltage across capacitor C0 in dummy cell DM1 is a voltage intermediate an information "1" voltage and an information "0" voltage across capacitor C0 in memory cell MC0. Therefore, signal read out from dummy cell DM1 to data line half D0 has a value intermediate information "1" and "0" signals read out from memory cell MC1 to data line half D0. Output signals which are of different polarities with respect to each other are obtained by the pre-amplifier PA0 in response to the difference between signals on the data line halves D0 and D0.
FIG. 2 shows a circuit of a large scale integrated (LSI) memory which employs the random access type memory circuit shown in FIG. 1.
In FIG. 2, MC0 to MC63 represent memory cells, DM0 and DM1 dummy cells, W0 to W63 and DW0 and DW1 word lines, D0 to D63 and D0 to D63 data line halves, A0 to A63 address signal terminals, MA a main amplifier, T0 an output terminal, Q0 to Q63 MOS transistors and WD a word driving circuit.
In order to detect signals on data line halves D0 to D63, address signals A0 to A63 are selectively applied to the gates of MOS transistors Q0 to Q63. For example, when a signal on data line half D0 is detected, MOS transistor Q0 is made conductive by a signal from terminal A0. Therefore, a signal on data line half D0 is applied to the main amplifier MA and an amplified signal is derived from the output terminal T0.
The contents of the memory cells MC0 to MC63 are read out by word signals on the word lines W0 to W63. At the same time, the contents of dummy cell DM0 or DM1 are read out by a word signal on word line DW0 or DW1. These word signals are supplied from the word driving circuit WD. For example, when the information stored in memory cell MC62 is read out, word signals are applied to word lines W62 and DW1.
The prior art memory shown in FIGS. 1 and 2 has the following disadvantages.
1. Since only a signal on either one of data line halves D0 and D0 is amplified by the main amplifier MA, it is impossible to detect the contents of a desired memory cell at a high speed.
2. There is the possibility of erroneously detecting the contents of a desired memory cell by an electrical imbalance of data line halves D0 and D0.
3. Since the data line halves D0 and D0 are geometrically separated from each other, unbalanced noise signals are produced on the data line halves D0 and D0. Therefore, there is the possibility that the pre-amplifier PA0 will operate erroneously.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 shows an embodiment of circuit construction of a semiconductor memory random access type according to this invention.
In FIG. 3, a pair of data line halves D0 and D0 are arranged at adjacent positions and in parallel.
Each of the memory cells MC0 to MC63 is connected between one of the word lines W0 to W63 which are orthogonal to the data line halves D0 and D0 and one of the data line halves D0 and D0. That is, a memory cell is connected to only one of the cross points between each of the word lines W0 to W63 and the data line halves. Memory cells MC1 to MC62 (even number) are connected between word lines W0 to W62 (even number) and data line half D0 and memory cell MC1 to MC63 (odd number) are connected between word lines W1 to W63 (odd number) and data line half D0. Furthermore, a dummy memory cell DM0 is connected between a word line DW0 and data line half D0 and a dummy memory cell DM1 is connected between a word line DW1 and data line half D0. The data line halves D0 and D0 are connected to a pre-amplifier, such as PA0 shown in FIG. 1 and are further connected to the main amplifier MA through MOS transistors Q0 and Q0, respectively. An address signal from terminal A0 is applied to MOS transistors Q0 and Q0.
Signals on other data line halves connected in common to common data lines CD and CD are also applied to the main amplifier MA.
When the contents of a desired memory cell, for example, MC63, are read out, word signals are applied to memory cell MC63 and dummy cell DM0 which is connected to data line half D0. Signals on the data line halves D0 and D0 are applied to the pre-amplifier PA0. Signals amplified differentially by the pre-amplifier PA0 are applied through transistors Q0 and Q0 to the main amplifier MA using a differential amplifier at the application of the address signal from terminal A0. A signal amplified differentially by the main amplifier MA is derived from the output terminal T0.
Since a pair of data line halves D0 and D0 are arranged in parallel and both signals on the data line halves D0 and D0 are applied through MOS transistors Q0 and Q0 to the main amplifier MA, it is possible to maintain an electrical balance of the data line halves D0 and D0.
FIGS. 4a to 4c show various embodiments of a random access type memory cell arrangement according to this invention.
In these figures, a circle represents the presence of a memory cell and an X represents the absence of a memory cell. Memory cells are arranged alternately one by one on the data line halves D0 and D0 in FIG. 4a. Memory cells are arranged alternately in pairs on the data line halves D0 and D0 in FIG. 4b. Furthermore, memory cells are arranged alternately in fours on the data line halves D0 and D0 in FIG. 4c.
FIG. 5a shows a plane view of an embodiment of a random access type memory arrangement according to the invention for realizing the memory arrangement shown in FIG. 4b by means of a silicon gate.
FIG. 5b shows a sectional view along line Vb-Vb' in FIG. 5a. In these figures, CP represents a storage capacitor forming electrode for forming storage capacitors C0 in the memory cells. 400 and 410 represent the drain and source (or source and drain) of transistor Q shown in FIG. 1, which are formed in a silicon substrate 600.
100 represents a contact part between the data line halves D0, D0, etc., and a diffusion layer 400 forming a drain (or source). 200 represents an insulating layer for separating word line W59 from data line half D1.
Electrodes CP and word lines W58, W59, etc. are formed of polysilicon and data line halves D0, D0, etc. are formed of aluminum.
In a N-channel MOS, the storage capacitor C0 is formed between a channel 500 and an electrode CP when a high voltage is applied to the electrode CP.
In such an arrangement, when pulse voltages are applied to a word line, for example, W60, transistor Q comprising drain 400 and source 410 connected to the cross point between word line W60 and data line half D0 is made conductive. Therefore, the storing voltage of the storage capacitor C0 beneath the data line half D0 is read out so that this voltage is divided by the capacitance of the data line half D0 and the storage capacitor C0. The storing voltage of the storage capacitor C0 beneath the data line half D0 is not read out, since there is no transistor connected to the cross point between word line W60 and data line half D0. The voltage from a dummy cell (not shown in the figure) is present on data line half D0.
FIG. 6 shows a plane view of another embodiment of a random access type memory arrangement according to this invention for realizing the memory arrangement in FIG. 4c by means of a silicone gate.
Since the construction and operation of a random access type memory arrangement shown in FIG. 6 are similar to those of memory arrangement shown in FIG. 5a except that memory cells are arranged alternately four by four on the data line halves D0 and D0, a detailed description thereof will be omitted.
In these embodiments, it is also possible to use aluminum in lieu of polysilicon as the word lines.
According to the memory arrangement of the invention shown in FIGS. 3 and 4, the following advantages are obtained.
1. Since both signals on the data line halves D0 and D0 are differentially applied through MOS transistors Q0 and Q0 to the main amplifier, it is possible to detect the contents of a desired memory cell at a high speed.
2. Since there is no electrical imbalance of the data line halves D0 and D0, the contents of a desired memory cell are correctly detected.
3. Since the data line halves D0 and D0 are geometrically adjacent each other, no imbalance noise signals are produced on the data line halves D0 and D0. Therefore, the pre-amplifier MA operates correctly.
4. In the prior art memory shown in FIGS. 1 and 2, the pre-amplifier PA0, which has an area far greater than that of a memory cell, must be arranged between the data line halves D0 and D0. Therefore, it is difficult to arrange such a pre-amplifier so as to maintain a desired pitch of a data line. However, in a memory of the invention shown in FIG. 3, since a pair of data line halves D0 and D0 are arranged in parallel on one side of pre-amplifier PA0, such a pre-amplifier can be arranged so as to maintain a desired pitch of a data line.
In FIG. 3, the pre-amplifier PA0 may be arranged between MOS transistors Q0 and Q0 and the main amplifier MA. Furthermore, it can be arranged on the left terminal side, that is, the word line W63 side. In such a case, it is possible to obviate the concentration of the control circuits (PA0, Q0, etc.), which arrangement is relatively difficult, on one side.
If necessary, the pre-amplifiers, which are provided for every pair of data line halves, may be arranged alternately on one side and the other sides.
Thus, it is possible to remarkably increase the freedom of the memory arrangement.
In FIG. 3, various differential amplifiers can be used as the pre-amplifier PA0. Each of the memory cells MC0 to MC63, DM0 and DM1 can be constituted by a memory cell of various types in lieu of a circuit shown in FIG. 1.
Furthermore, according to the invention, dummy memory cells DM0 and DM1 can be eliminated since the data line halves D0 and D0 are arranged in parallel.

Claims (20)

I claim:
1. A semiconductor memory comprising:
at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines orthogonally crossing over said data line portions;
a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data;
a differential amplifier to which signals on said pair of data line portions are respectively applied; .[.and.].
means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions.[...]..Iadd.;
a pair of second word lines orthogonally crossing over said data line portions;
a first dummy memory cell coupled to one of the data line portions of said pair of data line portions and one of said second word lines at the cross point thereof; and
a second dummy memory cell coupled to the other of the data line portions of said pair of data line portions and the other of said second word lines at the cross point thereof, wherein deriving signals are applied to one of said first word line and one of said pair of second word lines at the same time, so that data from one of said multiplicity of memory cells and one of said dummy memory cells are, respectively, read out on one and the other of said pair data line portions, at the same time. .Iaddend. .[.2. A semiconductor memory according to claim 1, further comprising,
a pair of second word lines orthogonally crossing over said data line portions;
a first dummy memory cell coupled to one of the data line portions of said pair of data line portions and one of said second word lines at the cross point thereof, and
a second dummy memory cell coupled to the other of the data line portions of said pair of data line portions and the other of said second word lines at the cross point thereof..]. .[.3. A semiconductor memory according to claim 1, wherein said output signal deriving means comprises
a pair of switching elements connected to said data line portions and
a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively
applied through said pair of switching elements..]. 4. A semiconductor memory according to claim 3, wherein said switching elements comprise a pair of transistors, each having an input terminal connected to a respective data line portion, an output terminal connected to said second differential amplifer, and a control terminal to which a control signal is
applied. .[.5. A semiconductor memory according to claim 1, wherein each of said memory cells comprises a metal-oxide-semiconductor transistor and a storage capacitor connected therewith..]. .[.6. A semiconductor memory according to claim 1, wherein, for each of said data line portions, the memory cells coupled thereto are coupled, alternately, to every other word line..]. .[.7. A semiconductor memory according to claim 1, wherein, for each of said data line portions, the memory cells coupled thereto are coupled in alternate pairs of adjacent word lines..]. .[.8. A semiconductor memory according to claim 1, wherein for each of said data line portions, the memory cells coupled thereto are coupled in alternate groups of four of adjacent word lines..]. .[.9. A semiconductor memory according to claim 1, wherein said memory cells are coupled to said data line portions and said word lines so that the electrical characteristics of said data line portions are balanced with respect to each other..]. .[.10. A semiconductor memory according to claim 1, wherein the number of memory cells connected to one of the data line portions of said pair of data line portions is equal to the number of memory cells connected to the other of the data line portions of said pair of data line portions..].
A semiconductor memory according to claim .[.3.]. .Iadd.2.Iaddend., further comprising
a pair of second word lines orthogonally crossing over said data line portions;
a first dummy memory cell coupled to one of the data line portions of said pair of data line portions and one of said second word lines at the cross point thereof; and
a second dummy memory cell coupled to the other of the data line portions of said pair of data line portions and the other of said second word lines
at the cross point thereof. 12. A semiconductor memory according to claim 11, wherein said switching elements comprise a pair of transistors, each having an input terminal connected to a respective data line portion, an output terminal connected to said second differential amplifier, and a control terminal to which a control signal is applied. .[.13. A semiconductor memory according to claim 1, wherein said data line portions are formed of aluminum and said first word lines are formed of
polysilicon..]. 14. A random access semiconductor memory comprising:
first and second data line portions disposed parallel and adjacent to each other.Iadd..Iaddend.;
a plurality of first word lines orthgonally crossing over each of said data line portions;
a plurality of memory cells, disposed at the cross points of said first word lines and one of said data line portions, each of which memory cells is capable of storing selected information to be written therein and is capable of reading out information stored therein, each memory cell having an address terminal connected to a respective word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to one of said data line portions;
a differential amplifier connected to each of said data line portions for differentially amplifying signals supplied thereby;
means, connected to said differential amplifier and said data line portions; for deriving output signals representative of signals on said pair of data line portions;
a pair of second word lines orthogonally crossing over each of said data line portions;
a first dummy memory cell, disposed at the crosspoint of one of said second word lines and said first data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said one of said second word lines, and having a data terminal connected to said first data line portion; and
a second dummy memory cell, disposed at the crosspoint of the other of said second word lines and said second data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said other of said second word lines, and having a data terminal connected to said second data line portion.Iadd., wherein driving signals are applied to one of said first word lines and one of said second word lines, at the same time, so that data from one of said plurality of memory cells and one of said dummy memory cells are, respectively read out on one and the other of said data line portions, at the same time. .Iaddend.
.[. . A random access semiconductor memory according to claim 14, wherein said output signal deriving means comprises
a pair of switching elements connected to said data line portions and
a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively
applied through said pair of switching elements..]. 16. A semiconductor memory according to claim 15, wherein each of said memory cells comprises a metal-oxide-semiconductor transistor and a storage capacitor connected
therewith. 17. A semiconductor memory according to claim 16, wherein said switching elements comprise a pair of transistors, each having an input terminal connected to a respective data line portion, an output terminal connected to said second differential amplifier, and a control terminal to
which a control signal is applied. .Iadd.18. A semiconductor memory comprising:
at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines orthogonally crossing over said data line portions;
a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data;
a first differential amplifier to which signals on said pair of data line portions are respectively applied;
means, connected to said first differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions and said output signal deriving means having:
a pair of switching elements connected to said data line portions; and
a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively
applied through said pair of switching elements. .Iaddend. .Iadd.19. A semiconductor memory comprising:
at least a pair of data line portions formed of aluminum arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines formed of polysilicon orthogonally crossing over said data line portions;
a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data;
a differential amplifier to which signals on said pair of data line portions are respectively applied; and
means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions. .Iaddend. .Iadd.20. A semiconductor memory comprising:
at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines orthogonally crossing over said data line portions;
a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data, said memory cells coupled such that pairs of cells coupled to adjacent word lines are alternately coupled to one and the other of said pair of data lines;
a differential amplifier to which signals on said pair of data line portions are respectively applied; and
means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions. .Iaddend. .Iadd.21. A semiconductor memory comprising:
at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines orthogonally crossing over said data line portions;
a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data, the memory cells of said data line portions, said memory cells coupled such that groups of four cells coupled to four adjacent word lines are alternately coupled to one and the other of said pair of data lines;
a differential amplifier to which signals on said pair of data line portions are respectively applied; and
means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said
pair of data line portions. .Iaddend. .Iadd.22. A semiconductor memory comprising:
at least two pairs of data line portions arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines orthogonally crossing over said data line portions;
a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data;
first and second differential amplifiers to which signals on said two pairs of data line portions are respectively applied, one of said differential amplifiers connected to one side of an arrangement formed by said data line portions and the other differential amplifier connected to the other side thereof; and
means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions. .Iaddend. .Iadd.23. A semiconductor memory comprising:
at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines orthogonally crossing over said data line portions;
a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data, the memory cells of said data line portions, said memory cells coupled such that pairs of cells coupled to adjacent word lines are alternately coupled to one and the other of said pair of data lines;
a differential amplifier to which signals on said pair of data line portions are respectively applied; and
each of said memory cells being a metal-oxide semiconductor transistor having an input electrode, an output electrode and a gate electrode, the respective output electrodes of two MOS transistors in two adjacent memory cells being connected at the same location to one data line portion and the respective gate electrodes thereof being connected to two respective adjacent word lines. .Iaddend. .Iadd.24. A semiconductor memory comprising:
at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines orthogonally crossing over said data line portions;
a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data;
a differential amplifier to which signals on said pair of data line portions are respectively applied;
means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions; and
each of said memory cells comprising a metal-oxide semiconductor transistor with source drain and gate regions, the direction of the channel formed between the source and drain regions of said MOS transistor being parallel
to the direction of said data line portions. .Iaddend. .Iadd.25. A semiconductor memory comprising:
at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines orthogonally crossing over said data line portions;
a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data;
a differential amplifier to which signals on said pair of data line portions are respectively applied;
means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions; and
each of said memory cells comprising a metal-oxide-semiconductor transistor having a gate electrode with the gate electrode of said MOS transistor in each memory cell formed by a portion of one of said first word lines. .Iaddend. .Iadd.26. A semiconductor memory comprising:
at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines orthogonally crossing over said data line portions;
a multiplicity of memory cells, formed at said surface, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data;
a differential amplifier to which signals on said pair of data line portions are respectively applied;
means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions;
said output signal deriving means comprising a pair of switching elements connected to said data line portions and a pair of common data lines
connected to said pair of switching elements. .Iaddend. .Iadd.27. A random access semiconductor memory comprising:
first and second data line portions disposed parallel and adjacent to each other;
a pluraltiy of first word lines orthogonally crossing over each of said data line portions;
a plurality of memory cells, disposed at the cross points of said first word lines and one of said data line portions, each of which memory cells is capable of storing selected information to be written therein and is capable of reading out information stored therein, each memory cell having an address terminal connected to a respective word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to one of said data line portions;
a differential amplifier connected to each of said data line portions for differentially amplifying signals supplied thereby;
means, connected to said differential amplifier and said data line portions for deriving output signals representative of signals on said pair of data line portions comprising:
a pair of switching elements connected to said data line portions, and
a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively amplified though said pair of switching elements;
pair of second word lines orthogonally crossing over each of said data line portions;
a first dummy memory cell, disposed at the crosspoint of one of said second word lines and said first data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein and having an address terminal connected to said one of said second word lines, and having a data terminal connected to said first data line portion; and
a second dummy memory cell, disposed at the crosspoint of the other of said second word lines and said second data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said other of said second word lines, and having a data terminal
connected to said second data line portion. .Iaddend. .Iadd.28. A semiconductor memory comprising:
at least a pair of data line portions formed of aluminum arranged in parallel with each other and at positions adjacent to each other;
a plurality of first word lines formed of polysilicon orthogonally crossing over said data line portions;
a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data for each of said data line portions, said memory cells coupled such that pairs of cells coupled to adjacent word lines are alternately coupled to one and the other of said pair of data lines;
a differential amplifier to which signals on said pair of data line portions are respectively applied;
means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said
pair of data line portions. .Iaddend. .Iadd.29. A semiconductor memory according to claim 22, wherein said differential amplifiers are arranged alternately on one side and the other side of the arrangement formed by said pairs of data line portions. .Iaddend. .Iadd.30. A semiconductor memory according to claim 24, wherein said data line portion overlaps said
channel as viewed in the vertical direction. .Iaddend. .Iadd.31. A semiconductor memory according to claim 1, wherein said pair of second word lines are arranged at positions adjacent to each other. .Iaddend. .Iadd.32. A semiconductor memory according to claim 18, wherein, for each of said data line portions, the memory cells coupled thereto are coupled in alternate pairs of adjacent word lines. .Iaddend. .Iadd.33. A semiconductor memory according to claim 18, wherein said data line portions are formed of aluminum and said first word lines are formed of
polysilicon. .Iaddend. .Iadd.34. A semiconductor memory according to claim 20, wherein each of said memory cells comprises a metal-oxide-semiconductor transistor, the respective output electrodes of two MOS transistors in two adjacent memory cells are connected at the same location to one data line portion, and the respective gate electrodes thereof are connected to two respective adjacent first word lines. .Iaddend. .Iadd.35. A semiconductor memory according to claim 34, wherein the direction of the channel formed between the source and drain regions of said MOS transistor is parallel to the direction of said data line portion. .Iaddend. .Iadd.36. A semiconductor memory according to claim 35, wherein said data line portion overlaps said channel as viewed in the vertical direction. .Iaddend. .Iadd.37. A semiconductor memory according to claim 34, wherein the gate electrode of said MOS transistor in each memory cell is formed by a portion of said first word line. .Iaddend. .Iadd.38. A semiconductor memory according to claim 34, further comprising
a pair of second word lines orthogonally crossing over said data line portions and being arranged at positions adjacent to each other;
a first dummy memory cell coupled to one of the data line portions and one of said second word lines at the cross point thereof; and
a second dummy memory cell coupled to the other of the data line portions of said pair of data line portions and the other of said second word lines
at the cross point thereof. .Iaddend. .Iadd.39. A semiconductor memory according to claim 19, wherein said output signal deriving means comprises a pair of switching elements connected to said data line portions and a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively applied through said pair of switching elements, and the memory cells coupled to said data line portions are coupled in alternate pairs of adjacent word lines for each of said data line portions. .Iaddend. .Iadd.40. A semiconductor memory according to claim 19, wherein each of said memory cells is formed at a surface portion of a semiconductor body having one conductivity type and has a semiconductor region being formed in said surface portion and having the opposite conductivity type to said semiconductor body, said first word lines are formed on an insulator disposed on said body, and each of said data line portions has a first portion thereof being contact with said semiconductor region, and a second portion thereof insulated from both said body and said first word lines. .Iaddend. .Iadd.41. A semiconductor memory according to claim 26, wherein said output signal deriving means further comprises another differential amplifier connected to said pair of data lines, to which the signals on said data line portions are selectively applied through said pair of
switching elements. .Iaddend. .Iadd.42. A semiconductor memory according to claim 26, wherein each of said switching elements comprises a MOS transistor having source and drain regions, and each of said pair of data line portions is connected through the channel formed between the source and drain regions of said transistor to each of said pair of data lines. .Iaddend.
US06/252,786 1974-12-25 1981-04-10 Semiconductor memory Expired - Lifetime USRE32708E (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP49-148056 1974-12-25
JP14805674A JPS5539073B2 (en) 1974-12-25 1974-12-25

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US05/645,306 Reissue US4044340A (en) 1974-12-25 1975-12-29 Semiconductor memory

Publications (1)

Publication Number Publication Date
USRE32708E true USRE32708E (en) 1988-07-05

Family

ID=15444168

Family Applications (2)

Application Number Title Priority Date Filing Date
US05/645,306 Ceased US4044340A (en) 1974-12-25 1975-12-29 Semiconductor memory
US06/252,786 Expired - Lifetime USRE32708E (en) 1974-12-25 1981-04-10 Semiconductor memory

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US05/645,306 Ceased US4044340A (en) 1974-12-25 1975-12-29 Semiconductor memory

Country Status (2)

Country Link
US (2) US4044340A (en)
JP (1) JPS5539073B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4984214A (en) * 1989-12-05 1991-01-08 International Business Machines Corporation Multiplexed serial register architecture for VRAM
US5134616A (en) * 1990-02-13 1992-07-28 International Business Machines Corporation Dynamic ram with on-chip ecc and optimized bit and word redundancy
US5307356A (en) * 1990-04-16 1994-04-26 International Business Machines Corporation Interlocked on-chip ECC system
US5581567A (en) * 1991-08-14 1996-12-03 International Business Machines Corporation Dual level error detection and correction employing data subsets from previously corrected data

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128236A (en) * 1975-04-30 1976-11-09 Nec Corp A memory circuit
US4025907A (en) * 1975-07-10 1977-05-24 Burroughs Corporation Interlaced memory matrix array having single transistor cells
JPS538528A (en) * 1976-07-12 1978-01-26 Nec Corp Memory circuit
JPS5325323A (en) * 1976-08-23 1978-03-09 Hitachi Ltd Pre-sense amplifier
JPS6041463B2 (en) * 1976-11-19 1985-09-17 株式会社日立製作所 dynamic storage device
US4147960A (en) * 1976-12-06 1979-04-03 Fujitsu Limited Plasma display panel including shift channels and method of operating same
JPS615677Y2 (en) * 1976-12-29 1986-02-20
JPS5399736A (en) * 1977-02-10 1978-08-31 Toshiba Corp Semiconductor memory unit
JPS53134337A (en) * 1977-03-25 1978-11-22 Hitachi Ltd Sense circuit
JPS586230B2 (en) * 1977-06-08 1983-02-03 沖電気工業株式会社 semiconductor memory circuit
DE2740154A1 (en) * 1977-09-06 1979-03-15 Siemens Ag MONOLITHICALLY INTEGRATED SEMI-CONDUCTOR ARRANGEMENT
DE2740113A1 (en) * 1977-09-06 1979-03-15 Siemens Ag MONOLITHICALLY INTEGRATED SEMI-CONDUCTOR MEMORY
DE2743662A1 (en) * 1977-09-28 1979-04-05 Siemens Ag A TRANSISTOR MEMORY ELEMENT AND METHOD FOR ITS MANUFACTURING
JPS55150188A (en) * 1979-05-10 1980-11-21 Nec Corp Memory circuit
JPS5683891A (en) * 1979-12-13 1981-07-08 Fujitsu Ltd Semiconductor storage device
JPS5942399B2 (en) * 1979-12-21 1984-10-15 株式会社日立製作所 memory device
US4319342A (en) * 1979-12-26 1982-03-09 International Business Machines Corporation One device field effect transistor (FET) AC stable random access memory (RAM) array
USRE32236E (en) * 1979-12-26 1986-08-26 International Business Machines Corporation One device field effect transistor (FET) AC stable random access memory (RAM) array
JPS5836503B2 (en) * 1980-01-25 1983-08-09 株式会社東芝 semiconductor memory device
US4287576A (en) * 1980-03-26 1981-09-01 International Business Machines Corporation Sense amplifying system for memories with small cells
JPS5611687A (en) * 1980-06-02 1981-02-05 Fujitsu Ltd Semiconductor memory unit
JPS5784149A (en) * 1980-11-14 1982-05-26 Hitachi Ltd Semiconductor integrated circuit device
JPS57111061A (en) * 1980-12-26 1982-07-10 Fujitsu Ltd Semiconductor memory unit
JPS57208691A (en) * 1981-06-15 1982-12-21 Mitsubishi Electric Corp Semiconductor memory
JPS6059677B2 (en) * 1981-08-19 1985-12-26 富士通株式会社 semiconductor storage device
JPS58111183A (en) * 1981-12-25 1983-07-02 Hitachi Ltd Dynamic ram integrated circuit device
US4493056A (en) * 1982-06-30 1985-01-08 International Business Machines Corporation RAM Utilizing offset contact regions for increased storage capacitance
JPS595489A (en) * 1982-07-02 1984-01-12 Toshiba Corp Semiconductor memory
JPS5960793A (en) * 1982-09-30 1984-04-06 Fujitsu Ltd Semiconductor memory
JPS5979488A (en) * 1982-10-28 1984-05-08 Nec Corp Mos memory circuit
JPS59203298A (en) * 1983-05-04 1984-11-17 Nec Corp Semiconductor memory
US4739475A (en) * 1983-09-20 1988-04-19 Mensch Jr William D Topography for sixteen bit CMOS microprocessor with eight bit emulation and abort capability
JPS59188889A (en) * 1984-03-28 1984-10-26 Hitachi Ltd Semiconductor memory
JPS6074196A (en) * 1984-04-27 1985-04-26 Nec Corp Memory circuit
JPS62150879A (en) * 1985-12-25 1987-07-04 Mitsubishi Electric Corp Semiconductor memory
JPH0815206B2 (en) * 1986-01-30 1996-02-14 三菱電機株式会社 Semiconductor memory device
JPS63244399A (en) * 1987-03-16 1988-10-11 シーメンス・アクチエンゲゼルシヤフト Inspection method and circuit apparatus for semiconductor memory
JP2610598B2 (en) * 1987-03-16 1997-05-14 シーメンス・アクチエンゲゼルシヤフト Circuit device for parallel writing of data to semiconductor memory
JPS6346695A (en) * 1987-06-08 1988-02-27 Hitachi Ltd Semiconductor memory
JP2656504B2 (en) * 1987-09-25 1997-09-24 株式会社日立製作所 Semiconductor device
US5010519A (en) * 1987-11-17 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Dynamic semiconductor memory device formed by 2-transistor cells
JPH0713872B2 (en) * 1987-11-24 1995-02-15 三菱電機株式会社 Semiconductor memory device
KR910009805B1 (en) * 1987-11-25 1991-11-30 후지쓰 가부시끼가이샤 Dynamic random access memory device and method of fabrication therefor
US4954992A (en) * 1987-12-24 1990-09-04 Mitsubishi Denki Kabushiki Kaisha Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor
JP2953708B2 (en) * 1989-07-31 1999-09-27 株式会社東芝 Dynamic semiconductor memory device
JPH0684359A (en) * 1993-08-13 1994-03-25 Hitachi Ltd Semiconductor memory
JPH0720182U (en) * 1993-09-13 1995-04-11 喜久子 御前 Washing machine fixed basket using fixed running water
JP3281304B2 (en) * 1997-11-28 2002-05-13 株式会社東芝 Semiconductor integrated circuit device
US5982657A (en) * 1997-12-18 1999-11-09 Texas Instruments Incorporated Circuit and method for biasing the charging capacitor of a semiconductor memory array
JP3795366B2 (en) * 2001-10-03 2006-07-12 プロモス テクノロジーズ インコーポレイテッド Memory element and manufacturing method thereof
US7534983B2 (en) * 2004-11-05 2009-05-19 Sony Corporation Optical imaging device comparing image data at first and second time periods
US20090257263A1 (en) * 2008-04-15 2009-10-15 Vns Portfolio Llc Method and Apparatus for Computer Memory

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3183490A (en) * 1962-10-03 1965-05-11 Gen Electric Capacitive fixed memory system
US3383663A (en) * 1963-09-27 1968-05-14 Bull Sa Machines Balanced sense line permanent memory system
US3506969A (en) * 1967-04-04 1970-04-14 Ibm Balanced capacitor read only storage using a single balance line for the two drive lines and slotted capacitive plates to increase fringing
US3678473A (en) * 1970-06-04 1972-07-18 Shell Oil Co Read-write circuit for capacitive memory arrays
US3771148A (en) * 1972-03-31 1973-11-06 Ncr Nonvolatile capacitive memory cell
US3882326A (en) * 1973-12-26 1975-05-06 Ibm Differential amplifier for sensing small signals
US4025907A (en) * 1975-07-10 1977-05-24 Burroughs Corporation Interlaced memory matrix array having single transistor cells

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3183490A (en) * 1962-10-03 1965-05-11 Gen Electric Capacitive fixed memory system
US3383663A (en) * 1963-09-27 1968-05-14 Bull Sa Machines Balanced sense line permanent memory system
US3506969A (en) * 1967-04-04 1970-04-14 Ibm Balanced capacitor read only storage using a single balance line for the two drive lines and slotted capacitive plates to increase fringing
US3678473A (en) * 1970-06-04 1972-07-18 Shell Oil Co Read-write circuit for capacitive memory arrays
US3771148A (en) * 1972-03-31 1973-11-06 Ncr Nonvolatile capacitive memory cell
US3882326A (en) * 1973-12-26 1975-05-06 Ibm Differential amplifier for sensing small signals
US4025907A (en) * 1975-07-10 1977-05-24 Burroughs Corporation Interlaced memory matrix array having single transistor cells

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IBM Tech. Dis. Bul., vol. 16, No. 7, p. 2418, "Interleaved Memory Array" by W. K. Hoffman.
IBM Tech. Dis. Bul., vol. 16, No. 7, p. 2418, Interleaved Memory Array by W. K. Hoffman. *
Japanese Patent Publication No. 22387/1969, published Sep. 25, 1969, by Tanaka et al. *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4984214A (en) * 1989-12-05 1991-01-08 International Business Machines Corporation Multiplexed serial register architecture for VRAM
US5134616A (en) * 1990-02-13 1992-07-28 International Business Machines Corporation Dynamic ram with on-chip ecc and optimized bit and word redundancy
US5307356A (en) * 1990-04-16 1994-04-26 International Business Machines Corporation Interlocked on-chip ECC system
US5581567A (en) * 1991-08-14 1996-12-03 International Business Machines Corporation Dual level error detection and correction employing data subsets from previously corrected data

Also Published As

Publication number Publication date
US4044340A (en) 1977-08-23
JPS5539073B2 (en) 1980-10-08
JPS5174535A (en) 1976-06-28

Similar Documents

Publication Publication Date Title
USRE32708E (en) Semiconductor memory
US5058058A (en) Structure for sense amplifier arrangement in semiconductor memory device
US4025907A (en) Interlaced memory matrix array having single transistor cells
US6333866B1 (en) Semiconductor device array having dense memory cell array and heirarchical bit line scheme
US4366559A (en) Memory device
US4922460A (en) Semiconductor memory device with folded bit line structure suitable for high density
US5644525A (en) Dynamic semiconductor memory device having an improved sense amplifier layout arrangement
EP0264929B1 (en) Semiconductor memory device with improved bit line arrangement
KR920008753A (en) Semiconductor memory
KR900017187A (en) Semiconductor memory
KR890005743A (en) Low noise semiconductor memory
US5012143A (en) Integrated delay line
US4922453A (en) Bit line structure of dynamic type semiconductor memory device
KR960002816B1 (en) Semiconductor memory cell
JP2865078B2 (en) Semiconductor storage device
KR100305031B1 (en) Lay-out of sense amplifier block in dram
US4402063A (en) Flip-flop detector array for minimum geometry semiconductor memory apparatus
US6438042B1 (en) Arrangement of bitline boosting capacitor in semiconductor memory device
US6865102B1 (en) Static semiconductor storage device
EP0282650A1 (en) Semiconductor memory with cell arrangement
US4984199A (en) Semiconductor memory cells having common contact hole
US20040036104A1 (en) Semiconductor memory device
US4133048A (en) Integrated semiconductor dynamic memory
KR960001784B1 (en) Semiconductor memory device
US6754110B2 (en) Evaluation circuit for a DRAM

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY