US8719834B2 - Information processing system, method, program and integrated circuit for maintaining balance of processing loads with respect to real-time tasks - Google Patents

Information processing system, method, program and integrated circuit for maintaining balance of processing loads with respect to real-time tasks Download PDF

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US8719834B2
US8719834B2 US13/383,291 US201113383291A US8719834B2 US 8719834 B2 US8719834 B2 US 8719834B2 US 201113383291 A US201113383291 A US 201113383291A US 8719834 B2 US8719834 B2 US 8719834B2
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task
real
time
processors
processing
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US20120117567A1 (en
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Katsushige Amano
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Panasonic Intellectual Property Corp of America
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Panasonic Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5077—Logical partitioning of resources; Management or configuration of virtualized resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083—Techniques for rebalancing the load in a distributed system

Definitions

  • the present invention relates to technology which, in information processing system having a plurality of virtual CPUs, allocates the virtual CPUs to a plurality of physical CPUs.
  • Technology exists for running a plurality of virtual machines on one physical machine.
  • a virtual machine operates on a virtual Central Processing Unit (CPU), and virtual CPUs are allocated to physical CPUs by time sharing.
  • Technology for virtual machines provides a management module for managing time sharing of physical CPUs by virtual CPUs. Such a management module is hereinafter referred to as a hypervisor.
  • an Operating System (OS) using a plurality of CPUs has, for each CPU, a task queue listing tasks. Each CPU executes the tasks listed in the task queue for that CPU.
  • OS Operating System
  • Technology has thus been developed for an OS to calculate the load on each CPU, based on factors such as the number of tasks listed in the task queue and the priority of the tasks, and balance the load by dividing up tasks.
  • the OS may for example list the task in the task queue for the CPU with the smallest load.
  • Another method for dividing the load is for the OS to calculate the load on each CPU at regular intervals and moves tasks between CPUs to balance the load.
  • Patent Literature 1 discloses technology for a virtual machine to notify the hypervisor of the priority of the next task to be executed when switching between tasks and for the hypervisor to determine which virtual machine will execute a task next based on the priority.
  • processing by a virtual machine executing a task with a high priority such as a task that needs to be executed in real time (hereinafter, a “real-time task” (RT task)) is executed first, thus more easily satisfying the demands of real-time processing.
  • RT task real-time task
  • two or more virtual CPUs may be allocated to one of a plurality of physical CPUs (processors).
  • processors physical CPUs
  • each OS manages the plurality of task queues included therein to balance the processing load.
  • the processing load may become higher for one physical CPU than for another.
  • Patent Literature 1 only serves to determine the order of execution between two virtual CPUs allocated to one physical CPU. This technology does not change the processing load on the physical CPU.
  • an object of the present invention to provide an information processing system, a method, a program, and an integrated circuit that maintain balance in the processing load on a plurality of processors.
  • an aspect of the present invention is an information processing system comprising: a plurality of operating systems each configured to perform execution control on processing tasks by assigning each task to a task group and causing all tasks assigned to a same task group to be executed on a same processor; and a hypervisor configured to associate each of a plurality of processors with one or more task groups in the operating systems and to cause each operating system to perform the execution control so that all tasks assigned to a same task group are executed on the processor associated with the same task group, the hypervisor including: an acquisition unit configured to sequentially acquire load indicators each indicating a processing load of each task group in each operating system; and a re-association unit configured to refer to the processing loads indicated by each load indicator acquired by the acquisition unit and, when determining that the processing loads are not balanced between the processors, to re-associate the processors with the task groups.
  • the information processing system re-associates the processors with the task groups when the processing loads are not balanced between the processors. This information processing system thus maintains balance in the processing loads across a plurality of processors.
  • FIG. 1 shows the structure of an information processing system 1000 .
  • FIG. 2 shows correspondence between physical CPUs 1 a - 1 c and virtual CPUs 6 a - 6 d.
  • FIG. 3 illustrates movement of a newly generated task.
  • FIG. 4A shows correspondence between physical CPUs 1 a - 1 c and virtual CPUs 6 a - 6 d before reallocation according to Embodiment 1
  • FIG. 4B shows correspondence between physical CPUs 1 a - 1 c and virtual CPUs 6 a - 6 d after reallocation according to Embodiment 1.
  • FIG. 5 outlines the flow of processing by the information processing system 1000 .
  • FIG. 6 shows details on processing by the information processing system 1000 (task generation and movement).
  • FIG. 7A shows correspondence between physical CPUs 1 a - 1 c and virtual CPUs 6 a - 6 d before reallocation according to Modification 1
  • FIG. 7B shows correspondence between physical CPUs 1 a - 1 c and virtual CPUs 6 a - 6 d after reallocation according to Modification 1 .
  • FIG. 8 shows operations by the information processing system of Modification 1 for task generation and movement.
  • FIG. 9A shows correspondence between physical CPUs 1 a - 1 c and virtual CPUs 6 a - 6 d before reallocation according to Modification 2
  • FIG. 9B shows correspondence between physical CPUs 1 a - 1 c and virtual CPUs 6 a - 6 d after reallocation according to Modification 2 .
  • FIG. 10 shows operations by the information processing system of Modification 2 for task generation and movement.
  • FIG. 11 shows the structure of an information processing system 1000 a.
  • FIG. 12 shows the flow of interrupt processing by the information processing system 1000 a.
  • FIG. 13 shows the structure of an information processing system 1000 b.
  • FIG. 14A shows correspondence between physical CPUs 1 a - 1 c and virtual CPUs 6 a - 6 d before reallocation according to Embodiment 3
  • FIG. 14B shows correspondence between physical CPUs 1 a - 1 c and virtual CPUs 6 a - 6 d after reallocation according to Embodiment 3.
  • FIG. 15 shows the flow of operating cycle updating by an information processing system 1000 b.
  • FIG. 16 shows operations by the information processing system 1000 b for task generation and movement.
  • FIG. 17 shows the structure of an information processing system 1000 c.
  • the following describes an information processing system 1000 as an embodiment of the present invention.
  • FIG. 1 shows the structure of the information processing system 1000 according to the present embodiment.
  • the information processing system 1000 includes a plurality of physical CPUs 1 a , 1 b , and 1 c , an I/O device 2 , and a load balancing device 3 .
  • the load balancing device 3 includes memory, such as a Random Access Memory (RAM) or flash memory, in which the load balancing device 3 stores data and a variety of executable programs.
  • RAM Random Access Memory
  • flash memory in which the load balancing device 3 stores data and a variety of executable programs.
  • the load balancing device 3 constructs a virtual machine for each of a plurality of operating systems and executes a plurality of tasks generated in each CPU on a corresponding physical CPU.
  • the load balancing device 3 is provided with multiple (in this case, two) operating systems OS 20 a and 20 b and a hypervisor 5 .
  • the OS 20 a constitutes a virtual machine 4 a and is provided with task queues 100 a and 100 b , a task load balancing unit 101 , a task registration unit 102 , and a task information notification unit 103 .
  • the OS 20 b constitutes a virtual machine 4 b . While not shown in FIG. 1 , the OS 20 b has a similar structure to the OS 20 a.
  • the OS 20 a and the OS 20 b have similar structures, the following describes the constituent elements of the OS 20 a.
  • the task queues 100 a and 100 b list tasks generated in the OS 20 a . As described below, these task queues 100 a and 100 b constitute virtual CPUs.
  • Tasks 10 a and 10 b respectively generated in the task queues 100 a and 100 b are processing units within a regular information processing system 1000 .
  • the OS 20 a normally operates using a plurality of CPUs, but in the present embodiment, the OS 20 a runs as a virtual machine and therefore uses a plurality of virtual CPUs.
  • the task load balancing unit 101 determines the balance of real-time tasks and regular tasks that are generated.
  • a real-time task refers to a task that requires real-time capability, i.e. the capability to complete execution by a deadline.
  • Real-time tasks are executed before regular tasks by, for example, increasing the priority of real-time tasks.
  • real-time tasks are referred to as RT tasks, whereas tasks not requiring real-time capability are referred to as regular tasks. Tasks for which no distinction between RT tasks and regular tasks is required are simply referred to as tasks.
  • the task load balancing unit 101 When a new task is generated, for example, the task load balancing unit 101 operates to determine which of the task queues 100 a and 100 b the new task should be registered in so as to balance the load.
  • the task load balancing unit 101 calculates the processing load of each of the task queues 100 a and 100 b by calculating the total sum of the priority of each task included therein.
  • the task load balancing unit 101 selects the task queue with the smallest processing load, i.e. the task queue with the smallest total sum of priorities.
  • the task registration unit 102 receives the selection of the task load balancing unit 101 and registers the newly generated task in the selected task queue.
  • the task information notification unit 103 determines whether the newly generated task is a regular task or an RT task. When the newly generated task is an RT task, the task information notification unit 103 notifies the hypervisor 5 of the registration destination of the RT task.
  • the task information notification unit 103 is called by the task registration unit 102 and is executed immediately on the physical CPU that executed the task registration unit 102 .
  • the hypervisor 5 manages the allocation of virtual CPUs in the virtual machines 4 a and 4 b to physical CPUs and causes each OS to perform tasks.
  • the hypervisor 5 includes a virtual CPU load determining unit 200 , a virtual CPU load balancing unit 201 , and a virtual CPU scheduling unit 202 .
  • the virtual CPU load determining unit 200 determines the load on each of the virtual CPUs 6 a - 6 d.
  • the virtual CPU load determining unit 200 determines the current load status in each task queue. For example, the virtual CPU load determining unit 200 manages the processing load by determining whether each task queue includes an RT task. In this case, a high priority is associated with an RT task. Therefore, the virtual CPU load determining unit 200 can identify whether the task queue includes a task with a priority of at least a predetermined threshold, i.e. an RT task. A task queue that includes such a task has a high processing load, whereas a task queue that does not has a low processing load.
  • the virtual CPU load balancing unit 201 determines a new allocation of task queues (virtual CPUs) in the virtual machines 4 a and 4 b to physical CPUs 1 a , 1 b , and 1 c and implements the new allocation.
  • the virtual CPU load balancing unit 201 based on the load status of each task queue as determined by the virtual CPU load determining unit 200 , the virtual CPU load balancing unit 201 identifies the processing load on the physical CPUs 1 a , 1 b , and 1 c.
  • the virtual CPU load balancing unit 201 determines an allocation of task queues (virtual CPUs) to the physical CPUs 1 a , 1 b , and 1 c that balances the processing loads. The virtual CPU load balancing unit 201 then implements the determined allocation.
  • the virtual CPU scheduling unit 202 determines the order of execution of the virtual CPUs allocated to the physical CPUs.
  • the virtual CPU scheduling unit 202 determines the processing order for execution of one virtual CPU by time sharing with other virtual CPUs. Specifically, when two virtual CPUs are allocated to one physical CPU, the virtual CPU scheduling unit 202 determines the processing order for execution of the two virtual CPUs by time sharing when switching between the context of one virtual CPU and the context of the other virtual CPU.
  • Each virtual CPU then sequentially executes the tasks contained therein by time sharing.
  • the physical CPUs 1 a , 1 b , and 1 c each process the tasks registered in the one or more task queues allocated thereto by the hypervisor 5 .
  • the I/O device 2 receives external instructions and notifies the physical CPUs 1 a , 1 b , and 1 c , as well as the load balancing device 3 , of the received instructions.
  • FIG. 2 shows an example of allocation.
  • the task queue 100 a (virtual CPU 6 a ) is allocated to the physical CPU 1 a
  • the task queue 100 b (virtual CPU 6 b ) is allocated to the physical CPU 1 b
  • the task queue 100 c (virtual CPU 6 c ) is allocated to the physical CPU 1 b
  • the task queue 100 d (virtual CPU 6 d ) is allocated to the physical CPU 1 c
  • two task queues, 100 b and 100 c are allocated to the physical CPU 1 b .
  • an RT task 30 is generated in virtual CPU 6 a.
  • the task load balancing unit 101 determines where to register the new RT task 30 so that the processing loads for the task queues 100 a and 100 b are balanced. For example, suppose the task load balancing unit 101 determines to register the RT task in the task queue 100 b . As shown in FIG. 3 , the task registration unit 102 then moves the RT task 30 to the determined task queue, registering the RT task 30 in the task queue 100 b (virtual CPU 6 b ).
  • the task information notification unit 103 notifies the hypervisor 5 that the RT task 30 has been registered in the task queue of the virtual CPU 6 b .
  • the task information notification unit 103 is called by the task registration unit 102 and is executed immediately on the CPU that executed the task registration unit 102 (in this example, the physical CPU 1 a ). It is also possible, for example, to notify the hypervisor 5 of registration of the RT task 30 upon a task switch in the virtual CPU 6 b . When notifying at the time of a task switch, however, the notification occurs after the virtual CPU 6 b is executed on the physical CPU 1 b .
  • a delay may occur in the hypervisor 5 being notified that the task registration unit 102 has registered the task queue 100 b in the virtual CPU 6 b .
  • the requirements for execution of the RT task 30 may not be met.
  • notification of the hypervisor 5 is performed immediately on that physical CPU.
  • the virtual CPU load determining unit 200 Upon receiving notification from the task information notification unit 103 of registration of a newly generated RT task, the virtual CPU load determining unit 200 determines the current load status in each task queue.
  • the virtual CPU load balancing unit 201 determines the allocation of the virtual CPUs 6 a - 6 d to the physical CPUs 1 a - 1 c and then implements the allocation. Note that at this point, the virtual CPU load determining unit 200 and the virtual CPU load balancing unit 201 , like the task information notification unit 103 , are executed immediately on the CPU that executed the task registration unit 102 (in this example, the physical CPU 1 a ).
  • the virtual CPU scheduling unit 202 shown in FIG. 1 determines the order of execution of the virtual CPUs allocated to the physical CPUs. This ordering is not shown in the figures.
  • FIG. 4A shows an example of the virtual CPUs 6 a - 6 d (task queues 100 a - 100 d ) when the RT task 30 moves from the virtual CPU 6 a (task queue 100 a ) to the virtual CPU 6 b (task queue 100 b ).
  • FIG. 4A two virtual CPUs, 6 b and 6 c , are allocated to the physical CPU 1 b .
  • An RT task 30 is registered in the virtual CPU 6 b
  • an RT task 30 c is registered in the virtual CPU 6 c .
  • no RT task is registered in the other virtual CPUs, 6 a and 6 d .
  • the virtual CPU load balancing unit 201 determines an allocation of task queues (virtual CPUs) to the physical CPUs 1 a , 1 b , and 1 c that balances the number of RT tasks.
  • the virtual CPU load balancing unit 201 then implements the determined allocation.
  • FIG. 4B shows an example of the result of reallocation, in which the virtual CPU 6 b is allocated to a different physical CPU.
  • the imbalance in RT tasks is thus corrected by distributing, between the physical CPU 1 a and the physical CPU 1 b , task queues in which RT tasks are registered (virtual CPU 6 b , virtual CPU 6 c ).
  • each physical CPU has at most one virtual CPU with an RT task 30 .
  • the virtual CPU scheduling unit 202 determines the order of execution of the virtual CPUs 6 a - 6 d allocated to the physical CPUs 1 a - 1 c .
  • the virtual CPU scheduling unit 202 prioritizes a virtual CPU that includes an RT task 30 .
  • the virtual CPU scheduling unit 202 for example first executes the virtual CPU 6 c that includes the RT task 30 c .
  • the virtual CPU scheduling unit 202 switches to the virtual CPU 6 a , which does not include an RT task.
  • the following describes operations of the information processing system 1000 .
  • the task load balancing unit 101 determines the allocation of a newly generated task to a virtual CPU (step S 5 ).
  • the task registration unit 102 registers the newly generated task in the task queue of the virtual CPU determined by the task load balancing unit 101 (step S 10 ).
  • the task information notification unit 103 immediately notifies the hypervisor 5 of information on the task registered in the task queue (step S 15 ).
  • the virtual CPU load determining unit 200 in the hypervisor 5 determines the load on each of the virtual CPUs (step S 20 ). Based on the load determined by the virtual CPU load determining unit 200 , the virtual CPU load balancing unit 201 balances the virtual CPUs between the physical CPUs 1 a - 1 c (step S 25 ). The virtual CPU scheduling unit 202 determines the order of execution of the virtual CPUs allocated to each of the physical CPUs 1 a - 1 c (step S 30 ). In accordance with the determined order of execution, each physical CPU then executes the tasks included in the one or more virtual CPUs allocated thereto.
  • the task load balancing unit 101 Upon generation of a new task, the task load balancing unit 101 calculates the processing load of the virtual CPUs 6 a and 6 b by calculating the total sum of the priority of every task in the respective task queues 100 a and 100 b . The task load balancing unit 101 then identifies the virtual CPU with the smallest processing load in the OS in which the new task was generated (step S 100 ).
  • the task registration unit 102 registers the newly generated task in the task queue of the virtual CPU that has been identified (step S 105 ).
  • the task information notification unit 103 determines whether the registered task is an RT task (step S 110 ).
  • the task information notification unit 103 When determining the registered task to be an RT task (step S 110 : Yes), the task information notification unit 103 notifies the virtual CPU load determining unit 200 in the hypervisor 5 of the newly registered RT task (step S 115 ).
  • the virtual CPU load determining unit 200 determines the current load status in each task queue (step S 120 ).
  • the virtual CPU load balancing unit 201 Based on the load status of each task queue as determined by the virtual CPU load determining unit 200 , the virtual CPU load balancing unit 201 identifies the processing load on the physical CPUs 1 a - 1 c . Based on the processing load determined for each of the physical CPUs 1 a - 1 c , the virtual CPU load balancing unit 201 determines the allocation of the virtual CPUs 6 a - 6 d to the physical CPUs 1 a - 1 c . Specifically, the virtual CPU load determining unit 200 determines whether, among a plurality of virtual CPUs including an RT task, any virtual CPUs are allocated to the same physical CPU (step S 125 ).
  • the virtual CPU load determining unit 200 searches for a physical CPU to which no virtual CPU including an RT task is allocated (step S 130 ). Upon finding a physical CPU to which a virtual CPU that does not include an RT task is allocated (step S 135 : Yes), the virtual CPU load determining unit 200 identifies the physical CPU as having a low processing load (step S 140 ).
  • the virtual CPU load balancing unit 201 switches the virtual CPU in which the new RT task is registered with the virtual CPU that does not include an RT task and is allocated to the physical CPU identified as having a low processing load (step S 145 ).
  • step S 110 when determining that the task registered in the virtual CPU is not an RT task (step S 110 : No), when determining that no virtual CPUs including an RT task are allocated to the same physical CPU (step S 125 : No), or when not finding a physical CPU when searching in step S 130 (step S 135 : No).
  • the virtual CPU scheduling unit 202 determines the order of execution of the virtual CPUs allocated to each of the physical CPUs 1 a - 1 c.
  • Modification 1 is the method of allocation by the virtual CPU load balancing unit.
  • the same reference signs are used for similar constituent elements as in Embodiment 1.
  • a virtual task load balancing unit in Modification 1 identifies the current load status in each physical CPU 1 a - 1 c based on the load status for each task queue as identified by the virtual CPU load determining unit 200 .
  • the virtual task load balancing unit determines whether another virtual CPU is also allocated to the physical CPU (referred to here as “first physical CPU”) to which a virtual CPU (task queue) including an RT task is allocated.
  • the virtual task load balancing unit determines whether there is any physical CPU (referred to here as “second physical CPU”) to which no virtual CPU including an RT task is allocated. If so, the virtual task load balancing unit determines the second physical CPU to have a low processing load and reallocates, to the second physical CPU, the other virtual CPU allocated to the first physical CPU.
  • second physical CPU any physical CPU
  • the following describes an example of a method of allocation to apply the function of the above-described virtual task load balancing unit.
  • FIG. 7A shows an example of the virtual CPUs 6 a - 6 d (task queues 100 a - 100 d ) when the RT task 30 shown in FIG. 3 moves from the virtual CPU 6 a (task queue 100 a ) to the virtual CPU 6 b (task queue 100 b ).
  • FIG. 7A two virtual CPUs, 6 b and 6 c , are allocated to the physical CPU 1 b .
  • An RT task 30 is registered in the virtual CPU 6 b
  • no RT task is registered in the virtual CPU 6 c .
  • An RT task 30 a is registered in the virtual CPU 6 a
  • no RT task is registered in the virtual CPU 6 d .
  • the virtual CPU 6 b which includes an RT task
  • the virtual CPU 6 c which does not, are both allocated to the same physical CPU 1 b .
  • the virtual CPU load balancing unit 201 determines that the processing load is unbalanced and, in order to restore balance, determines a new allocation so that no other virtual CPU is allocated to the physical CPU 1 b , to which the virtual CPU 6 b that includes the RT task 30 is allocated.
  • the virtual CPU load balancing unit 201 then implements the determined allocation.
  • FIG. 7B shows an example of the result of reallocation, in which the virtual CPU 6 c is allocated to a different physical CPU. In this example, the RT task 30 is moved to the virtual CPU 6 b . Therefore, the virtual CPU 6 c is allocated to the physical CPU 1 c.
  • the virtual CPU scheduling unit 202 need not perform any particular operations.
  • the information processing system performs the processing from step S 100 through step S 115 shown in FIG. 6 . Since this processing has already been described, further description is omitted here.
  • step S 115 the virtual CPU load determining unit 200 identifies the current load status in each task queue upon receiving notification from the task information notification unit 103 (step S 200 ).
  • the virtual task load balancing unit determines whether a virtual CPU that includes an RT task is allocated to the same physical CPU as another virtual CPU (step S 205 ). Specifically, the virtual task load balancing unit determines whether another virtual CPU is also allocated to a first physical CPU, to which the virtual CPU including the RT task is allocated.
  • step S 205 When the virtual task load balancing unit determines positively (step S 205 : Yes), the virtual CPU load balancing unit searches for a physical CPU to which no virtual CPU including an RT task is allocated (step S 210 ).
  • the virtual CPU load balancing unit When finding a physical CPU to which no virtual CPU that includes an RT task is allocated (step S 215 : Yes), the virtual CPU load balancing unit identifies the physical CPU (second physical CPU) as having a low processing load. The virtual CPU load balancing unit then reallocates, to the second physical CPU, the virtual CPU allocated to the first physical CPU (step S 220 ).
  • step S 205 When a negative determination is made in step S 205 (step S 205 : No), or during the search in step S 210 , when a virtual CPU that includes an RT task is allocated to every physical CPU (step S 215 : No), processing ends.
  • the virtual CPU scheduling unit 202 determines the order of execution of the virtual CPUs allocated to each of the physical CPUs 1 a - 1 c.
  • Modification 1 is the method of allocation by the virtual task load balancing unit.
  • the same reference signs are used for similar constituent elements as in Embodiment 1.
  • a predetermined load value indicating task load is assigned to both a regular task and an RT task.
  • the virtual CPU load determining unit determines the status of the processing load of a virtual CPU to be the total of the load value of each task in the corresponding one of the task queues 100 a and 100 b.
  • the virtual CPU load balancing unit balances (allocates) the virtual CPUs 6 a - 6 d so that the total of the load values of the virtual CPUs allocated to each of the physical CPUs 1 a - 1 c is even.
  • the following describes an example of a method of allocation to apply the function of the virtual CPU load balancing unit in the present modification.
  • FIG. 9A shows an example of the virtual CPUs 6 a - 6 d (task queues 100 a - 100 d ) when the RT task 30 shown in FIG. 3 moves from the virtual CPU 6 a (task queue 100 a ) to the virtual CPU 6 b (task queue 100 b ).
  • a value of one is assigned as the load value for a regular task, whereas a value of ten is assigned as the load value for an RT task.
  • FIG. 9A two virtual CPUs, 6 b and 6 c , are assigned to the physical CPU 1 b .
  • An RT task 30 and a regular task 10 b are registered in the virtual CPU 6 b
  • an RT task 30 c and a regular task 10 c are registered in the virtual CPU 6 c .
  • a regular task 10 a is registered in the virtual CPU 6 a
  • an RT task 30 d and a regular task 10 d are registered in the virtual CPU 6 d .
  • the total load value for the virtual CPU 6 a decreases from 11 to 1.
  • the total load value for the virtual CPU 6 b increases from 12 to 22.
  • FIG. 9B shows an example of the result of reallocation, in which the virtual CPU 6 b is allocated to a different physical CPU. In this example, the virtual CPU 6 b is reallocated to the physical CPU 1 a . After reallocation, the total load values for the physical CPUs 1 a - 1 c are 12, 11, and 11, which are nearly even.
  • the task load balancing unit 101 Upon generation of a new task, the task load balancing unit 101 calculates the processing load of each of the task queues 100 a and 100 b respectively in the virtual CPUs 6 a and 6 b by calculating the total sum of the priority of each task included therein. The task load balancing unit 101 then identifies the virtual CPU with the smallest processing load in the OS in which the new task was generated (step S 300 ).
  • the task registration unit 102 registers the newly generated task in the task queue of the virtual CPU that has been identified (step S 305 ).
  • the task information notification unit 103 notifies the virtual CPU load determining unit according to the present modification of the load value for the new registered task (step S 310 ).
  • the virtual CPU load determining unit calculates the total load value for each of the virtual CPUs 6 a - 6 d (step S 315 ).
  • the virtual CPU load balancing unit identifies the load status for each of the physical CPUs 1 a - 1 c based on the total load value calculated for the virtual CPUs (step S 320 ).
  • the virtual CPU load balancing unit then calculates the load that would be placed on the physical CPU currently having the smallest load if the virtual CPU in which the new task was registered is moved thereto (step S 325 ).
  • the virtual CPU load balancing unit determines whether the calculation in step S 325 results in a more even load on the physical CPUs 1 a - 1 c than before calculation (step S 330 ).
  • step S 330 When it is determined that the load is more even (step S 330 : Yes), the virtual CPU load balancing unit according to the present modification moves the virtual CPU in which the new task was registered to the physical CPU having the smallest load (step S 335 ).
  • step S 330 If it is determined that the load is not more even (step S 330 : No), processing ends.
  • the virtual CPU scheduling unit 202 determines the order of execution of the virtual CPUs allocated to each of the physical CPUs 1 a - 1 c.
  • the information processing system 1000 when an RT task is generated in a virtual CPU, the information processing system 1000 according to the present embodiment reallocates the virtual CPUs to physical CPUs so that RT tasks do not coincide on the same physical CPU.
  • balancing the load of virtual CPUs between physical CPUs avoids competition between RT tasks and allows for the requirements for execution of RT tasks to be met.
  • Embodiment 2 focusing on the differences from Embodiment 1. Note that constituent elements that are the same as in Embodiment 1 are indicated by the same reference signs.
  • FIG. 11 shows the structure of an information processing system 1000 a according to Embodiment 2.
  • the information processing system 1000 a in FIG. 11 includes an interrupt notification unit 204 .
  • the virtual CPU load determining unit 200 of the information processing system 1000 is replaced by a virtual CPU load determining unit 203 .
  • the following describes the virtual CPU load determining unit 203 and the interrupt notification unit 204 .
  • the virtual CPU load determining unit 203 includes the following functions.
  • the virtual CPU load determining unit 203 determines whether an interrupt notification should be issued to the virtual CPU that is the target of the interrupt. When determining that an interrupt notification should be issued, the virtual CPU load determining unit 203 notifies the interrupt notification unit 204 accordingly (via an interrupt notification instruction).
  • the operation for determining whether an interrupt notification should be issued is described below.
  • the interrupt notification unit 204 is notified of the result of determination.
  • the interrupt notification unit 204 Upon receiving an interrupt from the I/O device 2 , the interrupt notification unit 204 identifies the virtual CPU that is the target of the interrupt. Upon receiving an interrupt notification instruction for the identified virtual CPU from the virtual CPU load determining unit 203 , the interrupt notification unit 204 immediately provides notification of the interrupt.
  • immediately providing the interrupt notification means that issuing of the interrupt notification is prioritized over other interrupt notifications, so that even during a state of waiting for another interrupt notification to be issued (an interrupt related to a task other than a real-time task), a state of waiting for an interrupt related to a real-time task is not entered.
  • an interrupt notification can be delayed. Therefore, when the targeted virtual CPU is not being executed, for example, the virtual machine may be notified after waiting for execution. For example, a task may be placed in a suspended status that temporarily suspends operations, and the task in a suspended status may be executed again upon an interrupt.
  • the interrupt notification for a virtual CPU that includes an RT task may be triggered by restarting of the RT task. Therefore, the interrupt notification unit 204 allows for immediate restarting of an RT task by immediately providing interrupt notification. Furthermore, when a virtual CPU that includes an RT task is executed on the same physical CPU as another virtual CPU and immediately notifies the other virtual CPU of an interrupt, execution of the virtual CPU that includes the RT task may be suspended. In this sort of case, interrupt notification provided to another virtual CPU allocated to the same physical CPU may be delayed until the physical CPU that includes the RT task becomes idle.
  • the interrupt notification unit 204 receives an interrupt from the I/O device 2 (step S 400 ).
  • the interrupt notification unit 204 identifies the virtual CPU that is the target of the received interrupt (step S 405 ).
  • the virtual CPU load determining unit 203 determines whether the virtual CPU identified by the interrupt notification unit 204 includes an RT task (step S 410 ).
  • the virtual CPU load determining unit 203 transmits an interrupt notification instruction to the interrupt notification unit 204 .
  • the interrupt notification unit 204 immediately issues an interrupt notification to the identified virtual CPU (step S 430 ).
  • the virtual CPU load determining unit 203 When determining that the identified virtual CPU does not include an RT task (step S 410 : No), the virtual CPU load determining unit 203 further determines whether the identified virtual CPU is allocated to the same physical CPU as another virtual CPU (step S 415 ).
  • the virtual CPU load determining unit 203 determines whether the other virtual CPU includes an RT task (step S 420 ).
  • the virtual CPU load determining unit 203 determines whether the physical CPU is in an idle state (step S 425 ).
  • step S 425 When the physical CPU is in an idle state (step S 425 : Yes), the virtual CPU load determining unit 203 transmits an interrupt notification instruction to the interrupt notification unit 204 . Upon receiving the interrupt notification instruction, the interrupt notification unit 204 issues an interrupt notification to the identified virtual CPU (step S 430 ).
  • the virtual CPU load determining unit 203 also transmits an interrupt notification instruction to the interrupt notification unit 204 in the following cases: when the identified virtual CPU is not allocated to the same physical CPU as another virtual CPU (step S 415 : No), or when the identified virtual CPU is allocated to the same physical CPU as another virtual CPU, yet the other virtual CPU does not include an RT task (step S 420 : No).
  • the interrupt notification unit 204 Upon receiving the interrupt notification instruction, the interrupt notification unit 204 immediately issues an interrupt notification to the identified virtual CPU (step S 430 ).
  • Embodiment 3 focusing on the differences from Embodiment 1. Note that constituent elements that are the same as in Embodiment 1 are indicated by the same reference signs.
  • FIG. 13 shows the structure of an information processing system 1000 b according to Embodiment 3.
  • the information processing system 1000 b in FIG. 13 includes a real-time task execution notification unit 104 .
  • the virtual CPU load determining unit 200 and the virtual CPU load balancing unit 201 of the information processing system 1000 are respectively replaced by a virtual CPU load determining unit 205 and a virtual CPU load balancing unit 206 .
  • the following describes the functions of the real-time task execution notification unit 104 , the virtual CPU load determining unit 205 , and the virtual CPU load balancing unit 206 .
  • the real-time task execution notification unit 104 notifies the virtual CPU load determining unit 205 of time information indicating the time at which operations for an RT task began.
  • This time information on an RT task is, for example, acquired from a task scheduler (not shown in the figures) in the OS 20 a.
  • the virtual CPU load determining unit 205 Upon receiving the time information on an RT task, the virtual CPU load determining unit 205 calculates the operating cycle (activation cycle) of the RT task based on the time information that was just received and time information previously received. The virtual CPU load determining unit 205 then records the calculated operating cycle as the load of the virtual CPU that includes the RT task.
  • the virtual CPU load balancing unit 206 is provided with the following functions.
  • the virtual CPU load balancing unit 206 determines that every physical CPU has allocated thereto a virtual CPU that includes an RT task, the virtual CPU load balancing unit 206 allocates a virtual CPU that includes a newly generated RT task to the physical CPU to which is allocated the virtual CPU including the RT task with the longest operating cycle.
  • the following is an example of balancing the virtual CPUs according to the present embodiment.
  • FIG. 14A shows the state before reallocation. Specifically, two virtual CPUs, 6 b and 6 c , are allocated to the physical CPU 1 b . A newly generated RT task 40 is registered in the virtual CPU 6 b , and an RT task 30 c is registered in the virtual CPU 6 c . RT tasks 30 a and 30 d are respectively registered in the other virtual CPUs, 6 a and 6 d . In this case, since an RT task is included in every virtual CPU, the virtual CPU load balancing unit 201 cannot reallocate the virtual CPUs so that at most one RT task is allocated to each of the physical CPUs 1 a - 1 c .
  • the virtual CPU load balancing unit 206 therefore identifies the virtual CPU including the RT task with the longest operating cycle, as well as the physical CPU to which this virtual CPU is allocated. The virtual CPU load balancing unit 206 then allocates the virtual CPU 6 b that includes the newly generated RT task 40 to the identified physical CPU.
  • FIG. 14B shows an example of the result of reallocation.
  • the virtual CPU 6 a has the longest operating cycle and is allocated to the physical CPU 1 a . Therefore, the virtual CPU 6 b is reallocated from the physical CPU 1 b to the physical CPU 1 a.
  • reallocating virtual CPUs By reallocating virtual CPUs in this way, the probability of competition between the new RT task and the RT task with the longest operating cycle is low. Accordingly, the probability of the RT task 30 a in the virtual CPU 6 a and the RT task 40 in the virtual CPU 6 b simultaneously attempting to operate is low, thereby making it easier to satisfy the demands of real-time processing. If the number of virtual CPUs that include an RT task increases further, reallocation may be determined by considering the operating cycle of each physical CPU to be the shortest operating cycle of any real task included in any of the virtual CPUs 6 a - 6 d that are allocated to the physical CPU.
  • the real-time task execution notification unit 104 determines whether operations of an RT task included in a managed task queue have begun (step S 400 ).
  • step S 400 When determining that operations have begun (step S 400 : Yes), the real-time task execution notification unit 104 notifies the virtual CPU load determining unit 205 of time information on the RT task (step S 405 ).
  • the virtual CPU load determining unit 205 receives the notification of the RT task whose operations have just begun from the real-time task execution notification unit 104 and, based on the time information that was just received and time information previously received, calculates the operating cycle for this managed RT task. The virtual CPU load determining unit 205 then updates the operating cycle for the RT task (step S 410 ).
  • the information processing system 1000 b performs the processing from steps S 100 through S 115 in FIG. 6 . Since this processing has already been described, further description is omitted here.
  • step S 115 the virtual CPU load determining unit 205 identifies the current load status in each task queue upon receiving notification from the task information notification unit 103 (step S 500 ).
  • the virtual CPU load balancing unit 206 determines whether a virtual CPU that includes a new RT task is allocated to the same physical CPU as another virtual CPU (step S 505 ). Specifically, the virtual CPU load balancing unit 206 determines whether another virtual CPU is also allocated to the physical CPU to which the virtual CPU including the new RT task is allocated.
  • step S 505 When determining positively (step S 505 : Yes), the virtual CPU load balancing unit 206 searches for a physical CPU to which no virtual CPU including an RT task is allocated (step S 510 ).
  • the virtual CPU load balancing unit 206 When finding a physical CPU to which no virtual CPU including an RT task is allocated (step S 515 : Yes), the virtual CPU load balancing unit 206 identifies the physical CPU as having a low processing load. The virtual CPU load balancing unit 206 then reallocates, to this physical CPU, the other virtual CPU that is allocated to the same physical CPU as the virtual CPU that includes the new RT task.
  • step S 510 when not finding a physical CPU not having allocated thereto a virtual CPU that includes an RT task (step S 515 : No), the virtual CPU load balancing unit 206 moves the virtual CPU in which the new RT task is registered to the physical CPU having allocated thereto the virtual CPU that includes the RT task with the longest operating cycle (step S 525 ).
  • step S 505 When the determination in step S 505 is negative (step S 505 : No), processing ends.
  • the virtual CPU scheduling unit 202 determines the order of execution of the virtual CPUs allocated to each of the physical CPUs 1 a - 1 c.
  • Embodiment 4 focusing on the differences from Embodiment 1. Note that constituent elements that are the same as in Embodiment 1 are indicated by the same reference signs.
  • FIG. 17 shows the structure of an information processing system 1000 c according to Embodiment 4.
  • the information processing system 1000 c in FIG. 17 includes a virtual CPU processing capacity notification unit 207 .
  • the task load balancing unit 101 of the information processing system 1000 is replaced by a task load balancing unit 105 .
  • the virtual CPU processing capacity notification unit 207 acquires information from the virtual CPU scheduling unit 202 on how much physical CPU time to allocate to a virtual CPU. For example, this information may indicate allocation of 50% of the physical CPU time.
  • the virtual CPU processing capacity notification unit 207 calculates the processing capacity of each of the virtual CPUs 6 a - 6 d based on the time of the physical CPUs 1 a - 1 c allocated thereto. The virtual CPU processing capacity notification unit 207 then notifies the task load balancing unit 105 of the calculated processing capacities.
  • the task load balancing unit 105 balances the task load taking into consideration the processing capability of each CPU. Specifically, upon receiving information on the processing capability of each of the virtual CPUs 6 a - 6 d from the virtual CPU processing capacity notification unit 207 , the task load balancing unit 105 refers to the processing capacity of the virtual CPUs 6 a - 6 d to suppress the allocation of tasks to a virtual CPU having a lower processing capacity than other virtual CPUs.
  • the task load balancing unit 105 thus suppresses allocation of tasks to a virtual CPU with little physical CPU time. If many virtual CPUs are allocated to a certain physical CPU, registration of a new RT task in a task queue of one of the virtual CPUs is suppressed. This prevents RT tasks from becoming concentrated in the physical CPU.
  • Task generation and movement by the information processing system 1000 c is achieved by simply changing step S 100 of the operations shown in FIG. 6 to a determination of where to register a new task based on the processing capability of each of the virtual CPUs 6 a - 6 d . Therefore, a detailed description on these operations is omitted.
  • the information processing system determines where to move a new task upon generation thereof, but the information processing system is not limited in this way.
  • the information processing system may call the task load balancing unit at regular intervals and determine the movement of tasks between task queues to balance the load.
  • the number of virtual machines is two, but the number is not limited to two.
  • the information processing system may be provided with three or more virtual machines.
  • the virtual CPU scheduling unit determines the order of execution of tasks in the task queues by time sharing, but the present invention is not limited in this way.
  • An alternative form of virtual CPU scheduling is for the OS 20 a and the OS 20 b to notify the hypervisor 5 of completion of an RT task, and for the virtual CPU scheduling unit to continue execution of a virtual CPU that includes an RT task until receiving notification of completion.
  • RT tasks and regular tasks are distinguished by priority, but priority is not the only way to distinguish between tasks.
  • RT tasks may be distinguished from regular tasks by an OS having a function to distinguish RT tasks in some way other than by priority.
  • OS having a function to distinguish RT tasks in some way other than by priority.
  • any task with at least this certain degree of priority may be considered a real-time task.
  • An RT task in the present invention corresponds to a task that, based on the priority or type of the task, is treated as particularly requesting prioritized execution.
  • the time information is acquired from the OS task scheduler, but acquisition is not limited in this way.
  • the information recorded by the OS may be used.
  • the task information notification unit may double as the real-time task execution notification unit.
  • the information used for reallocation is the operating cycle of each RT task, but reallocation is not limited in this way.
  • a pseudo-cycle may be used as the average operation interval of an RT task.
  • the operation time of an RT task may be used to balance the virtual CPUs.
  • the functional blocks in the present invention are typically implemented as software, yet these functional blocks may be implemented as an LSI, a type of integrated circuit.
  • the functional blocks may be implemented as individual chips. Alternatively, a portion or all of the functional blocks may be integrated into one chip.
  • LSI depending on the degree of integration, the terms IC, system LSI, super LSI, or ultra LSI are also used.
  • the method for assembling integrated circuits is not limited to LSI, and a dedicated communication circuit or a general-purpose processor may be used.
  • a Field Programmable Gate Array which is programmable after the LSI is manufactured, or a reconfigurable processor, which allows reconfiguration of the connection and setting of circuit cells inside the LSI, may be used.
  • FPGA Field Programmable Gate Array
  • a reconfigurable processor which allows reconfiguration of the connection and setting of circuit cells inside the LSI.
  • An aspect of the present invention is an information processing system comprising: a plurality of operating systems each configured to perform execution control on processing tasks by assigning each task to a task group and causing all tasks assigned to a same task group to be executed on a same processor; and a hypervisor configured to associate each of a plurality of processors with one or more task groups in the operating systems and to cause each operating system to perform the execution control so that all tasks assigned to a same task group are executed on the processor associated with the same task group, the hypervisor including: an acquisition unit configured to sequentially acquire load indicators each indicating a processing load of each task group in each operating system; and a re-association unit configured to refer to the processing loads indicated by each load indicator acquired by the acquisition unit and, when determining that the processing loads are not balanced between the processors, to re-associate the processors with the task groups.
  • the information processing system re-associates the processors with the task groups when the processing loads are not balanced between the processors. This information processing system thus maintains balance in the processing loads across a plurality of processors.
  • Each processing load may relate to any real-time tasks in the corresponding task group, a real-time task requiring processing in real time, and when the processing loads relating to real-time tasks are not balanced between the processors, the re-association unit may re-associate the processors with the task groups so as to balance the processing loads for real-time tasks.
  • the information processing system re-associates the processors with the task groups so as to balance the processing loads for real-time tasks.
  • This information processing system thus maintains balance in the processing loads for real-time tasks. Since the processing loads for real-time tasks are maintained in balance, the demand for real-time processing of real-time tasks can be satisfied.
  • the processing load relating to real-time tasks included in a task group may be a count of any real-time tasks included in the task group, and when counts of real-time tasks to be processed by the processors are not balanced between the processors, the re-association unit may re-associate the processors with the task groups so as to balance the counts of real-time tasks to be processed.
  • the information processing system treats the number of real-time tasks as the processing load.
  • the information processing system can thus easily identify the processing load on each processor.
  • the re-association unit may determine that the processing load relating to real-time tasks is not balanced between the processors when at least two task groups among a plurality of task groups associated with a processor each include a real-time task, and may re-associate each of the at least two task groups with different processors.
  • the information processing system maintains balance in the processing loads for real-time tasks by re-associating at least two task groups that are associated with the same processor.
  • the at least two task groups are thus associated with different processors.
  • the re-association unit may determine that the processing load is not balanced between the processors when one of a plurality of task groups associated with a processor includes a real-time task.
  • the re-association unit may re-associate only the one of the plurality of task groups that includes a real-time task with the processor and re-associate the rest of the plurality of task groups with one or more different processors.
  • the information processing system associates one task group including a real-time task with one processor.
  • the need for scheduling with another task group that does not include a real-time task is thus eliminated, allowing for the demand for real-time processing of real-time tasks to be satisfied.
  • the processing load may indicate an operation interval of each real-time task in each task group.
  • the re-association unit may determine that the processing load is not balanced between processors when a processor is associated with a first task group and a second task group, a real-time task included in the first task group having a shorter operation interval than a real-time task included in the second task group, and may re-associate the second task group with a processor associated with a third task group that includes a real-time task with a longer operation interval than the real-time task included in the first task group.
  • the information processing system re-associates the second task group with the processor with which the third task group is associated.
  • the probability of competition between the real-time task in the second task group and the real-time task in the third task group is thus reduced.
  • the hypervisor may notify the operating system performing execution control of the task group including the real-time task.
  • the information processing system immediately provides an interrupt notification, thus allowing for the demand for real-time processing of real-time tasks to be satisfied.
  • Each task may be assigned a degree of priority for processing, and the re-association unit may determine, based on a total per task group of the degree of priority of each task included in the task group, that the processing loads are not balanced when totals of the degree of priority are not balanced between the processors, and may re-associate one of the processors with a different task group so as to average the totals of the degree of priority over the processors.
  • the information processing system treats the total of the degree of priority of each task included in a task group as the processing load for the task group.
  • the information processing system can thus easily identify the processing load on each processor.
  • the hypervisor may further include a notification unit configured to notify each operating system, regarding each task group included in the operating system, of a processing capacity allocated to the task group in the processor associated with the task group. Upon generating a new task, each operating system may allocate the new task to a task group having a highest processing capacity among the notified processing capacities.
  • the information processing system allocates a newly generated task based on the processing capacity allocated to each task group in each of the processors.
  • the information processing system thus maintains balance in the processing loads across a plurality of processors.
  • the hypervisor may further include a scheduling unit configured to determine, for each processor, a processing schedule for the one or more task groups associated with the processor, and the processing capacity may indicate a processing time for each task group based on the processing schedule.
  • the information processing system allocates a newly generated task based on the processing schedule of each task group in each of the processors.
  • the information processing system according to the present invention is useful not only in large-scale computers and personal computers, but in any device that performs processing using a virtual machine, including household appliances such as digital televisions and storage/playback devices, communications devices, industrial devices, control devices, and vehicle-mounted devices.
  • household appliances such as digital televisions and storage/playback devices, communications devices, industrial devices, control devices, and vehicle-mounted devices.

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130117745A1 (en) * 2011-05-16 2013-05-09 Teruo Kamiyama Virtual computer system, control method for virtual computer system, control program for virtual computer system, and integrated circuit
US20170024231A1 (en) * 2015-07-23 2017-01-26 Red Hat, Inc. Configuration of a computer system for real-time response from a virtual machine
US10379900B2 (en) * 2016-03-07 2019-08-13 International Business Machines Corporation Dispatching jobs for execution in parallel by multiple processors

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2012271352B2 (en) 2011-06-16 2015-05-07 Argyle Data, Inc. Software virtual machine for acceleration of transactional data processing
WO2013051136A1 (ja) * 2011-10-06 2013-04-11 株式会社日立製作所 仮想サーバ処理制御方法、システムおよび仮想サーバ処理制御管理サーバ
US9146690B2 (en) * 2012-01-27 2015-09-29 Marvell World Trade Ltd. Systems and methods for dynamic priority control
JP5624084B2 (ja) * 2012-06-04 2014-11-12 株式会社日立製作所 計算機、仮想化機構、及びスケジューリング方法
KR20140080058A (ko) * 2012-12-20 2014-06-30 삼성전자주식회사 멀티코어를 위한 로드 밸런싱 방법 및 휴대 단말
US9069594B1 (en) * 2012-12-27 2015-06-30 Emc Corporation Burst buffer appliance comprising multiple virtual machines
US9396012B2 (en) * 2013-03-14 2016-07-19 Qualcomm Incorporated Systems and methods of using a hypervisor with guest operating systems and virtual processors
WO2015031272A1 (en) * 2013-08-26 2015-03-05 Vmware, Inc. Cpu scheduler configured to support latency sensitive virtual machines
US9250953B2 (en) * 2013-11-12 2016-02-02 Oxide Interactive Llc Organizing tasks by a hierarchical task scheduler for execution in a multi-threaded processing system
CN103825842B (zh) * 2014-02-28 2017-06-23 新华三技术有限公司 一种多cpu***的数据流处理方法和装置
US10175885B2 (en) * 2015-01-19 2019-01-08 Toshiba Memory Corporation Memory device managing data in accordance with command and non-transitory computer readable recording medium
JP6447217B2 (ja) * 2015-02-17 2019-01-09 富士通株式会社 実行情報通知プログラム、情報処理装置および情報処理システム
JP6547363B2 (ja) * 2015-03-26 2019-07-24 日本電気株式会社 管理装置、管理装置の制御方法、及びプログラム
CN105955807B (zh) * 2016-04-20 2023-10-31 上海瀚银信息技术有限公司 一种任务处理***及方法
US11281482B2 (en) * 2016-12-14 2022-03-22 Intel Corporation I/O emulation with abortion in virtualized environments including transfer of portions of non-real time I/O emulation to work threads prior to switching contexts
US10789097B2 (en) * 2017-02-16 2020-09-29 Nasdaq Technology Ab Methods and systems of scheduling computer processes or tasks in a distributed system
JP6678823B1 (ja) * 2018-04-27 2020-04-08 三菱電機株式会社 データ処理装置、タスク制御方法及びプログラム
US20220395881A1 (en) 2020-02-27 2022-12-15 Nippon Steel Corporation Cooling device and cooling method
US11726827B2 (en) * 2021-02-19 2023-08-15 Vast Data Ltd. Hierarchical workload allocation in a storage system

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000242512A (ja) 1999-02-19 2000-09-08 Hitachi Ltd 複数のオペレーティングシステムを実行する計算機
US6148324A (en) * 1998-01-05 2000-11-14 Lucent Technologies, Inc. Prioritized load balancing among non-communicating processes in a time-sharing system
US20020087611A1 (en) 2000-12-28 2002-07-04 Tsuyoshi Tanaka Virtual computer system with dynamic resource reallocation
US20030097393A1 (en) 2001-11-22 2003-05-22 Shinichi Kawamoto Virtual computer systems and computer virtualization programs
US20050102677A1 (en) * 2001-01-24 2005-05-12 Gootherts Paul D. Load balancer with starvation avoidance
US20050108717A1 (en) * 2003-11-18 2005-05-19 Hong Steve J. Systems and methods for creating an application group in a multiprocessor system
US20060101465A1 (en) * 2004-11-09 2006-05-11 Hitachi, Ltd. Distributed control system
US20070074216A1 (en) * 2004-06-01 2007-03-29 Sony Computer Entertainment Inc. Task management method, task management device, semiconductor integrated circuit, electronic apparatus, and task management system
US20080148015A1 (en) 2006-12-19 2008-06-19 Yoshifumi Takamoto Method for improving reliability of multi-core processor computer
US7664931B2 (en) * 2004-07-01 2010-02-16 Harman Becker Automotive Systems Gmbh Scalable and configurable multimedia system for a vehicle
US20120204183A1 (en) * 2009-09-02 2012-08-09 Plurality Ltd. Associative distribution units for a high flowrate synchronizer/schedule

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007018268A (ja) * 2005-07-07 2007-01-25 Sumitomo Heavy Ind Ltd タスクスケジューリング方法、タスクスケジューリング装置、及びタスクスケジューリングプログラム
JP2009237858A (ja) * 2008-03-27 2009-10-15 Chugoku Electric Power Co Inc:The サーバタスク管理プログラム及びサーバタスク管理方法
US8468533B2 (en) * 2008-04-28 2013-06-18 Panasonic Corporation Virtual machine control device, method, and program wherein a switching task used to switch to the highest priority virtual machines is the highest priority task in the current virtual machine and the virtual machine that is the switching target

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6148324A (en) * 1998-01-05 2000-11-14 Lucent Technologies, Inc. Prioritized load balancing among non-communicating processes in a time-sharing system
US20050149933A1 (en) 1999-02-19 2005-07-07 Masahiko Saito Computer executing multiple operating systems
JP2000242512A (ja) 1999-02-19 2000-09-08 Hitachi Ltd 複数のオペレーティングシステムを実行する計算機
US20080034366A1 (en) 2000-12-28 2008-02-07 Tsuyoshi Tanaka Virtual computer system with dynamic resource reallocation
US20020087611A1 (en) 2000-12-28 2002-07-04 Tsuyoshi Tanaka Virtual computer system with dynamic resource reallocation
JP2002202959A (ja) 2000-12-28 2002-07-19 Hitachi Ltd 動的な資源分配をする仮想計算機システム
US20050102677A1 (en) * 2001-01-24 2005-05-12 Gootherts Paul D. Load balancer with starvation avoidance
JP2003157177A (ja) 2001-11-22 2003-05-30 Hitachi Ltd 仮想計算機システム及びプログラム
US20030097393A1 (en) 2001-11-22 2003-05-22 Shinichi Kawamoto Virtual computer systems and computer virtualization programs
US20110083135A1 (en) 2001-11-22 2011-04-07 Shinichi Kawamoto Virtual computer systems and computer virtualization programs
US20060288348A1 (en) 2001-11-22 2006-12-21 Shinichi Kawamoto Virtual computer systems and computer virtualization programs
US20050108717A1 (en) * 2003-11-18 2005-05-19 Hong Steve J. Systems and methods for creating an application group in a multiprocessor system
US20070074216A1 (en) * 2004-06-01 2007-03-29 Sony Computer Entertainment Inc. Task management method, task management device, semiconductor integrated circuit, electronic apparatus, and task management system
US7664931B2 (en) * 2004-07-01 2010-02-16 Harman Becker Automotive Systems Gmbh Scalable and configurable multimedia system for a vehicle
US20060101465A1 (en) * 2004-11-09 2006-05-11 Hitachi, Ltd. Distributed control system
US20080148015A1 (en) 2006-12-19 2008-06-19 Yoshifumi Takamoto Method for improving reliability of multi-core processor computer
JP2008152594A (ja) 2006-12-19 2008-07-03 Hitachi Ltd マルチコアプロセッサ計算機の高信頼化方法
US20120204183A1 (en) * 2009-09-02 2012-08-09 Plurality Ltd. Associative distribution units for a high flowrate synchronizer/schedule

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
International Search Report issued Jul. 5, 2011 in International (PCT) Application No. PCT/JP2011/002311.

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130117745A1 (en) * 2011-05-16 2013-05-09 Teruo Kamiyama Virtual computer system, control method for virtual computer system, control program for virtual computer system, and integrated circuit
US9032401B2 (en) * 2011-05-16 2015-05-12 Panasonic Intellectual Property Corporation Of America Virtual computer system having a first virtual computer that executes a protected process, a second virtual computer that executes an unprotected process, and a hypervisor that controls the first and second virtual computers
US20170024231A1 (en) * 2015-07-23 2017-01-26 Red Hat, Inc. Configuration of a computer system for real-time response from a virtual machine
US10002016B2 (en) * 2015-07-23 2018-06-19 Red Hat, Inc. Configuration of virtual machines in view of response time constraints
US10379900B2 (en) * 2016-03-07 2019-08-13 International Business Machines Corporation Dispatching jobs for execution in parallel by multiple processors
US10942772B2 (en) * 2016-03-07 2021-03-09 International Business Machines Corporation Dispatching jobs for execution in parallel by multiple processors

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CN102473118A (zh) 2012-05-23
WO2011148563A1 (ja) 2011-12-01

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