US8624766B2 - Method and system for auto-ranging analog-to-digital converter for current sensing - Google Patents
Method and system for auto-ranging analog-to-digital converter for current sensing Download PDFInfo
- Publication number
- US8624766B2 US8624766B2 US13/307,022 US201113307022A US8624766B2 US 8624766 B2 US8624766 B2 US 8624766B2 US 201113307022 A US201113307022 A US 201113307022A US 8624766 B2 US8624766 B2 US 8624766B2
- Authority
- US
- United States
- Prior art keywords
- auto
- ranging
- current
- adc
- replicated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000003362 replicative effect Effects 0.000 claims abstract description 6
- 230000008859 change Effects 0.000 claims description 4
- 238000001914 filtration Methods 0.000 claims description 2
- 238000001514 detection method Methods 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 230000003466 anti-cipated effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000010076 replication Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/001—Digital control of analog signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
- H03M1/183—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter
Definitions
- the present disclosure relates generally to the field of analog integrated circuit design and, more particularly, to methods and systems for power management in electronic circuits.
- a conventional solution for removal detection is to employ a very high resolution analog-to-digital converter (ADC) to measure current over a wide range, from Amperes on the high-end to micro amperes at the lower end of the scale.
- ADC analog-to-digital converter
- the high resolution ADCs require output of 16-bits and more. As is well understood in the art, that degree of resolution calls for high die area requirements.
- adding high resolution ADCs to an integrated chip increases the overall power consumption of the chip.
- the present disclosure describes a method and system for an auto-ranging analog-to-digital converter (ADC) for dynamically scaling inputs to an ADC.
- the auto-ranging ADC includes a dynamically configurable transistor arrangement for providing a load current and a replica device for replicating the load current.
- the replica device outputs a replicated load voltage based on the replicated current.
- the ADC generates a digital value based on the replicated load voltage.
- the auto-ranging ADC also includes an auto-ranging controller for dynamically configuring the transistor arrangement based on the digital value to scale the inputs to the ADC.
- the present disclosure describes an auto-ranging method for dynamically scaling inputs to an analog-to-digital converter (ADC).
- the auto-ranging method includes providing a load current by a dynamically configurable transistor arrangement and replicating the load current.
- the method further includes generating a replicated load voltage based on the replicated current.
- the method includes generating a digital value based on the replicated load voltage by the ADC.
- the method includes dynamically configuring the transistor arrangement based on the digital value to scale the inputs to the ADC.
- FIG. 1 is a block diagram of one embodiment of an auto-ranging system configured according to principles of the present invention.
- FIG. 2 is a circuit diagram of one embodiment of an auto-ranging system configured according to principles of the present invention
- FIG. 3 is a flowchart depicting an exemplary method for auto-ranging an ADC.
- Embodiments of the present disclosure provide a method and system for an auto-ranging analog-to-digital converter (ADC) for dynamically scaling inputs to the ADC.
- the auto-ranging ADC is used for high-precision measurement of current values.
- the auto-ranging ADC includes a dynamically configurable transistor arrangement for generating a replica current based on a load current. The load current is generated to meet the varying demands of downstream devices.
- the dynamically configurable transistor arrangement modifies the prior transistor arrangement to generate a replica current depending on the load current requirement.
- a replica device is connected to the transistor arrangement in a configuration which generates a replica current based on the load current drawn by a downstream device.
- the replica current is mirrored to flow through a current sense resistor.
- a voltage is developed across the current sense resistor.
- the developed voltage is fed to an ADC to generate a digital value corresponding to the developed voltage.
- the developed voltage may be input to a sample-and-hold, and anti-aliasing filter circuit to avoid the aliasing of higher frequency signals back into the ADC. This voltage may then be fed to the ADC.
- the digital value output by the ADC is fed to an auto-ranging controller.
- the auto-ranging controller Based on the digital value, the auto-ranging controller generates switching signals. When the digital value falls below a threshold value, the auto-ranging controller changes the state of the switching signals. The state of the switching signals determines the configuration of the transistor arrangement.
- the switching signals dynamically configure the transistor arrangement to scale the inputs to the ADC.
- the transistor arrangement includes at least two transistors connected in parallel.
- the dynamic re-configuration involves switching on one or more transistors to provide the required load current to the downstream device.
- the switching signals connect the switches coupling the input voltage supply to the gate terminals of the transistors. Depending on the state of one or more transistors, load current flows through the transistor arrangement. Therefore, the input to the ADC is scaled accordingly.
- the auto-ranging ADC can be used in a wide variety of electronic applications.
- a USB Port Power Controller can use an embodiment of the disclosure to control a 5V bus voltage, capable of delivering up to 2.5 A load current.
- the port power switch including three transistor switches connected in parallel, can be tailored to the anticipated ADC reading.
- an eight-bit SAR ADC may perform power-rationing by employing a replica device in parallel with the port power switch to generate a copy current based port power switch current.
- the port power switch is downsized to generate a replica current within the dynamic range of the ADC.
- the port power switch is downsized based on the prior reading of the ADC when all the transistors in the port power switch are connected.
- FIG. 1 is a block diagram illustrating an exemplary auto-ranging system 100 including an analog-to-digital converter (ADC) 108 for high precision current sensing.
- the auto-ranging system 100 includes a transistor arrangement 102 electronically coupled to a replica device 104 for replicating a load current (ILoad) 124 flowing through the transistor arrangement 102 .
- a current sense resistor 106 is electronically coupled to the replica device 104 for generating a replicated load voltage 128 based on the replicated current, and that voltage is fed to the ADC 108 . That device generates a digital value based on the replicated load voltage 128 .
- An auto-ranging controller 110 receives the ADC output and generates switching signals “Ibus_super_low” and “Ibus_low”. Those signals are fed to the transistor arrangement 102 , which accordingly configures transistor arrangement 102 .
- a downstream device 122 demands a load current 124 ILoad to meet the power requirement of the downstream device 122 and its components.
- Inputs to the transistor arrangement 102 are reference supply voltage VS and control voltage Vg.
- the transistor arrangement 102 can be dynamically configured among two or more current ranges, controlled by inputs “Ibus_super_low” and “Ibus_low”.
- the replica device 104 also receives control voltage Vg as an input, together with a signal based on the load current 124 , and it accordingly outputs a replica current 126 .
- the replica current 126 is fed to current sense resistor 106 , which in turn produces a replicated load voltage 128 .
- the replica device 104 may mirror the replica current 126 before generating the replicated load voltage 128 , which is then fed as an input to the ADC 108 .
- the ADC 108 receives the replicated load voltage 128 and generates a corresponding digital value adc_data ⁇ N:0>. Other inputs include “adc_start”, an active high signal, which initiates the conversion of the ADC 108 .
- a clock signal “adc_clk” is also provided, as is a voltage reference signal Vref.
- the ADC 108 may also include an anti-aliasing filter for restricting the frequency bandwidth of the replicated load voltage 128 .
- the ADC 108 is an 8-bit successive-approximation-register (SAR) analog-to-digital converter (ADC).
- the ADC 108 outputs a digital value adc_data ⁇ N:0>, where N represents the number of bits in the output digital value. For example, an eight bit ADC will generate a digital value adc_data ⁇ 8:0>.
- the auto-ranging controller 110 uses the output digital value adc_data ⁇ N:0> to generate switching signals “Ibus_super_low” and “Ibus_low”. Those signals are used by the transistor arrangement 102 to dynamically configure the prior transistor arrangement 102 .
- the switching signal output is based on the value of adc_data ⁇ N:0>, and thus the auto-ranging controller 110 may include sensing and response circuitry, such as a logic circuit, a microprocessor, a microcontroller, or similar circuits and devices known in the art for generating the switching signals.
- the auto-ranging controller 110 may include a memory device, such as a one-time programmable memory (OTP), for storing the threshold values of the digital value for determining the configuration of the transistor arrangement 102 .
- OTP one-time programmable memory
- the transistor arrangement 102 is configured for maximum load current 124 . Then, if the ADC 108 reading crosses a threshold value, the auto-ranging controller 110 sends an appropriate signal to the transistor arrangement 102 via switching signals “Ibus_super_low” and “Ibus_low”.
- FIG. 2 is a circuit diagram illustrating an exemplary auto-ranging system 200 including an analog-to-digital converter (ADC) 208 for high precision current sensing.
- the auto-ranging system 200 includes a pass transistor PM1 202 , which in turn includes three transistors PM1-A 202 -A, PM1-B 202 -B, and PM1-C 202 -C connected in parallel.
- a control voltage Vg is connected to the gates of the three transistors PM1-A 202 -A, PM1-B 202 -B, and PM1-C 202 -C, coupled through switches S1 203 -A and S2 203 -B.
- the switches S1 203 -A and S2 203 -B are controlled by switching signals “Ibus_super_low” and “Ibus_low” respectively. All three switches are closed at start-up.
- the polarities of the switching signals “Ibus_low” and “Ibus_super_low” are determined by the previous ADC 208 reading, which in turn is determined by the load current ILoad drawn by the downstream device 122 .
- an extremely low current is accommodated by turning PM1-B 202 -B, and PM1-C 202 -C off, so that current flows only through PM1-A 202 -A.
- that branch is designed to receive only a negligible amount of the total available capacity of the pass transistor PM1 202 .
- a medium current level can be provided for by also turning on transistor PM1-B 202 -B, which in the illustrated device accommodates 1/16 of the possible FET current. Full capacity is achieved by also turning on PM1-C 202 -C. Details of how those results are accomplished are set out below, together with a truth table for the device and the associated input signals.
- a replica transistor PM0 204 generates a replica current based on the load current ILoad using an error amplifier 207 .
- the error amplifier 207 forces the drain voltage of replica transistor PM0 204 to be the same voltage as voltage Vbus through a negative feedback.
- the error amplifier 207 drives the gate of a transistor PM2 205 to maintain the transistor PM2 205 in saturation while transistors PM1 202 and PM0 204 are controlled by gate voltage Vg.
- the gate voltage Vg can be used for current limiting purposes. This arrangement results in accurate replication of the load current ILoad.
- the replicated current is mirrored by the current mirrors NM1-A 244 -A and NM1-B 244 -B, and PM3-A 264 -A and PM3-B 264 -B to flow through the current sense resistor 206 , developing the replicated load voltage 128 .
- ADC 208 receives analog replicated load voltage 128 and performs analog to digital conversion.
- ADC 208 includes both sample-and-hold and anti-aliasing filter circuits.
- the anti-aliasing feature prevents aliasing higher frequency signals back into the baseband of the ADC 208 .
- Reference amplifier 209 provides a 2.5V reference voltage, generated based on a band gap voltage. As the maximum current drawn across the pass transistor PM1 202 cannot exceed 2.5 A, the full-scale voltage of the ADC 208 is set to 2.5V. The mathematical calculation for calculating the resolution of an 8-bit ADC is shown below.
- 1 LSB equaling 9.76 mA corresponds to 9.76 mV. This mode is used for power rationing.
- the ADC 208 receives the replicated load voltage 128 signal and generates a corresponding digital value adc_data ⁇ N:0>.
- Other inputs include “adc_start”, an active high signal, which initiates the functioning of the ADC 108 .
- a clock signal “adc_clk” is also provided, as is a voltage reference signal Vref.
- the ADC 108 may also include an anti-aliasing filter for restricting the frequency bandwidth of the replicated load voltage 128 .
- the ADC 208 is an 8-bit successive-approximation-register (SAR) analog-to-digital converter (ADC).
- the ADC 208 outputs a digital value adc_data ⁇ N:0>, where N represents the number of bits in the output digital value. For example, an eight bit ADC will generate a digital value adc_data ⁇ 8:0>.
- the auto-ranging controller 110 uses the output digital value adc_data ⁇ N:0> to generate switching signals “Ibus_super_low” and “Ibus_low”. Those signals are used by the transistor arrangement 102 to dynamically configure the transistor arrangement 102 .
- the switching signal output is based on the value of adc_data ⁇ N:0>, and thus the auto-ranging controller 110 may include sensing and response circuitry, such as a logic circuit, a microprocessor, a microcontroller, or similar circuits and devices known in the art for generating the switching signals
- the auto-ranging controller 110 may include a memory device, such as a one-time programmable memory (OTP), for storing the threshold values of the digital value for determining the configuration of the transistor arrangement 102 . In normal operation, the transistor arrangement 102 is configured for maximum load current. Then, if the ADC 108 reading crosses a threshold value, the auto-ranging controller 110 sends an appropriate signal to the transistor arrangement 102 via switching signals “Ibus_super_low” and “Ibus_low”.
- OTP one-time programmable memory
- the auto-ranging system 200 may also operate in a charger emulation mode.
- the charger emulation mode demands greater accuracy in terms of the ADC resolution for load currents ILoad below 150 mA.
- a USB Port Power Controller using the auto-ranging system 200 may operate in the charger emulation mode for accurately determining the load current flow in microamperes.
- the transistor PM1-C 15/16 FET is turned off. Therefore, the auto-ranging controller 110 drives the switching signal “Ibus_super_low” low, and “Ibus_low” high.
- the switch S2 203 -B is in an open state, i.e., an off state.
- the control voltage Vg is cut off from the transistor PM1-C 202 -C.
- the transistor PM1-C gets turned off.
- a hysteresis of 10 LSB's was added to prevent switching between the FET's around the threshold of 156.25 mA.
- the auto-ranging system 200 may also operate in a third mode, removal detection.
- the removal detection mode demands even greater accuracy in terms of the ADC resolution for load current ILoad below 200 microamperes.
- a USB Port Power Controller using the auto-ranging system 200 may operate in the removal detection mode for accurately determining events when the downstream device 122 is removed and the load current falls below 200 micro amperes.
- the USB Port Power controller has a removal detection mechanism to detect the removal event.
- the auto-ranging system 200 When the auto-ranging system 200 is in charger emulation mode (i.e., the transistors PM1-A 202 -A and PM1-B 202 -B are turned ON), and the ADC 208 reading drops below 16 LSB's (each LSB being 610 micro amperes), only the transistor PM1-A 202 -A in the pass transistor PM1 202 is turned ON. If the ADC reading falls below a threshold reading, a removal event is detected.
- the threshold for removal detection can be set by one-time programmable memory (OTP) included in the auto-ranging controller 110 .
- OTP one-time programmable memory
- a hysteresis of 6 LSB's was used to switch between the state when only the transistor PM1-A 202 -A is turned ON and the state when all the three transistors are turned ON.
- a 200 mV drop comparator across Vbus was used to turn ON the Full transistor PM1 202 , if the drop across Vbus exceeds 200 mV.
- the current sense resistor 206 can be trimmed for process variations using OTP.
- the truth table below shows the combination for which the different transistors PM1-A 202 -A, PM1-B 202 -B, and PM1-C 202 -C in the pass transistor PM1 202 are turned ON for different values of switching signals “Ibus_low” and “Ibus_super_low”.
- pass transistor PM1 operates in one of three ranges depending on how many of its component transistors is turned on.
- the range labeled Full FET is enabled when all the three transistors PM1-A 202 -A, PM1-B 202 -B, and PM1-C 202 -C are turned ON, allowing current flow in all three branches of the pass transistor PM1 202 .
- Range 1/16 FET which passes 1/16 th of the maximum current, is operative when the transistors PM1-A 202 -A, and PM1-B 202 -B are turned ON.
- the lowest range, allowing only small amounts of current, range Small FET is operative when only the transistor PM1-A 202 -A is turned ON. This system yields a high precision measurement of load current by not only accurately detecting amperes of current in the high end but also detecting few microamperes of current at the low end.
- FIG. 3 is a flowchart depicting an exemplary method for auto-ranging an analog-to-digital converter for high precision current sensing.
- the method 300 illustrated in FIG. 3 may be used in conjunction with any of the systems or devices shown in the previously described figures, among other devices. In various embodiments, some of the method elements shown may be performed concurrently, in a different order than shown, or may be omitted. Additional method elements may be performed as desired. As shown, the method 300 may operate as follows.
- the transistor arrangement 102 provides load current 124 ILoad to meet the power requirements of the downstream device 122 .
- the transistor arrangement 102 connected to the downstream device 122 , is coupled between the supply voltage VS and the voltage Vbus.
- a control voltage signal Vg is provided to the transistor arrangement 102 to provide the required amount of the load current 124 ILoad.
- Switching signals “Ibus_super_low” and “Ibus_low” are fed to the transistor arrangement 102 to determine the configuration of the transistor arrangement 102 .
- the replica device 104 replicates the load current 124 ILoad.
- the replica device 104 is connected to the transistor arrangement 102 to generate a replica current 126 based on the load current 124 .
- An auto-zeroed error amplifier 207 forces the VDS on replica transistor PM0 204 to be the same as the pass transistor PM1 202 . This causes accurate replication of the load current 214 ILoad to the replica current 126 .
- the replica current 126 is transferred to the current sense resistor 106 .
- the replica current 126 is mirrored to flow through the current sense resistor 106 .
- a current mirror may be used to mirror the replicated current to the current sense resistor 106 .
- the current sense resistor 106 generates the replicated load voltage 128 based on the replicated current flowing through the current sense resistor 106 .
- the replicated load voltage 128 is fed to the ADC 108 as an input.
- the current sense resistor 106 monitors the replica current 126 and translates the amount of current into the replicated load voltage 128 that can be easily measured and monitored.
- the ADC 108 generates a digital value based on the replicated load voltage 128 .
- the replicated load voltage 128 is fed to the ADC 108 for analog to digital conversion of the voltage signal.
- the ADC 108 receives the replicated load voltage 128 signal and generates a digital value adc_data ⁇ N:0> corresponding to the replicated load voltage 128 .
- a signal “adc_start” initiates the functioning of the ADC 108 .
- the signal “adc_start” is an active high signal. Therefore, a high state of the signal “adc_start” signals the ADC 108 to start functioning.
- a clock signal “adc_clk” is supplied to the ADC 108 to clock the functioning of the ADC 108 .
- the ADC 108 also receives an auto-zero signal “adc_az_sar” to remove the offsets present in the ADC 108 .
- a voltage reference signal Vref is also provided to the ADC 108 to meet the voltage requirements.
- the replicated load voltage 128 is input to a sample-and-hold, and anti-aliasing filter circuit for filtering the replicated load voltage 128 signal to restrict frequency bandwidth of the replicated load voltage 128 signal.
- the sample-and-hold, and anti-aliasing filter circuit prevents the aliasing of higher frequency signals back into the baseband of the ADC 208 . This voltage is then fed to the ADC 108 .
- the transistor arrangement 102 is dynamically configured based on the digital value.
- the auto-ranging controller 110 uses the output digital value adc_data ⁇ N: 0 > to generate switching signals “Ibus_super_low” and “Ibus_low”.
- the switching signals “Ibus_super_low” and “Ibus_low” are used to dynamically change the configuration of the transistor arrangement 102 . If the ADC 108 reading crosses a threshold value, the auto-ranging controller 110 sends an appropriate signal to the transistor arrangement 102 via signals “Ibus_super_low” and “Ibus_low”.
- the auto-ranging controller 110 may include a memory device for storing the threshold values of the digital value for determining the configuration of the transistor arrangement 102 .
- the memory device may include a one-time programmable memory (OTP).
- the auto-ranging method 300 may also include switching the state of at least one of the transistors PM1-A 202 -A, PM1-B 202 -B, and PM1-C 202 -C to dynamically change the configuration of the transistor arrangement 102 .
- One or more of the three transistors PM1-A 202 -A, PM1-B 202 -B, and PM1-C 202 -C may be switched ON to provide the desired amount of current.
- the auto-ranging method 300 may also include determining a state of switching signals “Ibus_super_low” and “Ibus_low” from a switching table for a configuration of the transistor arrangement 102 .
- the auto-ranging controller 110 including a memory device may store a switching table. The switching table tabulates the state of switching signals for various configurations of the transistor arrangement 102 .
- the methods and systems discussed in the present disclosure provide techniques for auto-ranging an ADC for high precision current measurement.
- the disclosed techniques present a high precision auto-ranging scheme with low quiescent current demands.
- the circuit implementations of the auto-ranging systems will consume lesser die area.
- the auto-ranging technique allows the use of low resolution ADCs to achieve high resolution for very small load currents.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Dc-Dc Converters (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
1 LSB=(2.5 Amperes/28)=9.76 mA (1)
For an eight-bit ADC, 1 LSB equaling 9.76 mA corresponds to 9.76 mV. This mode is used for power rationing.
1 LSB=(156.25 milli Amperes/28)=610 micro Amperes (2)
TABLE I |
Pass Transistor transition |
Ibus_low | Ibus_super_low | |
0 | 0 | |
1 | 0 | 1/16 |
1 | 1 | Small FET |
Claims (17)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/307,022 US8624766B2 (en) | 2011-11-30 | 2011-11-30 | Method and system for auto-ranging analog-to-digital converter for current sensing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/307,022 US8624766B2 (en) | 2011-11-30 | 2011-11-30 | Method and system for auto-ranging analog-to-digital converter for current sensing |
Publications (2)
Publication Number | Publication Date |
---|---|
US20130135130A1 US20130135130A1 (en) | 2013-05-30 |
US8624766B2 true US8624766B2 (en) | 2014-01-07 |
Family
ID=48466337
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/307,022 Active 2031-12-27 US8624766B2 (en) | 2011-11-30 | 2011-11-30 | Method and system for auto-ranging analog-to-digital converter for current sensing |
Country Status (1)
Country | Link |
---|---|
US (1) | US8624766B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9444414B2 (en) | 2014-07-11 | 2016-09-13 | Qualcomm Incorporated | Current sense circuit using a single opamp having DC offset auto-zeroing |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5815107A (en) * | 1996-12-19 | 1998-09-29 | International Business Machines Corporation | Current source referenced high speed analog to digitial converter |
US6121913A (en) * | 1997-09-30 | 2000-09-19 | Intel Corporation | Electronic system with high speed, low power, A/D converter |
US20020113723A1 (en) * | 1999-08-25 | 2002-08-22 | Greig David Vetea | CMOS DAC with high impedance differential current drivers |
US7221191B2 (en) * | 2005-05-23 | 2007-05-22 | Analog Devices, Inc. | Signal samplers with enhanced dynamic range |
US7425909B2 (en) * | 2006-07-31 | 2008-09-16 | Analog Devices, Inc. | Low-noise programmable current source |
US7446683B2 (en) * | 2005-11-03 | 2008-11-04 | Samsung Electronics Co., Ltd. | Digital current source |
US20100085225A1 (en) * | 2008-10-07 | 2010-04-08 | Soon-Jyh Chang | Successive approximation adc with binary error tolerance mechanism |
US20110063154A1 (en) * | 2009-09-11 | 2011-03-17 | Steven Porter Hotelling | Touch controller with improved analog front end |
US20110140689A1 (en) * | 2009-12-10 | 2011-06-16 | Fernando Lalinda D | Signal amplitude adjustment to improve resolver-to-digital converter performance |
US8078122B2 (en) * | 2000-01-21 | 2011-12-13 | Qualcomm Incorporated | Interface between digital and analog circuits |
US20110304489A1 (en) * | 2010-06-15 | 2011-12-15 | Zoran Corporation | Methods of and arrangements for offset compensation of an analog-to-digital converter |
US20120013495A1 (en) * | 2010-07-16 | 2012-01-19 | Analog Devices, Inc. | System for digitizing a parameter having an unknown value |
US8325072B2 (en) * | 2011-01-10 | 2012-12-04 | Intel Mobile Communications GmbH | Calibration circuit and method for calibrating capacitive compensation in digital-to-analog converters |
-
2011
- 2011-11-30 US US13/307,022 patent/US8624766B2/en active Active
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5815107A (en) * | 1996-12-19 | 1998-09-29 | International Business Machines Corporation | Current source referenced high speed analog to digitial converter |
US6121913A (en) * | 1997-09-30 | 2000-09-19 | Intel Corporation | Electronic system with high speed, low power, A/D converter |
US20020113723A1 (en) * | 1999-08-25 | 2002-08-22 | Greig David Vetea | CMOS DAC with high impedance differential current drivers |
US8078122B2 (en) * | 2000-01-21 | 2011-12-13 | Qualcomm Incorporated | Interface between digital and analog circuits |
US7221191B2 (en) * | 2005-05-23 | 2007-05-22 | Analog Devices, Inc. | Signal samplers with enhanced dynamic range |
US7446683B2 (en) * | 2005-11-03 | 2008-11-04 | Samsung Electronics Co., Ltd. | Digital current source |
US7425909B2 (en) * | 2006-07-31 | 2008-09-16 | Analog Devices, Inc. | Low-noise programmable current source |
US20100085225A1 (en) * | 2008-10-07 | 2010-04-08 | Soon-Jyh Chang | Successive approximation adc with binary error tolerance mechanism |
US20110063154A1 (en) * | 2009-09-11 | 2011-03-17 | Steven Porter Hotelling | Touch controller with improved analog front end |
US20110140689A1 (en) * | 2009-12-10 | 2011-06-16 | Fernando Lalinda D | Signal amplitude adjustment to improve resolver-to-digital converter performance |
US20110304489A1 (en) * | 2010-06-15 | 2011-12-15 | Zoran Corporation | Methods of and arrangements for offset compensation of an analog-to-digital converter |
US20120013495A1 (en) * | 2010-07-16 | 2012-01-19 | Analog Devices, Inc. | System for digitizing a parameter having an unknown value |
US8274421B2 (en) * | 2010-07-16 | 2012-09-25 | Analog Devices, Inc. | System for digitizing a parameter having an unknown value |
US8325072B2 (en) * | 2011-01-10 | 2012-12-04 | Intel Mobile Communications GmbH | Calibration circuit and method for calibrating capacitive compensation in digital-to-analog converters |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9444414B2 (en) | 2014-07-11 | 2016-09-13 | Qualcomm Incorporated | Current sense circuit using a single opamp having DC offset auto-zeroing |
Also Published As
Publication number | Publication date |
---|---|
US20130135130A1 (en) | 2013-05-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9680471B2 (en) | Apparatus for a reduced current wake-up circuit for a battery management system | |
US7957116B2 (en) | System and method for detection of multiple current limits | |
US9797959B2 (en) | Battery fuel gauges using FET segment control to increase low current measurement accuracy | |
JP6669856B2 (en) | Apparatus and scheme for IO pinless calibration or trimming of on-chip regulator | |
US8400862B2 (en) | Wake-up control circuit for power-gated IC | |
EP0851583A1 (en) | Data processing system having an auto-ranging low voltage detection circuit | |
US8970283B2 (en) | Switching arrangement, integrated circuit comprising same, method of controlling a switching arrangement, and related computer program product | |
US8339296B2 (en) | Amplifying circuit and analog-digital converting circuit including same | |
US10296025B2 (en) | Apparatus for electric current measurement or calibration and associated methods | |
JP3994098B2 (en) | Method and circuit for testing a regulated power supply in an integrated circuit | |
US7741870B2 (en) | Multi-function input terminal | |
US9229053B2 (en) | Methods and apparatus for debugging lowest power states in System-On-Chips | |
US20140375130A1 (en) | Circuit, Use, and Method for Operating a Circuit | |
US8624766B2 (en) | Method and system for auto-ranging analog-to-digital converter for current sensing | |
CN110580096B (en) | Micro control unit capable of reducing power consumption and control method thereof | |
US10425073B1 (en) | Digital active diode circuit | |
Li et al. | A 0.78-µw 96-ch. deep sub-vt neural spike processor integrated with a nanowatt power management unit | |
KR100728572B1 (en) | Semiconductor memory apparatus | |
US10497455B2 (en) | Apparatus for sampling electrical signals with reduced leakage current and associated methods | |
US20240162894A1 (en) | Semiconductor Integrated Circuit and Semiconductor Device | |
CN110096843B (en) | LDO repair control circuit | |
CN117630517A (en) | Mode detector for DC-DC converter | |
CN116599530A (en) | Chip configuration circuit and chip | |
US20160313376A1 (en) | Detection circuit | |
JPH0491466A (en) | Semiconductor storage device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: STANDARD MICROSYSTEMS CORPORATION, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PULIJALA, SRINIVAS K.;REEL/FRAME:027303/0477 Effective date: 20111130 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: MERGER;ASSIGNOR:STANDARD MICROSYSTEMS CORPORATION;REEL/FRAME:044865/0164 Effective date: 20120501 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT, DELAWARE Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INC.;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:053311/0305 Effective date: 20200327 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: MICROSEMI CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: MICROCHIP TECHNOLOGY INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 |
|
AS | Assignment |
Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, MINNESOTA Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INC.;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:053468/0705 Effective date: 20200529 |
|
AS | Assignment |
Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT, MINNESOTA Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:055671/0612 Effective date: 20201217 |
|
AS | Assignment |
Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT, MINNESOTA Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:057935/0474 Effective date: 20210528 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 |