US8365043B2 - Efficient redundant memory unit array - Google Patents
Efficient redundant memory unit array Download PDFInfo
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- US8365043B2 US8365043B2 US13/411,606 US201213411606A US8365043B2 US 8365043 B2 US8365043 B2 US 8365043B2 US 201213411606 A US201213411606 A US 201213411606A US 8365043 B2 US8365043 B2 US 8365043B2
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- 230000006870 function Effects 0.000 claims description 62
- 238000004590 computer program Methods 0.000 claims description 3
- 238000011084 recovery Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 8
- 238000003491 array Methods 0.000 description 3
- 238000012937 correction Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
- G06F11/1092—Rebuilding, e.g. when physically replacing a failing disk
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- Reliability and performance of memory units is improved by arranging multiple memory units in an array, such as a Redundant Array of Independent Discs (or, RAID) system.
- RAID Level 6 (or, RAID 6) arranges memory units to provide protection for double memory unit failure, and failures when a single memory unit is rebuilding.
- FIG. 1 is a block diagram illustrating an embodiment of a system for an efficient redundant memory unit array.
- FIG. 2 is a block diagram illustrating an embodiment of a system with data blocks and parity blocks in a typical redundant memory unit array.
- FIG. 3 is a block diagram illustrating an embodiment of a system for organizing the parity of an efficient redundant memory unit array.
- FIG. 4 is a diagram illustrating an embodiment of functions for implementing an efficient redundant memory unit array.
- FIG. 5 is a flowchart illustrating an embodiment of a process for a whole stripe write of a given stripe.
- FIG. 7 is a flowchart illustrating an embodiment of a process for a single block reconstruction of a given stripe.
- FIG. 8 is a flowchart illustrating an embodiment of a process for a double block reconstruction of a given stripe.
- FIG. 9 is a flowchart illustrating an embodiment of a process for a degraded block read of a given stripe.
- FIG. 10 is a flowchart illustrating an embodiment of a process for a degraded block write of a given stripe.
- FIG. 12 is a flowchart illustrating an embodiment of a process for a degraded block write for a lost first-level parity block of a given stripe.
- the invention can be implemented in numerous ways, including as a process, an apparatus, a system, a composition of matter, a computer readable medium such as a computer readable storage medium or a computer network wherein program instructions are sent over optical or communication links.
- these implementations, or any other form that the invention may take, may be referred to as techniques.
- a component such as a processor or a memory described as being configured to perform a task includes both a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task.
- the order of the steps of disclosed processes may be altered within the scope of the invention.
- the term ‘processor’ refers to one or more devices, circuits, and/or processing cores configured to process data, such as computer program instructions.
- Each memory unit 110 is composed of a plurality of blocks 112 .
- Blocks 112 may be a data block that stores system data, or a parity block that stores redundant information to protect integrity of data blocks. Parity blocks are necessary for the error detection and error correction of data blocks, and with one parity block for a set of data blocks, the system can recover from a single data or parity block failure.
- the blocks 112 are arranged logically in “stripes” such that the first block 112 from each memory unit 110 ; B[1,1], B[2,1], B[3,1], . . . , and B[r,1] form a first stripe 114 .
- the second block from each memory unit forms a second stripe, and so on for p stripes.
- stripe 302 is partitioned into proper subsets of the set of data blocks, where throughout this specification, a “proper subset” refers to a portion of a given set of data blocks that is strictly contained in the given set, and thus there exists at least one data block which is not contained in the portion.
- the partitioning ensures that there are at least two proper subsets, and the union of the proper subsets includes every data block.
- each of the proper subsets are protected, up to data blocks D[m,1] 312 , D[m,2] 314 , up to D[m,n] 316 being protected by first-level parity block P[m] 318 .
- a second-level parity block Q 320 protects the entire stripe 302 .
- the first-level parity blocks P[1], . . . , P[m] only protect data blocks D[1,1], . . . , D[m,n] while the second level parity block Q only protects data blocks D[1,1], . . . , D[m,n].
- the first-level parity blocks P[1], . . . P[m] protect both data blocks D[1,1], . . . , D[m,n] and the second level parity block Q, while the second level parity block Q only protects data blocks D[1,1], . . . , D[m,n].
- FIG. 4 is a diagram illustrating an embodiment of functions for implementing an efficient redundant memory unit array. These functions may be implemented in read/write controller 104 .
- a second-level parity function of a given stripe with m proper subsets of up to n data blocks is as shown in 406 , to calculate Q, the second-level parity block of the given stripe.
- Q is a function, g_, of at least D[1,1], . . . , D[m,n], each data block in the stripe.
- a second-level parity update function of a given stripe is as shown in 410 , to calculate Q′, the updated second-level parity block after a data block D has been modified.
- Q′ is a function, v_, of at least D and Q, where Q is the second-level parity block before D was modified.
- a data recovery function of a given proper subset in a given stripe is as shown in 412 , to recalculate D[i], the i-th data block in the given proper subset, if the data within D[i] is lost.
- D[i] is a function, a_, of at least D[1], . . . D[i ⁇ 1], D[i+1], . . . , D[n], and P, where P is the first-level parity block of the given proper subset.
- FIG. 5 is a flowchart illustrating an embodiment of a process for a whole stripe write of a given stripe.
- a “whole stripe write” refers to the process of writing or rewriting data and parity blocks to a given stripe, such as when the stripe is first initialized.
- the process may be implemented in read/write controller 104 .
- step 502 the first-level parity blocks, P[1], . . . , P[m] of each of the m proper subsets in the given stripe are computed using either first-level parity function 402 or first-level parity alternate function 404 , depending on the system.
- step 502 the second-level parity block Q of the given stripe is computed using second-level parity function 406 .
- FIG. 6 is a flowchart illustrating an embodiment of a process for a single block update of a given stripe.
- a “single block update” refers to the process of updating a data block in a given proper subset of a given stripe. The process may be implemented in read/write controller 104 .
- FIG. 7 is a flowchart illustrating an embodiment of a process for a single block reconstruction of a given stripe.
- a “single block reconstruction” refers to the process of reconstructing the contents of a lost block and rewriting the contents to the given stripe.
- the process may be implemented in read/write controller 104 .
- step 702 the single lost block and its location is detected in the given stripe. If it is determined in step 704 that the lost block type is a first-level parity block, then control is transferred to 710 ; otherwise control is transferred to 706 . If it is determined in step 706 that the lost block type is a second-level parity block, then control is transferred to step 712 ; otherwise control is transferred to 708 .
- the lost data block is recomputed using data recovery function 412 from the other data blocks and the parity block in the corresponding proper subset of the lost data block.
- the lost first-level parity block is recomputed using first-level parity function 402 or first-level parity alternate function 404 , depending on the system.
- the lost second-level parity block is recomputed using second-level parity function 406 .
- the recomputed block is rewritten over the lost block in the given stripe.
- FIG. 8 is a flowchart illustrating an embodiment of a process for a double block reconstruction of a given stripe.
- a “double block reconstruction” refers to the process of reconstructing the contents of two lost blocks and rewriting the contents to the given stripe.
- the process may be implemented in read/write controller 104 .
- step 802 the two lost blocks and their locations are detected in the given stripe.
- step 804 with a double reconstruction it is required to read all the remaining blocks in the given stripe.
- step 806 the first lost block is recomputed using generic block recovery function 414 based on the remaining blocks read in 804 .
- step 808 the second lost block is recomputed using the single block reconstruction of FIG. 7 .
- step 902 the location of all blocks in the lost data block's corresponding proper subset are determined.
- step 904 the lost data block is recomputed for the read access by using data recovery function 412 .
- a double degraded read, or a degraded read with two lost blocks can be completed by performing a double block reconstruction if the lost blocks are both data blocks, or by performing a single block reconstruction if one lost block is a data block and one lost block is a parity block, or by not requiring any action if the lost blocks are both parity blocks.
- FIG. 10 is a flowchart illustrating an embodiment of a process for a degraded block write of a given stripe.
- a “degraded block write” refers to the process of reconstructing the contents of a lost block for the purposes of a write access to a data block. The process may be implemented in read/write controller 104 .
- the lost block In a degraded block write, the lost block cannot be rewritten to, but the data and parity blocks corresponding to the lost block must be updated for future access.
- step 1002 the lost block's location is determined. If it is determined in step 1004 that the lost block is a first-level parity block, then control is transferred to step 1010 ; otherwise control is transferred to step 1006 . If it is determined in step 1006 that the lost block is a second-level parity block, then control is transferred to step 1012 ; otherwise control is transferred to step 1008 .
- a degraded block write for a lost data block is performed.
- a degraded block write for a lost first-level parity block is performed.
- a degraded block write for a second-level parity block is performed.
- a double degraded write, or a degraded write with two lost blocks can be completed by performing a double block reconstruction if the lost blocks are both data blocks, or by performing a single block reconstruction if one lost block is a data block and one lost block is a parity block, or by not requiring any action if the lost blocks are both parity blocks.
- FIG. 11 is a flowchart illustrating an embodiment of a process for a degraded block write for a lost data block of a given stripe.
- the process of FIG. 11 is included in 1008 of FIG. 10 .
- the process may be implemented in read/write controller 104 .
- step 1102 the location of all blocks in the proper subset corresponding to the lost data block and the second-level parity block are determined.
- step 1104 all blocks in the proper subset corresponding to the lost data block and the second-level parity block are read.
- step 1106 the lost data block is recomputed using data recovery function 412 .
- step 1108 the corresponding first-level parity block is recomputed using the recomputed data block from 1106 using first-level parity update function 408 .
- step 1110 the second-level parity block is recomputed using the recomputed data block from 1106 using second-level parity update function 410 .
- step 1112 the updated first-level parity block and updated second-level parity block are written to the given stripe.
- FIG. 12 is a flowchart illustrating an embodiment of a process for a degraded block write for a lost first-level parity block of a given stripe.
- the process of FIG. 12 is included in 1010 of FIG. 10 .
- the process may be implemented in read/write controller 104 .
- step 1202 the location of the data block to be written and the second-level parity block are determined.
- step 1204 the contents of the data block to be updated and the second-level parity block are read.
- step 1206 the updated second-level parity block is computed using the second-level parity function 410 .
- step 1208 the updated data block and updated second-level parity block are written to the given stripe.
- FIG. 13 is a flowchart illustrating an embodiment of a process for a degraded block write for a lost second-level parity block of a given proper subset of a given stripe.
- the process of FIG. 13 is included in 1012 of FIG. 10 .
- the process may be implemented in read/write controller 104 .
- step 1302 the location of the data block to be written and the corresponding first-level parity block are determined.
- step 1304 the contents of the data block to be updated and the corresponding first-level parity block are read.
- step 1306 the corresponding updated first-level parity block is computed using either the first-level parity function 402 or first-level parity alternate function 404 , depending on the system.
- step 1308 the updated data block and corresponding updated first-level parity block are written to the given proper subset.
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US8539303B2 (en) * | 2010-12-20 | 2013-09-17 | Intel Corporation | Low overhead error correcting code protection for stored information |
GB201203557D0 (en) * | 2012-02-29 | 2012-04-11 | Qando Service Inc | Electronic communication |
JP6375886B2 (en) * | 2014-11-14 | 2018-08-22 | 富士通株式会社 | Parity layout determination program, parity layout determination method, storage apparatus and storage system |
US9760436B2 (en) * | 2015-06-10 | 2017-09-12 | Micron Technology, Inc. | Data storage error protection |
US10013323B1 (en) | 2015-09-29 | 2018-07-03 | EMC IP Holding Company LLC | Providing resiliency to a raid group of storage devices |
US10142419B2 (en) * | 2016-03-04 | 2018-11-27 | Sandisk Technologies Llc | Erasure correcting coding using data subsets and partial parity symbols |
US10218789B2 (en) | 2016-03-04 | 2019-02-26 | Western Digital Technologies, Inc. | Erasure correcting coding using temporary erasure data |
US10929226B1 (en) | 2017-11-21 | 2021-02-23 | Pure Storage, Inc. | Providing for increased flexibility for large scale parity |
CN110471789A (en) * | 2019-07-02 | 2019-11-19 | 深圳市金泰克半导体有限公司 | Solid state hard disk error correction method and solid state hard disk |
WO2021012164A1 (en) * | 2019-07-22 | 2021-01-28 | 华为技术有限公司 | Data reconstruction method and apparatus, computer device, storage medium, and system |
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US6970987B1 (en) * | 2003-01-27 | 2005-11-29 | Hewlett-Packard Development Company, L.P. | Method for storing data in a geographically-diverse data-storing system providing cross-site redundancy |
US7681105B1 (en) * | 2004-08-09 | 2010-03-16 | Bakbone Software, Inc. | Method for lock-free clustered erasure coding and recovery of data across a plurality of data stores in a network |
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EP0612015A1 (en) * | 1993-02-16 | 1994-08-24 | International Business Machines Corporation | Improved disk array system having special parity groups for data blocks with high update activity |
US7146524B2 (en) * | 2001-08-03 | 2006-12-05 | Isilon Systems, Inc. | Systems and methods for providing a distributed file system incorporating a virtual hot spare |
US7185144B2 (en) * | 2003-11-24 | 2007-02-27 | Network Appliance, Inc. | Semi-static distribution technique |
JP4285688B2 (en) * | 2003-10-22 | 2009-06-24 | ヤマハモーターハイドロリックシステム株式会社 | Oscillator for propulsion unit in outboard motor |
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US6970987B1 (en) * | 2003-01-27 | 2005-11-29 | Hewlett-Packard Development Company, L.P. | Method for storing data in a geographically-diverse data-storing system providing cross-site redundancy |
US7681105B1 (en) * | 2004-08-09 | 2010-03-16 | Bakbone Software, Inc. | Method for lock-free clustered erasure coding and recovery of data across a plurality of data stores in a network |
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