US7821480B2 - Charge transfer circuit and method for an LCD screen - Google Patents
Charge transfer circuit and method for an LCD screen Download PDFInfo
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- US7821480B2 US7821480B2 US11/648,173 US64817306A US7821480B2 US 7821480 B2 US7821480 B2 US 7821480B2 US 64817306 A US64817306 A US 64817306A US 7821480 B2 US7821480 B2 US 7821480B2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
- G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
- G09G2330/024—Power management, e.g. power saving using energy recovery or conservation with inductors, other than in the electrode driving circuitry of plasma displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Definitions
- Embodiments of the present invention generally relate to liquid crystal display screens (LCD) and, more specifically, to circuits for controlling such screens.
- LCD liquid crystal display screens
- FIG. 1 partially and very schematically shows a pixel 1 of a monochrome LCD screen or a sub-pixel of a color LCD screen.
- each pixel 1 is formed of a control switch M (typically, a MOS transistor) and of a capacitor C 1 , as a memory cell.
- a first conduction terminal of switch M is connected to a column conductor Col, common to all the switches of the display panel column.
- the other conduction terminal is connected to a first electrode of capacitor C 1 of the pixel, having its second electrode connected to ground, the dielectric of capacitor C 1 being formed of the liquid crystal used for the display.
- the gates of switches M are connected, in rows, to line conductors Row.
- switch M generates a capacitive element C between its gate and its source, and thus between line Row and the first electrode of capacitance C 1 of cell 1 .
- Columns conductors Col are controlled by a column driver circuit 2 (CDRIVER) generally setting the luminance reference values while row conductors Row are controlled in scan mode by a row driver circuit 3 (GDRIVER).
- CDRIVER column driver circuit 2
- GDRIVER row driver circuit 3
- each cell 1 forms a sub-pixel and the color is provided by a corresponding chromatic filter (RGB) arranged in front of each sub-pixel.
- RGB chromatic filter
- FIG. 2 partially and schematically shows the equivalent electric diagram of a liquid crystal display panel 10 and of its row control circuit
- FIG. 2 shows only two columns Col i and Col i+1 have been shown. Similarly, only five rows Row 1 , Row 2 , Row 3 , Row n-1 , and Row n have been shown.
- the screen integration on a substrate generally made of glass is no longer limited to the cells but also involves the row control circuits. These circuits comprise, for each row, an RS-type flip-flop B 1 , B 2 , B 3 . . .
- the S activation input of first flip-flop B 1 receives a scan start signal Start.
- the S activation input of flip-flop B 2 is connected to line Row 1 , downstream of switch K 1 with respect to the supply source.
- the S activation input of flip-flop B 3 is connected to line Row 2 , downstream of switch K 2 , etc. until the S activation input of the last flip-flop Bn connected to line Row n-1 .
- the R reset inputs of the flip-flops are respectively connected to the conductor of the row of next rank, downstream of the corresponding switch K, until the R input of the last flip-flop Bn which is looped back on row Row 1 .
- the line powering is generally performed by a line scanning.
- the rows of odd rank Row 1 , Row 3 , . . . , Row n-1 are interconnected upstream of switches K 1 , K 3 , . . . Kn- 1 to a terminal 32 while the lines of even rank Row 2 , . . . Row n are, upstream of their respective switches, connected to a terminal 33 .
- Terminals 32 and 33 are respectively connected to the junction points of pairs of switches Q 1 and Q 2 , respectively Q 3 and Q 4 , series-connected between terminals of application of respectively high and low turn-on and turn-off voltages V ON and V OFF .
- the scanning is performed by lines, starting, for example, with an odd line by turning on switches Q 1 and Q 4 and by turning off switches Q 2 and Q 3 for both supplying this odd line and forcing the turning-off of the even line of next rank.
- Signal Start applied on the S activation input of first flip-flop B 1 enables automatic row scanning.
- the addressing of an even row is performed symmetrically by turning off switches Q 1 and Q 4 and by turning on switches Q 2 and Q 3 .
- the switching of switches Q 1 to Q 4 is thus performed at the rate of the line scanning under control of a circuit 5 (CTRL).
- a problem is that the series associations of elements C and C 1 of all columns of a row are in parallel and have a charge opposite to that of the next row.
- a charge recovery stage is generally provided, thus enabling, for each column, using the power stored in the pixels to be turned off of the row which has just been addressed to help the turning-on of the pixels of the next line.
- terminals 32 and 33 are generally connected by an assembly of two diodes in ant-parallel D 1 and D 2 , each in series with a resistor R 1 and R 2 and a switch S 1 and S 2 .
- FIG. 3 shows an equivalent simplified electric diagram of FIG. 2 enabling better illustrating the operation of the H bridge formed of switches Q 1 , Q 2 , Q 3 , and Q 4 and the charge transfer circuits formed of switches S 1 , S 2 and of their diodes and resistors in series.
- the assembly of the cells of an odd line of the panel has been symbolized by a block 35 , a switch Mo, and an equivalent capacitance
- switches Q 1 and Q 4 are turned on, which causes the application of a voltage V ON on terminal 32 and V OFF on terminal 33 . A current can then flow to charge the capacitances of pixels of this first line.
- transistors Q 1 and Q 4 are turned off and switch S 1 is turned on for a so-called power recovery or transfer phase, which enables precharging the next line (even) by the discharge of the odd line which has just been addressed. This phase places the first odd and even lines in an intermediary equilibrium voltage.
- switches Q 2 and Q 3 are turned on to bring the voltage of the even line to level V ON and end the discharge of the first odd line to level V OFF .
- switches Q 2 and Q 3 are turned off and switch S 2 is turned on to enable precharge of the next odd line and thus resume the operation by turning-on of switches Q 1 and Q 4 .
- Embodiments of the present invention improve the control of flat screens, especially with liquid crystals, with a charge transfer stage to decrease the power losses of such screens.
- the control of the switches of charge transfer stages may also be simplified.
- One embodiment of the present invention provides a liquid crystal display charge transfer circuit including at least one inductive element connectable between a first and a second common terminal, respectively, to a first and to a second group of lines of the display.
- said terminals are connected to the respective junction points of switches connected, in pairs, in series between third and fourth terminals of application of high and low line supply voltages.
- the circuit comprises two switches respectively in parallel with a diode, these parallel associations being in series between said first and second terminals, and said inductive element being interposed between the two switches.
- each switch has a first conduction terminal connected to the inductive element and its control terminal connected to its second conduction terminal by a parallel association of a resistive element, of a capacitive element, and of a voltage-limiting element, the control terminal of each switch being further respectively connected to the midpoints of series associations of diodes connected between a fifth terminal of provision of a control current and said third terminal of application of the high line supply voltage.
- said control current is provided by a current source connected via a third switch to said fifth terminal.
- said capacitive element comprises the gate-source capacitance of a MOS transistor forming the corresponding switch.
- Embodiments of the present invention also provide a circuit for controlling a liquid crystal display.
- Embodiments of the present invention include a circuit for controlling a liquid crystal display and may also include such a control circuit in a flat liquid crystal display.
- FIG. 1 previously described, very schematically and partially shows a liquid crystal display to which embodiments of the present invention apply;
- FIG. 2 shows an equivalent electric diagram of a liquid crystal display and of a conventional line control circuit with a supply and charge transfer stage;
- FIG. 3 shows a simplified electric diagram of the supply and charge transfer circuit of FIG. 2 ;
- FIG. 4 very schematically and partially shows a power supply circuit of a liquid crystal display according to an embodiment of the present invention
- FIGS. 5A , 5 B, 5 C, 5 D, 5 E, 5 F, and 5 G are examples of timing diagrams illustrating the operation of the circuit of FIG. 4 ;
- FIG. 6 shows an embodiment of a circuit for controlling the charge transfer switches of the circuit of FIG. 4 ;
- FIG. 7 shows a variation of charge transfer circuit according to an embodiment of the present invention.
- a feature of an embodiment of the present invention is to use an inductive element in the charge transfer stage of the display.
- FIG. 4 shows an embodiment of the present invention. This drawing shows the equivalent electric diagram of a liquid crystal display in a representation to be compared with that of previously-described FIG. 3 .
- the assembly of cells of a line of odd rank is symbolized by a block 35 , a switch Mo, and an equivalent capacitor Co.
- the assembly of cells of a line of even rank is symbolized by a block 36 , a switch Me, and an equivalent capacitance Ce.
- the line conductors are connected via scan switches (not shown) to common points, respectively 32 for odd lines and 33 for even lines.
- the scan circuit has not been illustrated in FIG. 4 .
- Points 32 and 33 are connected to the junction points of switches Q 1 and Q 2 and switches Q 3 and Q 4 , respectively, between two terminals of application of respectively high and low supply voltages V ON and V OFF .
- charge transfer stage 38 connecting terminals 32 and 33 to form, with switches Q 1 to Q 4 , an H bridge comprises two switches S 1 and S 2 in series and between which an inductive element L is interposed, each switch being in parallel with diodes D 1 , D 2 having anodes connected to terminals 33 , and 32 , respectively.
- An inductance L made of ferrite may be used to optimize the loss reduction.
- FIGS. 5A , 5 B, 5 C, 5 D, 5 E, 5 F, and 5 G are timing diagrams illustrating, in examples of shapes of control signals of switches Q 1 and Q 4 , of switch S 1 , switches Q 2 and Q 3 , of switch S 2 , and in examples of shapes of voltages VCe and VCo across equivalent capacitors Ce and Co of the cells of an even and odd line, respectively, as well as in an example of shape of current I in the charge transfer stage, the operation of the circuit of FIG. 4 .
- the turning-on of the first odd line starts with a turning-on of switches Q 1 and Q 4 (time t 0 ), with switches Q 2 and Q 3 as well as switches S 1 and S 2 being off.
- Voltage VCo is then brought to level V ON and voltage VCe is brought to level V OFF .
- the luminance reference values are provided by the column control circuit (not shown). In the indicated voltage levels, the influences of the different voltage drops of the switching elements in the ON state are neglected.
- switches Q 1 and Q 4 are turned off and switch S 1 is turned on to precharge the first even line by flowing of a current through diode D 2 , inductance L, and switch S 1 .
- the current through inductance L increases up to a maximum Ip before canceling at a time t 2 .
- voltage VCe switches from level V OFF to a level dose to level V ON and voltage VCo switches from level V ON to a level dose to level V OFF .
- the interval between times t 1 and t 2 is a function of equivalent capacitance Co and of the value of inductance
- the maximum current Ip also depends on equivalent capacitance Co and on inductance L and is equal to V ON -V OFF ⁇ square root over (Co/2L) ⁇ .
- switch S 1 is off and switches Q 3 and Q 2 are on to complete the charge of the cells of the even line (voltage VCe) to level V ON and end the discharge of the cells of the odd line (voltage VCo) to level V OFF .
- the addressing of the cells of the first even line is performed during this phase.
- switch S 2 is turned on while switches Q 2 and Q 3 are off to cause a precharge of the cells of the next odd line.
- a current then flows through diode D 1 , inductance L, and switch S 2 .
- This current is of course in reverse direction with respect to the current between times t 1 and t 2 . It also has a non-linear increase and decrease and a peak value V ON -V OFF ⁇ square root over (Ce/2L) ⁇ which is a function of equivalent capacitance Ce.
- the interval between times t 4 and t 5 during which a current flows through inductance L, and which conditions the duration for voltages VCe and VCo to respectively reach levels dose to levels V OFF and V ON depends on equivalent capacitance
- An advantage of this embodiment of the present invention is that it decreases losses by taking advantage of the resonance introduced by inductance L in charge transfer phases. Losses P during this resonance phase can be expressed as:
- FIG. 6 shows the electric diagram of a circuit for controlling switches S 1 and S 2 of FIG. 4 , here made in the form of MOS transistors.
- the cells of an even and odd line are symbolized by the respective equivalent capacitances Ce and Co in series with respective resistances Re and Ro between terminals 33 , and 32 , respectively, and a grounded terminal 44 .
- the respective gates of transistors S 1 and S 2 are connected to terminals 33 and 32 by parallel assemblies, each formed of a resistor R 11 or R 12 , of a capacitor C 1 or C 2 (possibly formed of the gate-source capacitance of transistor S 1 or S 2 ), and of a Zener diode DZ 1 or DZ 2 (or another voltage-limiting element).
- the function of diodes DZ 1 and DZ 2 is to protect the gates of transistors S 1 and S 2 .
- These gates are further connected to the respective junction points of diodes D 11 and D 12 , and D 13 and D 14 , connecting a terminal 40 , connected by a switch S 3 to a source 41 of a preferably constant current ( 10 ), to a terminal 42 of application of voltage V ON .
- Source 41 is supplied by a D.C. voltage Vcc, at least greater than voltage V ON plus the on-state gate-source voltage (Vgs ON ) of transistor S 1 or S 2 .
- Diodes D 11 to D 14 selectively charge the gate of transistor S 1 or S 2 having its conduction terminal on the side of switches Q at the low level (typically V OFF at the beginning, but the selection operates as long as the voltage is smaller than V ON ).
- Resistors R 11 and R 12 are used to discharge the gates of transistors S 1 and S 2 in the quiescent state.
- Switch S 3 is controlled to be turned on at times t 1 , t 4 , t 1 ′, etc. to initiate the power recovery phases.
- capacitor C 1 Once capacitor C 1 has reached a sufficient charge, it causes the turning-on of transistor S 1 . In fact, as compared with the illustration of FIGS. 5A to 5G , this translates as a slight delay (set by the on-state gate-source voltage Vgs ON of transistor S 1 , the current in source 41 , and capacitor C 1 ) on turning-on of switch S 1 with respect to time t 1 . A flowing of the current then establishes from the cells of the odd line (Co, Ro), through diode D 2 , inductance L, and switch S 1 , to reach the cells of the next even line (Ce, Re). Transistor S 1 remains on as long as the voltage across its gate is positive and is greater than the threshold set by diode DZ 1 . Switch S 3 remains on until capacitor C 1 has a sufficient charge (for example, on the order of from 10 to 12 volts). This amounts, for example, to a few hundreds of nanoseconds.
- An advantage of the circuit of FIG. 6 is that it enables controlling both switches S 1 and S 2 by means of a same control circuit, and thus solving the problems of floating voltages of the conventional circuit ( FIG. 3 ).
- the control signal of switch S 3 which is designated CT in FIG. 6 , is, for example, generated by a circuit of control and synchronization ( 5 , FIG. 2 ) of the screen circuits (generally, of microprocessor type).
- a circuit such as illustrated in FIG. 6 may be formed with components having the following values:
- FIG. 7 illustrates a variation of the circuit of FIG. 4 according to which two inductive elements L 1 and L 2 replace the conventional resistors of the assembly of FIG. 3 according to another embodiment of the present invention.
- Such a variation enables decreasing losses with respect to this conventional assembly of FIG. 3 but it does not enable simplifying the control as in the assembly of FIGS. 4 and 6 .
- Flat screens such as LCD panels including embodiments of the present invention may be contained in a variety of different types of electronic devices, such as portable devices like cellular phones, personal digital assistants (PDAs), calculators, video/audio players, and so on, and may be contained in electronic systems such as computer systems.
- portable devices like cellular phones, personal digital assistants (PDAs), calculators, video/audio players, and so on
- PDAs personal digital assistants
- video/audio players and so on
- electronic systems such as computer systems.
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Abstract
Description
the sum comprising all the cells in the odd row). The assembly of the cells of the even rows has been symbolized by a
the sum comprising all the cells in the even row). For simplification, the flip-flops used for the scanning have not been illustrated in
The maximum current Ip also depends on equivalent capacitance Co and on inductance L and is equal to VON-VOFF·√{square root over (Co/2L)}.
where Ceq=Ce=Co and where Req represents the sum of the resistances of the conductive row lines and of the switches in the on state. In the former example of a 4.7-nF equivalent capacitance Ceq, of a 166-kHz frequency, of a 35-volt voltage VON, and of a −25-volt voltage VOFF, and estimating at 20 ohms the total equivalent resistance of the lines, a 0.213-watt loss to be compared with the previously-obtained 1.4 watts is obtained
-
- L=100 μH;
- C1=C2=1 nF;
- R 11=R12=100 kΩ; and
- DZ1=DZ2=10 Volts.
Claims (14)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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FR0554130 | 2005-12-29 | ||
FR0554130 | 2005-12-29 | ||
FR05/54130 | 2005-12-29 |
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US20070188437A1 US20070188437A1 (en) | 2007-08-16 |
US7821480B2 true US7821480B2 (en) | 2010-10-26 |
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US11/648,173 Expired - Fee Related US7821480B2 (en) | 2005-12-29 | 2006-12-29 | Charge transfer circuit and method for an LCD screen |
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US8786592B2 (en) | 2011-10-13 | 2014-07-22 | Qualcomm Mems Technologies, Inc. | Methods and systems for energy recovery in a display |
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US3509374A (en) * | 1967-05-01 | 1970-04-28 | Itt | Double pole electronic switching circuit |
US5717437A (en) | 1994-12-07 | 1998-02-10 | Nec Corporation | Matrix display panel driver with charge collection circuit used to collect charge from the capacitive loads of the display |
US5821923A (en) | 1995-02-23 | 1998-10-13 | U.S. Philips Corporation | Picture display device |
US5914588A (en) * | 1997-10-27 | 1999-06-22 | Lucent Technologies Inc. | DC/DC converters having dual, EMI-quiet outputs |
US5936598A (en) * | 1996-03-08 | 1999-08-10 | Nec Corporation | Capacitive load drive circuit and method |
US5943030A (en) | 1995-11-24 | 1999-08-24 | Nec Corporation | Display panel driving circuit |
US6064158A (en) | 1995-07-04 | 2000-05-16 | Denso Corporation | Electroluminescent display device |
US6160531A (en) * | 1998-10-07 | 2000-12-12 | Acer Display Technology, Inc. | Low loss driving circuit for plasma display panel |
US20010029102A1 (en) * | 2000-03-23 | 2001-10-11 | Nec Corporation | Drive circuit for plasma display panel |
US7151518B2 (en) * | 2001-09-13 | 2006-12-19 | Hitachi, Ltd. | Liquid crystal display device and driving method of the same |
US20060290631A1 (en) * | 2005-06-22 | 2006-12-28 | Bi-Hsien Chen | Driving Circuit of Plasma Display Panel |
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US7391401B2 (en) * | 2002-12-04 | 2008-06-24 | Samsung Electronics Co., Ltd. | Liquid crystal display, and apparatus and method of driving liquid crystal display |
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2006
- 2006-12-29 US US11/648,173 patent/US7821480B2/en not_active Expired - Fee Related
Patent Citations (13)
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US3509374A (en) * | 1967-05-01 | 1970-04-28 | Itt | Double pole electronic switching circuit |
US5717437A (en) | 1994-12-07 | 1998-02-10 | Nec Corporation | Matrix display panel driver with charge collection circuit used to collect charge from the capacitive loads of the display |
US5821923A (en) | 1995-02-23 | 1998-10-13 | U.S. Philips Corporation | Picture display device |
US6064158A (en) | 1995-07-04 | 2000-05-16 | Denso Corporation | Electroluminescent display device |
US5943030A (en) | 1995-11-24 | 1999-08-24 | Nec Corporation | Display panel driving circuit |
US5936598A (en) * | 1996-03-08 | 1999-08-10 | Nec Corporation | Capacitive load drive circuit and method |
US5914588A (en) * | 1997-10-27 | 1999-06-22 | Lucent Technologies Inc. | DC/DC converters having dual, EMI-quiet outputs |
US6160531A (en) * | 1998-10-07 | 2000-12-12 | Acer Display Technology, Inc. | Low loss driving circuit for plasma display panel |
US20010029102A1 (en) * | 2000-03-23 | 2001-10-11 | Nec Corporation | Drive circuit for plasma display panel |
US7151518B2 (en) * | 2001-09-13 | 2006-12-19 | Hitachi, Ltd. | Liquid crystal display device and driving method of the same |
US7391401B2 (en) * | 2002-12-04 | 2008-06-24 | Samsung Electronics Co., Ltd. | Liquid crystal display, and apparatus and method of driving liquid crystal display |
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Non-Patent Citations (1)
Title |
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French Search Report, FR0554130, Aug. 4, 2006. |
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US20070188437A1 (en) | 2007-08-16 |
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