US7709920B2 - Photodiode arrangement - Google Patents
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- US7709920B2 US7709920B2 US11/979,902 US97990207A US7709920B2 US 7709920 B2 US7709920 B2 US 7709920B2 US 97990207 A US97990207 A US 97990207A US 7709920 B2 US7709920 B2 US 7709920B2
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- 238000009792 diffusion process Methods 0.000 claims abstract description 183
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 166
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 165
- 239000010703 silicon Substances 0.000 claims abstract description 165
- 239000004065 semiconductor Substances 0.000 claims abstract description 161
- 239000012535 impurity Substances 0.000 claims abstract description 81
- 244000126211 Hericium coralloides Species 0.000 claims description 18
- 239000010410 layer Substances 0.000 description 352
- 229910052581 Si3N4 Inorganic materials 0.000 description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 23
- 238000004519 manufacturing process Methods 0.000 description 18
- 238000000206 photolithography Methods 0.000 description 18
- 238000010521 absorption reaction Methods 0.000 description 14
- 230000003287 optical effect Effects 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000000034 method Methods 0.000 description 12
- 239000007943 implant Substances 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 101000701286 Pseudomonas aeruginosa (strain ATCC 15692 / DSM 22644 / CIP 104116 / JCM 14847 / LMG 12228 / 1C / PRS 101 / PAO1) Alkanesulfonate monooxygenase Proteins 0.000 description 2
- 101000983349 Solanum commersonii Osmotin-like protein OSML13 Proteins 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 208000000453 Skin Neoplasms Diseases 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000000844 anti-bacterial effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- -1 e.g. Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 201000000849 skin cancer Diseases 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
Definitions
- the present invention relates to a photodiode arrangement which receives light, especially ultraviolet rays to generate a current.
- an N+ diffusion layer which has an N-type impurity diffused therein with a high concentration and is formed into a comb shape like “E” and a P+ diffusion layer which has a P-type impurity diffused therein with a high concentration and is formed into a shape like “ ⁇ ” are laterally arranged to face each other in a silicon semiconductor layer having an N-type impurity diffused therein with a low concentration on an SOI (Silicon On Insulator) substrate which has the silicon semiconductor layer with a thickness of approximately 150 nm formed on a silicon substrate to sandwich a buried oxide film there between in such a manner that a comb tooth portion of the N+ diffusion layer meshes with a comb tooth portion of the P+ diffusion layer, and a predetermined voltage is applied to a metal wiring line electrically connected with the N+ diffusion layer and the P+ diffusion layer to detect an intensity of an ultraviolet ray (see, e.g., Japanese Patent Application Laid-open No. 1620
- the amount of ultraviolet irradiation is increasing due to destruction of the ozone layer and concern over the influence of ultraviolet rays contained in solar light on the human body and/or the environment is increasing.
- an ultraviolet ray is invisible light in an ultraviolet range of a wavelength of 400 nm or below.
- the ultraviolet ray is classified into a long-wave ultraviolet ray (an UV-A wave: a wavelength of approximately 320 to 400 nm), a medium-wave ultraviolet ray (an UV-B wave: a wavelength of approximately 280 to 320 nm), and a short-wave ultraviolet ray (an UV-C wave: a wavelength of approximately 280 nm or below).
- an UV-A wave a wavelength of approximately 320 to 400 nm
- an UV-B wave a wavelength of approximately 280 to 320 nm
- an UV-C wave a wavelength of approximately 280 nm or below
- the UV-A wave darkens skin and reaches inner skin to cause aging
- the UV-B wave inflames skins to possibly provoke skin cancer
- the UV-C wave has a strong bactericidal function but is absorbed in the ozone layer.
- a photodiode arrangement comprising an insulating layer; and a plurality of silicon semiconductor layers having different thicknesses formed on the insulating layer, wherein each of the plurality of silicon semiconductor layers has a low-concentration diffusion layer formed by diffusing one of a P-type impurity or an N-type impurity therein with a low concentration; a P-type high-concentration diffusion layer formed by diffusing a P-type impurity therein with a high concentration; and an N-type high-concentration diffusion layer formed by diffusing an N-type impurity therein with a high concentration, and wherein the P-type high-concentration diffusion layer and the N-type high-concentration diffusion layer formed in a respective one of the plurality of silicon semiconductor layers are arranged to face each other with the low-concentration diffusion layer formed in said respective one of the plurality of silicon semiconductor layers interposed therebetween.
- a photodiode arrangement comprising an insulating layer; a first silicon semiconductor layer formed on the insulating layer; a second silicon semiconductor layer which is formed on the insulating layer and which has a thickness which is less than that of the first silicon semiconductor layer; a first photosensitive element which is formed in the first silicon semiconductor layer and in which a first P-type high-concentration diffusion layer having a P-type impurity diffused therein with a high concentration and a first N-type high-concentration diffusion layer having an N-type impurity diffused therein with a high concentration are arranged to face each other with a first low-concentration diffusion layer having one of a P-type impurity or an N-type impurity diffused therein with a low concentration interposed therebetween; and a second photosensitive element in which a second P-type high-concentration diffusion layer having a P-type impurity diffused therein with a high concentration and a second N-type high
- ultraviolet rays in the three wavelength ranges can be separated to obtain intensities thereof based on a calculation of outputs from photosensitive elements formed in the respective silicon semiconductor layers having different thicknesses, and it is possible to obtain an effect of readily providing the photodiode arrangement which can separate ultraviolet rays in the three wavelength ranges to detect intensities thereof.
- FIG. 1 is an explanatory drawing showing a top face of a photodiode arrangement according to Embodiment 1;
- FIG. 2 is an explanatory drawing showing a cross section of the photodiode arrangement according to Embodiment 1;
- FIGS. 3A-3D is series of steps (P 1 )-(P 4 ), respectively, showing in cross section a manufacturing method of a photo IC according to Embodiment 1 of the present invention
- FIGS. 4A-4D is a series of additional steps (P 5 )-(P 8 ), respectively, showing in cross section the manufacturing method of the photo IC according to Embodiment 1;
- FIGS. 5A-5D is a series of additional steps (P 9 )-(P 12 ), respectively, showing in cross section the manufacturing method of the photo IC according to Embodiment 1;
- FIG. 6 illustrates step (P 13 ) in cross section of the manufacturing method of the photo IC according to Embodiment 1;
- FIG. 7 is a graph showing wavelength dependence of an optical absorption coefficient of silicon ( 100 );
- FIG. 8 is a graph showing an optical absorption ratio depending on a thickness of a silicon semiconductor layer
- FIG. 9 is a graph showing a wavelength with which an optical absorption ratio becomes 10%
- FIG. 10 is a graph showing an optical absorption ratio of each photosensitive element in the photodiode arrangement according to Embodiment 1;
- FIGS. 11A and 11B are explanatory drawings showing a detection method for an ultraviolet ray in each wavelength range in the photodiode arrangement according Embodiment 1;
- FIG. 12 is a graph showing output characteristics of the photodiode arrangement according to Embodiment 1;
- FIG. 13 is an explanatory drawing showing a cross section of a photodiode arrangement according to Embodiment 2;
- FIGS. 14A-14D is a series of steps (PA 1 )-(PA 4 ), respectively, showing in cross section a manufacturing method of a photo IC according to Embodiment 2 of the present invention
- FIGS. 15A-15D is a series of additional steps (P 5 )-(P 8 ), respectively, showing in cross section the manufacturing method of the photo IC according to Embodiment 2;
- FIGS. 16A-16D is a series of additional steps (PA 9 )-(PA 12 ), respectively, showing in cross section the manufacturing method of the photo IC according to Embodiment 2;
- FIG. 17 illustrates step (PA 13 ) in cross section of the manufacturing method of the photo IC according to Embodiment 2;
- FIG. 18 is a graph showing a sheet resistance of a P+ diffusion layer according to Embodiment 2.
- FIG. 19 is a graph showing a sheet resistance of an N+ diffusion layer according to Embodiment 2.
- FIG. 1 is an explanatory drawing showing a top face of a photodiode according to Embodiment 1
- FIG. 2 is an explanatory drawing showing a cross section of the photodiode arrangement according to Embodiment 1
- FIGS. 3A-3D , 4 A- 4 D, 5 A- 5 D, and 6 are explanatory drawings showing a manufacturing method of a photo IC according to Embodiment 1.
- FIG. 2 is a cross-sectional view taken along a cutting-plane line A-A in FIG. 1 .
- reference numeral 1 denotes a photodiode arrangement (generally referred to simply as a photodiode for the remainder of this specification), and it is constituted of first and second photosensitive elements 11 and 21 formed in first and second silicon semiconductor portions 4 a and 4 b with different thicknesses of a semiconductor wafer having an SOI structure in which a silicon semiconductor layer 4 composed of single-crystal silicon with a small thickness is formed on a silicon substrate (not shown) made of silicon (Si) to sandwich a buried oxide film 3 as an insulating layer formed of a silicon oxide (SiO 2 ) therebetween.
- the first and second silicon semiconductor portions 4 a and 4 b will be generally referred to simply as first and second silicon semiconductor layers for the remainder of this specification.
- the thicknesses of the first and second silicon semiconductor layers 4 a and 4 b according to this embodiment are set to gradually different thicknesses in a thickness range of 50 nm or below to separate ultraviolet rays in three wavelength ranges in an ultraviolet range of a wavelength of 400 nm or below and to detect intensities of these ultraviolet rays.
- the optical absorption coefficient ⁇ has wavelength dependence as shown in FIG. 7 , and such a graph as depicted in FIG. 8 can be obtained when Expression (1) is used to obtain the optical absorption ratio I/Io in accordance with each thickness (Z) of the silicon semiconductor layer 4 .
- the optical absorption ratio I/Io becomes 0.1 or below, i.e., 10% or below, the optical absorption coefficient I/Io is precipitously reduced, and its wavelength shifts in a direction of a short wavelength, i.e., an ultraviolet range direction as the thickness is decreased.
- the thickness of the silicon semiconductor layer 4 it is desirable to set the thickness of the silicon semiconductor layer 4 to 50 nm or below in order to selectively detect the ultraviolet range alone, and setting a lower limit of this thickness to 3 nm is preferable.
- the thickness of the silicon semiconductor layer 4 is set to 3 nm or above because assimilating irregularities in thickness when forming the silicon semiconductor layer 4 in the semiconductor wafer becomes difficult if the thickness is smaller than this value.
- the first silicon semiconductor layer 4 a is formed with a thickness larger than that of the second silicon semiconductor layer 4 b , and the first silicon semiconductor layer 4 a has a thickness of 35 nm whilst the second silicon semiconductor layer 4 b has a thickness of 10 nm.
- a first diode forming region 6 a where the first photosensitive element 11 of the photodiode 1 is formed and transistor forming regions 8 a and 8 b where an nMOS element 31 and a pMOS element 41 as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are formed are set on the first silicon semiconductor layer 4 a whose thickness is set as explained above, and a second diode forming region 6 b where the second photosensitive element 21 of the photodiode 1 is formed is set on the second silicon semiconductor layer 4 b.
- MOSFETs Metal Oxide Semiconductor Field Effect Transistors
- an element isolating region 10 where element isolating layer pattern 9 (generally referred to simply as element isolating layer 9 in the remainder of this specification) is set in a rectangular frame-like region surrounding each of the first and second diode forming regions 6 a and 6 b and the transistor forming regions 8 a and 8 b.
- the element isolating layer 9 is formed of an insulating material, e.g., a silicon oxide in the first silicon semiconductor layer 4 a having the large thickness in the element isolating region 10 to reach a buried oxide film 3 , and it has the function of electrically isolating the neighboring first and second diode forming regions 6 a and 6 b of the first and second silicon semiconductor layers 4 a and 4 b and the neighboring transistor forming regions 8 a and 8 b of the first silicon semiconductor layer 4 a from each other.
- an insulating material e.g., a silicon oxide in the first silicon semiconductor layer 4 a having the large thickness in the element isolating region 10 to reach a buried oxide film 3 , and it has the function of electrically isolating the neighboring first and second diode forming regions 6 a and 6 b of the first and second silicon semiconductor layers 4 a and 4 b and the neighboring transistor forming regions 8 a and 8 b of the first silicon semiconductor layer 4 a
- the element isolating layer 9 is shown with hatching for discrimination in this explanation.
- the first photosensitive element 11 is formed in the first diode forming region 6 a set in the first silicon semiconductor layer 4 a having the large thickness.
- Reference numeral 12 denotes a first P+ diffusion layer or region as a P-type high-concentration diffusion layer which is a diffusion layer formed by diffusing a P-type impurity, e.g., boron (B) in the first silicon semiconductor layer 4 a in the first diode forming region 6 a with a relatively high concentration.
- a P-type impurity e.g., boron (B)
- the first P+ diffusion layer 12 is formed into a comb-like shape including a peak portion 12 a which is in contact with one side 9 a on the inner side of the element isolating layer 9 a and a plurality of comb tooth portions 12 b extending from the peak portion 12 a toward the other side 9 b on the inner side of the element isolating layer 9 facing the one side 9 a.
- the first P+ diffusion layer 12 is formed into a shape like “ ⁇ ” by extending the two comb tooth portions 12 b from the peak portion 12 a.
- Reference numeral 14 denotes a first N+ diffusion layer or region as an N-type high-concentration diffusion layer which is a diffusion layer formed by diffusing an N-type impurity, e.g., phosphorus (P) or arsenic (As) which is the type opposite to that of the P-type high-concentration diffusion layer in the first silicon semiconductor layer 4 a in the first diode forming region 6 a with a relatively high concentration.
- N-type impurity e.g., phosphorus (P) or arsenic (As) which is the type opposite to that of the P-type high-concentration diffusion layer in the first silicon semiconductor layer 4 a in the first diode forming region 6 a with a relatively high concentration.
- the first N-type diffusion layer 14 is formed into a comb-like shape including a peak portion 14 a which is in contact with the other side 9 b on the inner side of the element isolating layer 9 and a plurality of comb tooth portions 14 b extending from the peak portion 14 a toward the one side 9 a facing the other side 9 b .
- Doped diffusion regions will frequently be referred to as diffusion layers for the remainder of this specification.
- the first N+ diffusion layer 14 is formed into a shape like “E” by extending the three comb tooth portions 14 b from both ends and a center of the peak portion 14 a.
- Reference numeral 15 denotes a first P ⁇ diffusion layer or region as a low-concentration diffusion layer which is a diffusion layer formed by diffusing a P-type impurity with a relatively low concentration in the first silicon semiconductor layer 4 a which is in contact with the first P+ diffusion layer 12 and the first N+ diffusion layer 14 arranged to face each other in such a manner that the comb tooth portions 12 b and 14 b mesh with each other with a gap therebetween.
- the first P ⁇ diffusion layer is a part where each pair of an electron and a hole is produced by an ultraviolet ray absorbed in a depletion layer formed therein.
- the first photosensitive element 11 of the photodiode 1 is formed in such a manner that the first P+ diffusion layer 12 and the first N+ diffusion layer 14 are oppositely arranged to sandwich the first P ⁇ diffusion layer 15 with the respective comb tooth portions 12 b and 14 b meshing with each other and rims except boundaries 16 with respect to the first P ⁇ diffusion layer 15 are in contact with the element isolating layer 9 .
- the second photosensitive element 21 is formed in the second diode forming region 6 b set in the second silicon semiconductor layer 4 b with the small thickness like the first photosensitive element 11 .
- the second photosensitive element 21 includes a second P+ diffusion layer or region as a P-type high-concentration diffusion layer and a second N+ diffusion layer or region 24 as an N-type high-concentration diffusion layer.
- the second P+ diffusion layer or region 22 is formed into a comb shape like “ ⁇ ” with a plurality of comb tooth portions 22 b extending from a peak portion 22 a which is in contact with one side 9 c on the inner side of the element isolating layer 9 toward the other side 9 d on the inner side of the element isolating layer 9 facing the one side 9 c , and has a P-type impurity diffused therein with a relatively high concentration.
- the second N+ diffusion layer 24 is formed into a comb shape like “E” with a plurality of comb tooth portions 24 b extending from a peak portion 24 a which is in contact with the other side 9 d on the inner side of the element isolating layer 9 toward the opposed one side 9 c , and has an N-type impurity diffused therein with a relatively high concentration.
- the second P+ diffusion layer 22 and the second N+ diffusion layer 24 are arranged to face each other with their comb tooth portions 22 b and 24 b meshing each other.
- the second photosensitive element 21 also includes a second P ⁇ diffusion layer 25 as a low-concentration diffusion layer which is interposed between the second P+ diffusion layer 22 and the second N+ diffusion layer 24 , is in contact with each boundary 26 , and has a P-type impurity diffused therein with a relatively low concentration.
- the first and second photosensitive elements 11 and 21 are formed together with an nMOS element 31 and a pMOS element 41 formed on the first silicon semiconductor layer 4 a.
- the nMOS element 31 according to this embodiment is formed in the transistor forming region 8 a set in the first silicon semiconductor layer 4 a having the large thickness.
- reference numeral 32 denotes a gate oxide film, and it is an insulating film which is formed of an insulating material, e.g., a silicon oxide and has a relatively small film thickness.
- Reference numeral 33 designates a gate electrode, and it is an electrode formed of, e.g., polysilicon in which an impurity that is of the same type as a source layer or region 35 (which will be explained later) (the N type in this embodiment) is diffused with a relatively high concentration.
- the gate electrode 33 is formed at a central part of the transistor forming region 8 a in a gate length direction to face the first silicon semiconductor layer 4 a in the transistor forming region 8 a with the gate oxide film 32 being sandwiched therebetween, and a sidewall 34 formed of an insulating material, e.g., a silicon nitride (Si 3 N 4 ) is formed on a side surface of the gate electrode 33 .
- the source layer 35 and a drain layer or region 36 in which the N-type impurity is diffused with a relatively high concentration are formed in the first silicon semiconductor layer 4 a on both sides of the gate electrode 33 in the transistor forming region 8 a , and respective extension portions 37 of the source layer 35 and the drain layer 36 are formed on the respective gate electrode 33 sides with an impurity which is of the same type as that in the source layer 35 being diffused therein with a concentration lower than that of the source layer 35 (which will be referred to as a medium concentration).
- a channel region 38 in which the P-type impurity that is opposite to that in the source layer 35 is diffused with a relatively low concentration and a channel of the nMOS element 31 is configured is formed in the first silicon semiconductor layer 4 a between the respective extension portions 37 of the source layer 35 and the drain layer 36 below the gate oxide film 32 .
- the pMOS element 41 has a source layer or region 45 , a drain layer or region 46 , and a gate electrode 43 .
- the source layer 45 and the drain layer 46 are likewise formed in the transistor forming region 8 b set in the first silicon semiconductor layer 4 a having the large thickness with the impurity which is of a type opposite to that in the nMOS element 31 .
- the gate electrode 43 faces a channel region 48 between respective extension portions 47 of the source layer 45 and the drain layer 46 to sandwich a gate oxide film 42 therebetween, and has a sidewall 34 on a side surface thereof.
- the first and second P+ diffusion layers 12 and 22 of the first and second photosensitive element 11 and 21 and the source and drain layers 45 and 46 of the pMOS element 41 according to this embodiment are formed by diffusing the same P-type impurity with the same concentration.
- first and second N+ diffusion layers 14 and 24 of the first and second photosensitive elements 11 and 21 and the source and drain layers 35 and 36 of the nMOS element 31 are formed by diffusing the same N-type impurity with the same concentration.
- first and second P ⁇ diffusion layers 15 and 25 of the first and second photosensitive elements 11 and 21 and the channel region 38 of the nMOS element 31 are formed by diffusing the same P-type impurity with the same concentration.
- the gate length direction means a direction extending from the source layer 35 or 45 toward the drain layer 36 or 46 in parallel with the top face of the first silicon semiconductor layer 4 a or an opposite direction.
- reference numeral 51 denotes a resist mask as a mask member which is a mask pattern formed by exposing and developing a positive type or negative type resist applied to the silicon semiconductor layer 4 based on photolithography, and the resist mask functions as a mask in etching or ion implantation according to this embodiment.
- a manufacturing method for a photo IC according to this embodiment will now be explained based on steps indicated by P in FIGS. 3 to 6 .
- the silicon semiconductor layer 4 of the semiconductor wafer according to this embodiment is formed with the thickness 354 nm equal to that of the first silicon semiconductor layer 4 a by forming a sacrificial oxide film by a thermal oxidation method on a thin silicon layer of the semiconductor wafer having the SOI structure formed on a buried oxide film 3 by a SIMOX (Separation by Implanted Oxygen) method while leaving the thin silicon layer or of the semiconductor wafer having the SOI structure formed by bonding the thin silicon layer on the buried oxide film 3 .
- SIMOX Separatation by Implanted Oxygen
- a pad oxide film having a small film thickness is formed by the thermal oxidation method on the silicon semiconductor layer 4 of the semiconductor wafer having the silicon semiconductor layer 4 with a predetermined thickness (35 nm in this embodiment) formed on the buried oxide film 3 , a silicon nitride film composed of a silicon nitride is formed on the pad oxide film by a CVD (Chemical Vapor Deposition) method, and the resist mask (not shown) which covers the first diode forming regions 6 a and 6 b and the transistor forming regions 8 a and 8 b , i.e., in which the exposed element isolating region 10 is exposed is formed on the silicon nitride film based on photolithography. This is used as a mask to remove the silicon nitride film based on anisotropic etching so that the pad oxide film is exposed.
- the resist mask is removed, the exposed silicon nitride film is used as a mask, and the silicon semiconductor layer 4 in the element separating region 10 is oxidized to form the element isolating layer 9 reaching the buried oxide film 3 based on a LOCOS (Local Oxidation Of Silicon) method.
- the silicon nitride film and the pad oxide film are removed by wet etching to form the element isolating layer 9 in each element isolating region 10 of the silicon semiconductor layer 4 .
- a silicon nitride film 53 made of a silicon nitride is formed on the silicon semiconductor layer 4 by the CVD method, and a resist mask 51 in which the second diode forming region 6 b is exposed is formed on the silicon nitride film 53 based on photolithography. This is used as a mask to remove the silicon nitride film 53 based on anisotropic etching, thereby exposing the silicon semiconductor layer 4 in the second diode forming region 6 b.
- the resist mask 51 formed at the step P 1 is removed, and a sacrificial oxide film 54 is formed on the silicon semiconductor layer 4 in the second diode forming region 6 b by the thermal oxidation method.
- the sacrificial oxide film 54 is removed by wet etching and the silicon nitride film 53 is immersed in hot phosphoric acid to be removed thereby forming the second silicon semiconductor layer 4 b having a thickness of 10 nm as a thickness of the silicon semiconductor layer 4 in the second diode forming region 6 b.
- the silicon semiconductor layer 4 covered with the silicon nitride film 53 in the regions other than the second diode forming region 6 b is formed as the first silicon semiconductor layer 4 a.
- the resist mask 51 in which the first diode forming region 6 a and the transistor forming region 8 a of the first silicon semiconductor layer 4 a and the second diode forming region 6 b of the second silicon semiconductor layer 4 b are exposed is formed based on photolithography.
- This is used as a mask to implant a P-type impurity ion in the exposed first and second silicon semiconductor layers 4 a and 4 b , thereby forming the first P-diffusion layer 15 of the first photosensitive element 11 and the channel region 38 of the nMOS element 31 having the P-type impurity diffused therein with a relatively low concentration in the first silicon semiconductor layer 4 a and also forming the second P ⁇ diffusion layer 25 of the second photosensitive element 21 having the P-type impurity diffused therein with a relatively low concentration in the second silicon semiconductor layer 4 b.
- the resist mask 51 formed at the step P 4 is removed, and the resist mask 51 in which the transistor forming region 8 b of the first silicon semiconductor layer 4 a is exposed is again formed based on photolithography. This is used as a mask to implant an N-type impurity ion into the exposed first silicon semiconductor layer 4 a , thereby forming the channel region 48 of the pMOS element 41 having the N-type impurity diffused therein with a relatively low concentration in the first silicon semiconductor layer 4 a in the transistor forming region 8 b.
- the top faces of the first and second silicon semiconductor layers 4 a and 4 b are oxidized based on the thermal oxidation method to form a silicon oxide film 55 , and polysilicon is deposited on the silicon oxide film 55 by the CVD method to form a polysilicon layer 56 having a relatively large film thickness.
- a resist mask (not shown) which covers regions where the gate electrodes 33 and 43 are formed at the central parts of the transistor forming regions 8 a and 8 b in the gate length direction is formed on the polysilicon layer 56 based on photolithography. This is used as a mask to etch the polysilicon layer 56 and the silicon oxide film 55 based on, e.g., dry etching, the gate electrodes 33 and 43 facing the channel regions 38 and 48 in the first silicon semiconductor layer 4 a through the gate oxide films 32 and 42 are formed, and the resist mask is removed.
- the resist mask 51 in which regions where the first and second N+ diffusion layers 14 and 24 in the first and second diode forming regions 6 a and 6 b (the parts having the shape like “E” depicted in FIG. 1 ) and the transistor forming region 8 a are exposed is formed based on photolithography.
- This is used as a mask to implant an N-type impurity ion into the exposed first and second silicon semiconductor layers 4 a and 4 b and the polysilicon in the gate electrode 33 , thereby forming the extension portions 37 of the nMOS element 31 having the N-type impurity diffused therein with a medium concentration in the first silicon semiconductor layer 4 a on both sides of the gate electrode 33 and diffusing the N-type impurity having a medium concentration in the gate electrode 33 and the first and second silicon semiconductor layers 4 a and 4 b in the regions where the first and second N+ diffusion layers 14 and 24 are formed.
- the resist mask 51 formed at the step P 8 is removed, and the resist mask 51 in which regions where the first and second P+ diffusion layers 12 and 22 are formed (the parts having the shape like “ ⁇ ” depicted in FIG. 1 ) in the first and second diode forming regions 6 a and 6 b and the transistor forming region 8 b are exposed is formed based on photolithography.
- This is used as a mask to implant a P-type impurity ion in the exposed first and second silicon semiconductor layers 4 a and 4 b and the polysilicon in the gate electrode 43 , thereby forming the extension portions 47 of the pMOS element 41 having the P-type impurity diffused therein with a medium concentration in the first silicon semiconductor layer 4 a on both sides of the gate electrode 43 and diffusing the P-type impurity having the medium concentration in the gate electrode 43 and the first and second silicon semiconductor layers 4 a and 4 b in the regions where the first and second P+ diffusion layers 12 and 22 are formed.
- the resist mask 51 formed at the step P 9 is removed, and a silicon nitride is deposited on the entire surfaces of the gate electrodes 33 and 43 and the first and second silicon semiconductor layers 4 a and 4 b by the CVD method to form a silicon nitride film.
- the silicon nitride film is etched based on anisotropic etching to expose the top faces of gate electrodes 33 and 43 and the top faces of the first and second silicon semiconductor layers 4 a and 4 b , and the sidewall 34 is formed on side surfaces of the gate electrodes 33 and 43 .
- the same resist mask 51 as that at the step P 8 is formed based on photolithography. This is used as a mask to implant an N-type impurity ion into the exposed first and second silicon semiconductor layers 4 a and 4 b and the polysilicon in the gate electrode 33 , thereby forming the source layer 35 and the drain layer 36 of the nMOS element 31 having the N-type impurity diffused therein with a relatively high concentration in the first silicon semiconductor layer 4 a on both sides of the sidewall 34 and also forming the first and second N+ diffusion layers 14 and 24 of the first and second photosensitive elements 11 and 21 in the first and second silicon semiconductor layers 4 a and 4 b . Further, the N-type impurity is diffused in the gate electrode 33 with a relatively high concentration.
- the resist mask 51 formed at the step P 11 is removed, and the same resist mask 51 as that at the step P 9 is formed based on photolithography.
- This is used as a mask to implant a P-type impurity ion in the exposed first and second silicon semiconductor layers 4 a and 4 b and the polysilicon in the gate electrode 43 , thereby forming the source layer 45 and the drain layer 46 of the pMOS element 41 having the P-type impurity diffused therein with a relatively high concentration in the first silicon semiconductor layer 4 a on both sides of the sidewall 34 and also forming the first and second P+ diffusion layers 12 and 22 of the first and second photosensitive elements 11 and 21 in the first and second silicon semiconductor layers 4 a and 4 b .
- the P-type impurity is diffused in the gate electrode 43 with a relatively high concentration.
- the resist mask 51 formed at the step P 12 is removed, and a heat treatment of activating each diffusion layer is performed to form the first and second photosensitive elements 11 and 21 and the nMOS element 31 and the pMOS element 41 according to this embodiment.
- an insulating material e.g., a silicon oxide is deposited with a relatively large thickness on the entire surfaces of the first and second silicon semiconductor layers 4 a and 4 b on, e.g., the element isolating layer 9 based on a CVD method, and the upper surface of the insulating material is flattened to form an interlayer insulating film.
- a resist mask (not shown) having opening portions where the interlayer insulating film in contact hole forming regions on the second P+ diffusion layer 22 and the second N+ diffusion layer 24 is exposed is formed on the interlayer insulating film based on photolithography.
- the resist mask is removed, then the contact holes are filled with an electroconductive material based on the CVD method or a sputtering method to form contact plugs, and the upper surfaces of the contact plugs are flattened to expose the upper surface of the interlayer insulating film.
- the contact holes on the first P+ diffusion layer 12 , the first N+ diffusion layer 14 , the source layers 35 and 45 , and the drain layers 36 and 46 are filled with the electroconductive material to form contact plugs, and the upper surfaces of the contact plugs are flattened to expose the upper surface of the interlayer insulating film.
- the contact holes reaching the gate electrodes 33 and 43 are filled with an electroconductive material to form the contact plugs, and a flattening processing is carried out to form a photo IC 58 according to this embodiment.
- the same P-type impurity as that in the channel region 38 of the nMOS element 31 constituting the photo IC 58 is diffused with the same concentration. Therefore, at the step P 4 of forming the channel region 38 of the nMOS element 31 , the same resist mask 51 can be used to simultaneously form the channel region 38 , thereby simplifying the manufacturing process of the photo IC 58 .
- the same N-type impurity as that in the source layer 35 and the drain layer 36 of the nMOS element 31 constituting the photo IC 58 is diffused with the same concentration. Therefore, at the step P 11 of forming the source layer 35 and the drain layer 36 of the nMOS element 31 , the same resist mask 51 can be used to simultaneously form these layers, thereby simplifying the manufacturing process of the photo IC 58 .
- the same P-type impurity as that in the source layer 45 and the drain layer 46 of the pMOS element 41 constituting the photo IC 58 is diffused in the first and second P+ diffusion layers 12 and 22 of the first and second photosensitive elements 11 and 21 with the same concentration. Therefore, at the step P 12 of forming the source layer 45 and the drain layer 46 of the pMOS element 41 , the same resist mask 51 can be used to simultaneously form these layers, thereby simplifying the manufacturing process of the photo IC 58 .
- FIG. 10 shows a result of calculating an optical absorption ratio I/Io with respect to a wavelength when the photodiode 1 formed of the first and second photosensitive elements 11 and 12 in which the first and second P ⁇ diffusion layers 15 and 25 have different thicknesses is uniformly irradiated with ultraviolet rays having all wavelengths in the ultraviolet range.
- the thickness of the first P ⁇ diffusion layer 15 in the first photosensitive layer 11 used for the calculation is 35 nm, and the thickness of the second P ⁇ diffusion layer 25 in the second photosensitive element 21 used for the same is 10 nm.
- the first photosensitive element 11 (the thickness of the first P-type diffusion layer 15 : 35 nm) and the second photosensitive element 21 (the thickness of the second P-type diffusion layer 25 : 10 nm) according to this embodiment have different optical absorption characteristics.
- these characteristics are utilized to perform the calculation based on, e.g., a difference, absolute values, a proportional multiple, or a combination of these outputs, a UV-A wave, a UV-B wave, and a UV-C wave (which will be referred to as an A wave, a B wave, and a C wave hereinafter) can be separated from each other to detect their intensities.
- the first and second photosensitive elements 11 and 21 are uniformly irradiated with the same ultraviolet rays having all the wavelengths, these elements have different optical absorption ratio characteristics because their silicon semiconductor layers 4 have different thicknesses. Therefore, as shown in FIG. 11A , when an output from the second photosensitive element 21 is multiplied by approximately 1.1 (a broken line shown in FIG. 11A ) and the obtained result is subtracted from an output from the first photosensitive element 11 , the C wave is canceled out and its difference is an output including approximately 5% of each of the A wave and the B wave.
- the resultant difference is an incident light intensity of the B wave.
- the difference is an incident light intensity of the A wave.
- FIG. 12 shows a result of obtaining each incident light intensity of each short wavelength interval like the above-explained calculation.
- the first and second photosensitive elements including the P+ diffusion layer and the N+ diffusion layer arranged to face each other with the P ⁇ diffusion layer sandwiched therebetween are formed on the first and second silicon semiconductor layers with the different thicknesses formed on the insulating layer. Therefore, the ultraviolet rays in the three wavelength ranges can be separated to obtain their intensities from the two types of outputs from the first and second photosensitive elements based on the calculation, thereby readily providing a photodiode which can separate the ultraviolet rays in the three wavelength ranges to detect their intensities.
- FIG. 13 is an explanatory drawing showing a cross section of a photodiode according to Embodiment 2
- FIGS. 14A-14D , 15 A- 15 D, 16 A- 16 D, and 17 are explanatory drawings showing a manufacturing method of a photo IC according to Embodiment 2.
- FIG. 13 is a cross-sectional view showing a cross section like FIG. 2 according to Embodiment 1, and a top face of the photodiode is the same as that in FIG. 1 according to Embodiment 1.
- like reference numerals denote parts equal to those in Embodiment 1, thereby eliminating a need for an explanation thereof.
- a second silicon semiconductor layer 4 b having a small thickness is formed in a second P ⁇ forming region 61 in a second P ⁇ diffusion layer 61 (which is a region sandwiched between the second P+ diffusion layer 22 having the shape like “ ⁇ ” and the second N+ diffusion layer 24 having the shape like “E” in the second transistor forming region 8 b depicted in FIG. 1 ) alone of a second P ⁇ diffusion layer 25 as shown in FIGS. 14 to 17 .
- a second P+ diffusion layer 22 and a second N+ diffusion layer 24 according to this embodiment are formed with the same thickness as that of a first silicon semiconductor layer 4 a.
- the second silicon semiconductor layer 4 b is set to have a thickness which is not smaller than 3 nm and less than 30 nm
- the first silicon semiconductor layer 4 a is set to have a thickness which is not smaller than 30 nm and not greater than 50 nm.
- the silicon semiconductor layer 4 is set to the thickness which is not smaller than 3 nm and not greater than 50 nm for the same reason as the Embodiment 1.
- Each of the second P+ diffusion layer 22 and the second N+ diffusion layer 24 is set to the thickness which is not smaller than 30 nm when the second silicon semiconductor layer 4 b is set to the thickness which is less than 30 nm because a sheet resistance is extremely increased and an output from a photosensitive element 21 is lowered in both a P+ diffusion layer depicted in FIG. 18 and an N+ diffusion layer shown in FIG. 19 when each of the second P+ diffusion layer 22 and the second N+ diffusion layer 24 is set to the thickness which is less than 30 nm.
- an abscissa in each of FIGS. 18 and 19 represents a width of the P+ diffusion layer or the N+ diffusion layer in a gate length direction, i.e., a width in the cross-sectional direction depicted in FIG. 13 .
- a manufacturing method of the photo IC according to this embodiment will now be explained with reference to steps indicated by PA in FIGS. 14 to 17 .
- the silicon semiconductor layer 4 of a semiconductor wafer according to this embodiment is formed with the same thickness 35 nm as that of the first silicon semiconductor layer 4 a like Embodiment 1.
- an element isolating layer 9 is formed in each element isolating region 10 of the silicon semiconductor layer 4 , a silicon nitride film 53 composed of a silicon nitride is formed on the silicon semiconductor layer 4 by a CVD method, a resist mask 51 in which the second P ⁇ forming region 61 of a second diode forming region 6 b is exposed is formed on the silicon nitride film 53 based on photolithography, and this is used as a mask to remove the silicon nitride film 53 based on anisotropic etching, thereby exposing the silicon semiconductor layer 4 in the second P ⁇ forming region 61 .
- the resist mask 51 formed at the step P 1 is removed, and a sacrificial oxide film 54 is formed on the silicon semiconductor layer 4 in the second P ⁇ forming region 61 based on a thermal oxidation method.
- the sacrificial oxide film 54 is removed by wet etching, the silicon nitride film 53 is removed by immersion in a hot phosphoric acid, thereby forming the second silicon semiconductor layer 4 b in which the silicon semiconductor layer 4 in the second P ⁇ forming region 61 has a thickness of 10 nm.
- the silicon semiconductor layer 4 covered with the silicon nitride film 53 in regions other than the second P ⁇ forming region 61 is formed as a first silicon semiconductor layer 4 a.
- a resist mask 51 in which the first diode forming region 6 a and a transistor forming region 8 a of the first silicon semiconductor layer 4 a and the second diode forming region 6 b of the second silicon semiconductor layer 4 b are exposed is formed based on photolithography. This is used as a mask to form a first P ⁇ diffusion layer 15 of the first photosensitive element 11 and a channel region 38 of an nMOS element 31 and also form a second P ⁇ diffusion layer 25 of the second photosensitive element 21 having a P-type impurity diffused therein with a relatively low concentration in the second diode forming region 6 b including the second silicon semiconductor layer 4 b like the step P 4 according to Embodiment 1.
- the resist mask 51 formed at step P 4 is removed to form a channel region 48 of a pMOS element 41 as in step P 5 according to Embodiment 1.
- a silicon oxide film 55 is formed, and a polysilicon layer 56 is further formed on this film.
- gate electrodes 33 and 43 facing the channel regions 38 and 48 of the first silicon semiconductor layer 4 a through gate oxide films 32 and 42 are formed.
- a resist mask 51 in which regions where the first and second N+ diffusion layers 14 and 24 in the first and second diode forming regions 6 a and 6 b are formed (parts having the shape like “E” shown in FIG. 1 ) are exposed is formed based on photolithography.
- This is used as a mask to implant an N-type impurity ion into the exposed first silicon semiconductor layer 4 a and polysilicon in the gate electrode 33 , thereby forming extension portions 37 of the nMOS element 31 having an N-type impurity diffused therein with a medium concentration in the first silicon semiconductor layer 4 a on both sides of the gate electrode 33 and diffusing the N-type impurity with the medium concentration in the gate electrode 33 and the first silicon semiconductor layer 4 a in the regions where the first and second N+ diffusion layers 14 and 24 are formed.
- the resist mask 51 formed at step PA 8 is removed, and a resist mask 51 in which regions where first and second P+ diffusion layers 12 and 22 in the first and second diode forming regions 6 a and 6 b are formed (parts having the shape like “ ⁇ ” depicted in FIG. 1 ) and the transistor forming region 8 b are exposed is formed based on photolithography.
- This is used as a mask to implant a P-type impurity ion into the exposed first silicon semiconductor layer 4 a and polysilicon in the gate electrode 43 , thereby forming extension portions 47 of the pMOS element 41 having a P-type impurity diffused therein with a medium concentration in the first silicon semiconductor layer 4 a on both sides of the gate electrode 43 and diffusing the P-type impurity with the medium concentration in the gate electrode 43 and the first silicon semiconductor layer 4 a in the regions where the first and second P+ diffusion layers 12 and 22 are formed.
- step P 10 As for step P 10 according to Embodiment 1, sidewalls 34 are formed on side surfaces of the gate electrodes 33 and 43 .
- the same resist mask as that at step PA 8 is formed based on photolithography. This is used as a mask to implant an N-type impurity ion into the exposed first silicon semiconductor layer 4 a and polysilicon in the gate electrode 33 , thereby forming a source layer 35 and a drain layer 36 of the nMOS element 31 having the N-type impurity diffused therein with a relatively high concentration in the first silicon semiconductor layer 4 a , also forming the first and second N+ diffusion layers 14 and 24 of the first and second photosensitive elements 11 and 21 in the first silicon semiconductor layer 4 a , and diffusing the N-type impurity in the gate electrode 33 with a relatively high concentration.
- the resist mask 51 formed at step PA 11 is removed, and the same resist mask 51 as that at step PA 9 is formed based on photolithography. This is used as a mask to implant a P-type impurity ion into the exposed first silicon semiconductor layer 4 a and polysilicon in the gate electrode 43 , thereby forming a source layer 45 and a drain layer 46 of the pMOS element 41 having the P-type impurity diffused therein with a relatively high concentration in the silicon semiconductor layer 4 a on both sides of the sidewall 34 and the first and second P+ diffusion layers 12 and 22 of the first and second photosensitive elements 11 and 21 in the first silicon semiconductor layer 4 a , and diffusing the P-type impurity in the gate electrode 43 with a relatively high concentration.
- the resist mask 51 formed at step PA 12 is removed, and a heat treatment of activating each diffusion layer is performed, thereby forming the first and second photosensitive elements 11 and 21 , the nMOS element 31 , and the pMOS element 41 according to this embodiment.
- an interlayer insulating film is formed like Embodiment 1, and a resist mask (not shown) having opening portions in which the first and second P+ diffusion layers 12 and 22 , the first and second N+ diffusion layers 14 and 24 , and the interlayer insulating film in contact hole forming regions on the source layers 35 and 45 and the drain layers 36 and 46 are exposed is formed on the interlayer insulating film based on photolithography.
- a resist mask (not shown) having opening portions in which the first and second P+ diffusion layers 12 and 22 , the first and second N+ diffusion layers 14 and 24 , and the interlayer insulating film in contact hole forming regions on the source layers 35 and 45 and the drain layers 36 and 46 are exposed is formed on the interlayer insulating film based on photolithography.
- contact plugs reaching the respective diffusion layers are formed, and top faces of the contact plugs are flattened to expose a top face of the interlayer insulating film.
- the contact holes reaching the gate electrodes 33 and 43 are filled with an electroconductive material to form contact plugs, and a flattening processing is carried out to form the photo IC 58 according to this embodiment.
- the impurity which is of the same type as that in the respective diffusion layers of the nMOS element 31 and the pMOS element 41 is diffused with the same concentration in the respective diffusion layers of the thus formed first and second photosensitive elements 11 and 21 as in Embodiment 1. Therefore, at each forming step, the same resist mask 51 can be used to simultaneously form each layer, thereby simplifying the manufacturing process of the photo IC 58 .
- the second P ⁇ diffusion layer 25 in the second photosensitive element 21 has a thickness which is less than 30 nm, sheet resistance does not become excessive and output from the second photosensitive element 21 is not reduced since the second P+ diffusion layer 22 and the second N+ diffusion layer 25 are formed in the first silicon semiconductor layer 4 a having a thickness which is not smaller than 30 nm.
- depth of each contact hole can be equal to the depth of the contact hole formed in the diffusion layer, e.g., the source layer and others, and the step of forming each contact plug can be simplified, thereby achieving simplification of the manufacturing process of the photo IC 58 .
- the thickness of the second P ⁇ diffusion layer 25 is less than 30 nm has been explained in this embodiment, but forming the second P+ diffusion layer 22 and the second N+ diffusion layer 25 in the silicon semiconductor layer 4 a enables acquiring an effect of simplifying the process of forming each contact plug like the above example even if the thickness of the second P ⁇ diffusion layer 25 is not smaller than 30 nm.
- the thickness of the second silicon semiconductor layer in which the second P ⁇ diffusion layer is formed is less than 30 nm
- setting the thickness of each of the second P+ diffusion layer and the second N+ diffusion layer to 30 nm or above enables preventing a sheet resistance of the high-concentration diffusion layer in the second photosensitive element from becoming excessive, thereby avoiding a reduction in an output from the second photosensitive element.
- forming the second P+ diffusion layer and the second N+ diffusion layer in the first silicon semiconductor layer enables setting the top faces of the second P+ diffusion layer and the second N+ diffusion layer on a level with the top faces of the source layer and the drain layer of an MOSFET, and the process of forming each contact plug can be simplified, thereby achieving simplification of the manufacturing process of the photo IC.
- the low-concentration diffusion layer of the photosensitive element in the photodiode is formed in each of the silicon semiconductor layers having the two types of thicknesses. It is to be noted that the example where the low-concentration diffusion layer of the photosensitive element in the photodiode is formed in each of the silicon semiconductor layers having the two types of thicknesses has been explained in each embodiment, but this layer may be formed in each of the silicon semiconductor layers having three or more types of thicknesses.
- the P+ diffusion layer has the shape like “ ⁇ ” and the N+ diffusion layer has the shape like “E” in each embodiment, the shapes of these layers may be counterchanged, and the number of comb tooth portions may be increased.
- these layers may be arranged in such a manner that the peak portions alone face each other to sandwich the low-concentration diffusion layer without providing the comb tooth portions.
- the silicon semiconductor layer is the silicon semiconductor layer formed on the buried oxide film as the insulating layer of the SOI substrate
- the silicon semiconductor layer may be, e.g., a silicon semiconductor layer of an SOS (Silicon On Sapphire) substrate formed on a sapphire substrate as an insulating layer or may be a silicon semiconductor layer of an SOQ (Silicon On Quartz) substrate formed on a quartz substrate as an insulating layer.
- SOS Silicon On Sapphire
- SOQ Silicon On Quartz
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Abstract
Description
I/Io=exp(−αZ) (1)
where Z is an entering depth of light, I is a light intensity at the depth Z, and Io is an incident light intensity.
Claims (14)
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JP2007044465A JP2008147606A (en) | 2006-11-14 | 2007-02-23 | Photodiode |
JP2007-044465 | 2007-02-23 |
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US7935546B2 (en) * | 2008-02-06 | 2011-05-03 | International Business Machines Corporation | Method and apparatus for measurement and control of photomask to substrate alignment |
JP2017084875A (en) * | 2015-10-23 | 2017-05-18 | ラピスセミコンダクタ株式会社 | Semiconductor device and method of manufacturing semiconductor device |
US20220005845A1 (en) * | 2020-07-02 | 2022-01-06 | Bardia Pezeshki | Cmos-compatible short wavelength photodetectors |
WO2022076894A1 (en) | 2020-10-08 | 2022-04-14 | Avicenatech Corp. | Integration of oe devices with ics |
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