US7671638B2 - Negative N-epi biasing sensing and high side gate driver output spurious turn-on prevention due to N-epi P-sub diode conduction during N-epi negative transient voltage - Google Patents
Negative N-epi biasing sensing and high side gate driver output spurious turn-on prevention due to N-epi P-sub diode conduction during N-epi negative transient voltage Download PDFInfo
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- US7671638B2 US7671638B2 US12/146,736 US14673608A US7671638B2 US 7671638 B2 US7671638 B2 US 7671638B2 US 14673608 A US14673608 A US 14673608A US 7671638 B2 US7671638 B2 US 7671638B2
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- 230000001052 transient effect Effects 0.000 title claims abstract description 10
- 230000002265 prevention Effects 0.000 title description 2
- 230000003071 parasitic effect Effects 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 230000000295 complement effect Effects 0.000 claims abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
Definitions
- the present invention relates gate drivers, and more specifically to detecting and preventing spurious gate driver output turn ON due to N ⁇ epi P-sub diode conduction during N ⁇ EPI negative transient voltage. These negative transients can occur due to one parasitic inductive and current transients.
- a high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device.
- the high-side driver including first and second complementary switched MOSFET series connected at a high-side node, driving the high-side power switching device, one of the MOSFETs having a parasitic bipolar transistor formed between the substrate, an N+ epitaxial region connected to the high-side driver supply voltage and the switched node, with the parasitic transistor having a base electrode formed by the N+ epitaxial region, an emitter electrode formed by the substrate and a collector electrode formed by the switched node, such that if a transient voltage that is negative with respect to the substrate is present at the high-side driver supply voltage, the parasitic transistor will conduct a short circuit current between the switched node and the substrate; a first circuit for controlling the conduction of the first and second MOSFETs to switch the high-side switching device ON and OFF; a diffusion in the
- FIG. 1A is a circuit diagram of the connection between a driver circuit and a half-bridge switching stage that it controls;
- FIG. 1B is a diagram of the driver circuit of FIG. 1A ;
- FIG. 2A is a diagram of a high voltage NMOS driver used in the circuit of FIG. 1A showing the parasitic transistors;
- FIG. 2B is a graph showing negative transient at pin VB, the negative transient at the switching mode VS, and a counter start reset original time;
- FIG. 3A is a diagram of a portion of the high voltage NMOS driver of FIG. 2A including a P diffusion forming a P-Zener ring added according to the invention
- FIG. 3B is a diagram of the parasitic PNP transistor including the P-Zener ring and a resistance
- FIG. 3C is a graph showing the voltages at pin VB, pin VS and at the P-Zener ring V P-Zener ;
- FIG. 4 is a diagram of the VS sensing and reset circuit
- FIGS. 5A and 5B are graphs showing voltage VCE, short circuit current I SC , and voltage at pin VS for two different die sizes of the high driver IC.
- Driver circuits for example, for driving half-bridge circuits that include two power switching devices series connected at a switched node, may include a high side driver that is connected to a higher voltage supply than a low side driver.
- a level shift circuit is used to level shift high side drive input signals to the driver circuit to drive the high side driver, which is referenced to a floating voltage level VS. This voltage level VS is present at the switched node located at the connection of the power switching devices of the half-bridge.
- FIGS. 1A and 1B show an example of such driver circuit 5 .
- FIG. 1A illustrates power switching devices, e.g., MOSFETs, Q 1 and Q 2 series connected at a switched node to form a half-bridge. The node between the power switching devices is the switched node VS. As shown, a load is connected to the switched node VS. In the circuit shown, power switching devices Q 1 and Q 2 are alternately switched ON and OFF. When power switching device Q 1 is turned ON, a current flowing through the switched node VS is sourced to the load. When power switching device Q 1 is turned OFF, power switching device Q 2 is turned ON and sinks the load circuit, e.g., inductive motor current if the load is a motor. There is a dead time between the ON times provided by dead time circuits, not shown.
- power switching devices e.g., MOSFETs
- Q 1 and Q 2 series connected at a switched node to form a half-bridge.
- the high side driver, indicated at 10 may comprise two complementary switched switching devices N 1 and N 2 , for example, MOSFETs.
- the low side driver, indicated at 20 may comprise two complementary switched switching devices N 3 and N 4 , e.g., MOSFETs.
- the high side drive input signals at pin HIN to the driver circuit 5 are provided to a level shifting circuit 30 as pulses from a pulse generator 40 .
- the level shifting circuit 30 includes transistors N 5 and N 6 , whose drains are connected to a pulse filter 50 .
- the pulse filter 50 controls the operation of a latch 60 .
- the high side driver 10 switching devices N 1 and N 2 provide an output on pin HO.
- a high signal at pin HO provides output to drive or turn the high side switching device Q 1 ON.
- pin HO goes low.
- a low signal at pin HO turns the high side switching device Q 1 OFF.
- the high side driver 10 is referenced to the floating voltage at pin VS, which is equal to the voltage at the switched node VS, it is necessary to provide an increased supply voltage to the high side driver 10 as well as to the level shifting circuit 30 .
- This voltage is derived as a bootstrap voltage at pin VB from a bootstrap capacitor CBS.
- capacitor CBS charges from a voltage source VCC through a bootstrap diode DBS. Accordingly, a voltage VCC appears across the capacitor CBS.
- FIG. 2A shows a portion of the high voltage NMOS driver 10 .
- the driver 10 includes a HV NMOS device N 2 .
- the source(s), gate (G) and drain (D) of this device are shown.
- a parasitic PNP transistor 100 is formed between VS, the epitaxial region N+ epi and the P-substrate.
- Another parasitic transistor, a NPN transistor 102 is also formed as shown.
- the PNP transistor 100 is present between pin VS and the substrate forming the base of the transistor.
- Pin VB is connected to the N+ epitaxial layer forming the base of this transistor and the P-substrate is the emitter of this transmitter.
- the collector of the transistor is connected typically to pin VS.
- the N+ epi supply voltage i.e., the voltage at pin VB
- the voltage at pin VB can go negative due to wire parasitic inductance and current transients. As shown in FIG. 2B , this will cause voltage at the switching node VS to go even more negative.
- a P diffusion 101 in order to sense the negative N ⁇ epitaxial voltage at pin VB, a P diffusion 101 , illustrated in FIGS. 2A and 3A , is added. Any P type diffusion shape or dimension working as described can be used.
- a Zener ring 101 of P material provides an additional collector for the parasitic bipolar transistor 100 .
- a resistance R is provided between pin VS and the Zener ring.
- FIG. 3B shows the parasitic PNP transistor 100 including the collector provided by the Zener ring 101 and the resistance R between pin VS and the Zener ring.
- the transistor 100 turns on when voltage at pin VB is low.
- the voltages at pin VB, pin VS, and at the P-diffusion during negative voltage at pin VB is shown in the graph of FIG. 3C .
- the resistor R is used to sense the negative voltage between VS and the Zener ring 101 .
- FIG. 4 illustrates a circuit that performs sensing of the negative voltage VB and provides an active reset.
- the parasitic PNP transistor 100 has its emitter at the P-substrate, its base at pin VB (N+ Epi), and its collector at the added P-Zener ring.
- a resistance R of, for example 10K Ohms, is connected between the Zener ring and VS for sensing when the voltage at pin VB goes too low. When this occurs, a voltage is developed across the resistor R and, an additional reset is provided to the high side flip flop 60 ( FIG. 1B ) to keep it in a reset condition during the negative voltage condition at pin VB. As shown in FIG.
- a blanking circuit 110 is provided to prevent turning on a transistor 120 for the blanking time duration.
- a reset counter 130 is set, which provides a reset pulse of, for example 3 microseconds, during and over the negative voltage duration to clear the flip flop 60 (FF Clr) and ensure that the high side switching device Q 1 is turned off by keeping the driver circuit off (HO turn off). This prevents any spurious set signal at the latch 60 .
- Other parameter values for the resistance R, the blanking time, and the reset pulse can be chosen as necessary. Also, any passive or active device working as a collector current detector for the bipolar transistor 100 can be used in place of the resistor R.
- FIGS. 5A and 5B show the short circuit current for two different die sizes that can occur during negative VB, VS transients, leading to potential damage, what the invention prevents.
- FIG. 5A shows voltages VCE and at pin VS and short circuit current I SC for a die size 3.0
- FIG. 5B shows voltages VCE and at pin VS and short circuit current I SC for a die size 4.0.
- the short circuit currents are 140 and 320 A, respectively.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Power Conversion In General (AREA)
Abstract
Description
Claims (6)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/146,736 US7671638B2 (en) | 2007-06-28 | 2008-06-26 | Negative N-epi biasing sensing and high side gate driver output spurious turn-on prevention due to N-epi P-sub diode conduction during N-epi negative transient voltage |
PCT/US2008/007981 WO2009005697A1 (en) | 2007-06-28 | 2008-06-27 | Negative n-epi biasing sensing and high side gate driver output spurious turn-on prevention due to n-epi p-sub diode conduction during n-epi negative transient voltage |
TW097124528A TW200921318A (en) | 2007-06-28 | 2008-06-30 | Negative N-epi biasing sensing and high side gate driver output spurious turn-on prevention due to N-epi P-sub diode conduction during N-epi negative transient voltage |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US94680507P | 2007-06-28 | 2007-06-28 | |
US12/146,736 US7671638B2 (en) | 2007-06-28 | 2008-06-26 | Negative N-epi biasing sensing and high side gate driver output spurious turn-on prevention due to N-epi P-sub diode conduction during N-epi negative transient voltage |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090002060A1 US20090002060A1 (en) | 2009-01-01 |
US7671638B2 true US7671638B2 (en) | 2010-03-02 |
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ID=40159663
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/146,736 Active 2028-08-19 US7671638B2 (en) | 2007-06-28 | 2008-06-26 | Negative N-epi biasing sensing and high side gate driver output spurious turn-on prevention due to N-epi P-sub diode conduction during N-epi negative transient voltage |
Country Status (3)
Country | Link |
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US (1) | US7671638B2 (en) |
TW (1) | TW200921318A (en) |
WO (1) | WO2009005697A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8564363B1 (en) * | 2012-07-11 | 2013-10-22 | Alitek Technology Corp. | Pulse filter and bridge driver using the same |
US9374006B2 (en) * | 2014-10-24 | 2016-06-21 | Edgar Abdoulin | Three-channel high-side gate driver having startup circuit and configurable outputs |
Families Citing this family (7)
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US7672106B1 (en) * | 2008-01-22 | 2010-03-02 | Sullivan James D | Switching incandescent lamps and other variable resistance loads with a solid state, smart, high side driver having overcurrent and temperature sensing protection circuits |
JP5488256B2 (en) * | 2010-06-25 | 2014-05-14 | 三菱電機株式会社 | Power semiconductor device |
JP6117640B2 (en) * | 2013-07-19 | 2017-04-19 | ルネサスエレクトロニクス株式会社 | Semiconductor device and drive system |
ITUA20162322A1 (en) * | 2016-04-05 | 2017-10-05 | St Microelectronics Srl | PROCEDURE FOR PILOTING SWITCHING, CIRCUIT AND CORRESPONDENT STAGES |
CN110212813A (en) * | 2018-12-12 | 2019-09-06 | 华帝股份有限公司 | Direct current motor drive circuit, motor assembly using same and range hood |
US10862483B2 (en) | 2019-01-25 | 2020-12-08 | Infineon Technologies Austria Ag | Low power cycle to cycle bit transfer in gate drivers |
JP7490449B2 (en) * | 2020-05-15 | 2024-05-27 | ローム株式会社 | Semiconductor integrated circuit, motor driver, and motor drive system |
Citations (5)
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US5502412A (en) * | 1995-05-04 | 1996-03-26 | International Rectifier Corporation | Method and circuit for driving power transistors in a half bridge configuration from control signals referenced to any potential between the line voltage and the line voltage return and integrated circuit incorporating the circuit |
US6198139B1 (en) | 1998-09-14 | 2001-03-06 | Mitsubishi Denki Kabushiki Kaisha | Complementary MOS device |
US20040212021A1 (en) * | 2003-04-24 | 2004-10-28 | Mitsubishi Denki Kabushiki Kaisha | High voltage integrated circuit |
US6870354B2 (en) | 2002-07-24 | 2005-03-22 | Seiko Epson Corporation | Power source circuit |
US7482655B2 (en) * | 2002-06-06 | 2009-01-27 | International Rectifier Corporation | MOSgate driver integrated circuit with adaptive dead time |
-
2008
- 2008-06-26 US US12/146,736 patent/US7671638B2/en active Active
- 2008-06-27 WO PCT/US2008/007981 patent/WO2009005697A1/en active Application Filing
- 2008-06-30 TW TW097124528A patent/TW200921318A/en unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5502412A (en) * | 1995-05-04 | 1996-03-26 | International Rectifier Corporation | Method and circuit for driving power transistors in a half bridge configuration from control signals referenced to any potential between the line voltage and the line voltage return and integrated circuit incorporating the circuit |
US6198139B1 (en) | 1998-09-14 | 2001-03-06 | Mitsubishi Denki Kabushiki Kaisha | Complementary MOS device |
US7482655B2 (en) * | 2002-06-06 | 2009-01-27 | International Rectifier Corporation | MOSgate driver integrated circuit with adaptive dead time |
US6870354B2 (en) | 2002-07-24 | 2005-03-22 | Seiko Epson Corporation | Power source circuit |
US20040212021A1 (en) * | 2003-04-24 | 2004-10-28 | Mitsubishi Denki Kabushiki Kaisha | High voltage integrated circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8564363B1 (en) * | 2012-07-11 | 2013-10-22 | Alitek Technology Corp. | Pulse filter and bridge driver using the same |
US9374006B2 (en) * | 2014-10-24 | 2016-06-21 | Edgar Abdoulin | Three-channel high-side gate driver having startup circuit and configurable outputs |
Also Published As
Publication number | Publication date |
---|---|
US20090002060A1 (en) | 2009-01-01 |
WO2009005697A1 (en) | 2009-01-08 |
TW200921318A (en) | 2009-05-16 |
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