US7529078B2 - Low tunneling current MIM structure and method of manufacturing same - Google Patents

Low tunneling current MIM structure and method of manufacturing same Download PDF

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US7529078B2
US7529078B2 US11/379,478 US37947806A US7529078B2 US 7529078 B2 US7529078 B2 US 7529078B2 US 37947806 A US37947806 A US 37947806A US 7529078 B2 US7529078 B2 US 7529078B2
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metal
dielectric layer
electrode
magnetic moment
forming
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Yu-Jen Wang
Hsing-Lien Lin
Yeur-Luen Tu
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/10—Metal-oxide dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Disclosed embodiments herein relate generally to metal-insulator-metal (MIM) structures, and more particularly to new MIM structures having increased capacitance with little or no tunneling current, and related methods of manufacturing the same.
  • MIM metal-insulator-metal
  • Capacitors in electrical integrated circuits are typically incorporated between the interconnect layers of a semiconductor wafer in order to maximize the use of the space between the interconnect layers.
  • the capacitors formed between the interconnect layers are preferably of a metal-insulator-metal (MIM) construction, as the conductors of the interconnect layers are metal in construction.
  • MIM capacitors may be used to store a charge in a variety of semiconductor devices, that may be utilized in the IC.
  • MIM structures are one of the key devices in radio-frequency (RF). mixed-signal integrated circuit, and DRAM application.
  • MIM structures consume a relatively large percentage of the surface area of a semiconductor wafer or chip because they are typically constructed as a large flat structure formed by a low dielectric constant (k) silicon dioxide or nitride capacitor dielectric layer sandwiched between upper and lower metal electrodes, positioned parallel to the wafer surface.
  • k dielectric constant
  • capacitance is generally a function of electrode area.
  • the prior art has attempted a few different approaches.
  • An even more advantageous approach for gaining capacitance (per device size) would be to shrink the dielectric thickness and employ a high-k material simultaneously.
  • high-k materials are often incompatible with the idea of decreasing dielectric thickness due to the issue of leakage current. More specifically, as high-k dielectrics are made thinner, the propensity of leakage or “tunneling” current from electrode to electrode across the dielectric increases. Accordingly, an MIM capacitor structure is needed that utilizes wafer area more efficiently than conventional MIM capacitor structures, while using high-k dielectrics without the detrimental effects of leakage current.
  • an MIM structure constructed according to the disclosed principles allows the thickness of that layer to be extremely thin without the high risk of tunneling/leakage current that is typically present with such thin dielectrics.
  • Such a thin dielectric layer in an MIM stack provides a high capacitance, despite its extremely thin size.
  • an MIM structure comprises a first electrode comprising a magnetic metal and having a magnetic moment aligned in a first direction, and a second electrode comprising a magnetic metal and having a magnetic moment aligned in a second direction antiparallel to the first direction.
  • such an MIM structure comprises a dielectric layer formed between the first and second electrodes and contacting the first and second magnetic metals.
  • a method of manufacturing an MIM structure comprises forming a bottom electrode from a magnetic metal, growing a dielectric layer on the bottom electrode, and then forming a second electrode from a magnetic metal on the dielectric layer. Such a method further provides annealing the top and bottom electrodes to align a magnetic moment of the top electrode in a first direction and a magnetic moment of the bottom electrode in a second direction antiparallel to the first direction.
  • FIG. 1 illustrates one embodiment of a metal-insulator-metal (MIM) structure constructed according to the principles disclosed herein;
  • MIM metal-insulator-metal
  • FIG. 1A illustrates the spin directions of the electrodes shown in the MIM structure of FIG. 1 ;
  • FIG. 2 illustrates a graph that shows the relationship between magnetic alignment and resistance
  • FIG. 3 illustrates a more detailed view of one embodiment of the MIM structure illustrated in FIG. 1 ;
  • FIG. 4 illustrates another embodiment of an MIM structure constructed according to the disclosed principles, but employing two annealing steps during the manufacturing process.
  • the disclosed MIM structure 100 includes a top electrode 110 and a bottom electrode 120 , with a high-k dielectric layer 130 interposed between the top and bottom electrodes 110 , 120 .
  • the term “high-k dielectric” means a dielectric material having a dielectric constant of at least 9. Examples of high-k dielectric materials suitable for use with the disclosed principles are Al 2 O 3 , SiO 2 , Ta 2 O 5 , MgO and HfO, but no limitation to any particular material is intended.
  • the MIM structure 100 in FIG. 1 may appear to be similar to a conventional MIM structure because of the two electrodes surrounding a dielectric layer, this MIM structure 100 is distinct from known structures because of the antiparallel alignment provided between the top and bottom electrodes 110 , 120 . Specifically, the magnetic moments of the top and bottom electrodes 110 , 120 are aligned antiparallel to each other when the MIM stack 100 is constructed.
  • one of the primary concerns with the use of thin high-k dielectric layers in MIM structures is the tunneling current that usually occurs across that dielectric layer.
  • the tunneling current is typically spin-dependent tunneling in such conventional MIM structures.
  • the disclosed principles provide for an MIM structure 100 where the spin directions of the electrodes 110 , 120 are antiparallel to each other, as shown in FIG. 1A .
  • the spin directions of the electrodes 110 , 120 are antiparallel (i.e., alignment of magnetic moments is antiparallel)
  • no tunneling (or leakage) current passes across the high-k dielectric layer 130 . This principles is set forth below in equation (2).
  • parallel magnetizations are defined in equation (3)
  • antiparallel magnetizations are defined in equation (4).
  • P L and P R are the spin polarizations of left and right ferromagnets (e.g., ferromagnetic metals), and are defined respectively in equations (5) and (6) below.
  • FIG. 2 a graph is shown that illustrates the relationship between magnetic alignment and resistance. Specifically, the electrical resistance through a dielectric layer surrounded by magnetic electrodes as the magnetic moments of the surrounding electrodes become larger. Conversely, the resistance decreases as they become more parallel. Referring back to FIG. 1 , in an MIM stack, the electrical resistance of the dielectric layer 130 can therefore be controlled by aligning the magnetic moments of the surrounding electrodes 110 , 120 . As discussed in further detail below, the composition of electrodes 110 , 120 can determine the technique used to provide the desired antiparallel alignment.
  • an MIM structure By preventing or drastically reducing leakage current across the dielectric layer 130 , an MIM structure according to the disclosed principles allows the thickness of that dielectric layer to be extremely thin without the high risk of tunneling that is typically present with such thin dielectrics.
  • the thickness of the dielectric layer 130 may be reduced to only a few Angstroms.
  • a structure 100 according to the disclosed principles may allow the dielectric layer 130 to be formed with an equivalent of oxide thickness (EOT) of only about 3 Angstroms.
  • EOT oxide thickness
  • FIG. 3 illustrates a more detailed view of one embodiment of the MIM structure 100 illustrated in FIG. 1 .
  • FIG. 3 provides more detail on the construction of the top and bottom electrodes 110 , 120 of the structure 100 , in order to illustrate how the magnetic moments of these electrodes 110 , 120 can be aligned antiparallel to each other, in accordance with the disclosed principles.
  • a key principle of the disclosed structure is the antiparallel alignment of the magnetic moments of the portions of the top and bottom electrodes 110 c and 120 a that are adjacent to the dielectric material.
  • the first electrode 110 may be comprised of two magnetic metals 110 a , 110 c surrounding a non-magnetic metal spacer 110 b .
  • the magnetic moments of the layers comprising the electrodes 110 , 120 are aligned antiparallel to each other using a single annealing process.
  • this embodiment provides the beneficial dielectric properties discussed above without the use of antiferromagnetic materials in the structure. More specifically, the upper and lower magnetic metals 110 a , 110 c , 120 a , 120 c for each electrode 110 , 120 (respectively) are separated by the illustrated spacers 110 b , 120 b , which introduces the Ruderman-Kittel-Kasuya-Yosida (“RKKY”) effect into the electrodes 110 , 120 .
  • RKKY Ruderman-Kittel-Kasuya-Yosida
  • a single annealing process may then be performed during manufacture of the stack 100 to set the antiparallel configuration of magnetization between the top and bottom electrodes 110 , 120 .
  • layered ferromagnetic structures such as the illustrated electrodes 110 , 120 utilize the RKKY effect, and thus are very sensitive to the thickness of the non-magnetic film, this is not a disadvantage in the disclosed structure since a primary purpose of the disclosed principles is decreasing layer thickness within the stack 100 . Thus, sensitivity to layer thickness due to the RKKY effect is actually used as an advantage by the disclosed technique.
  • FIG. 4 illustrates another embodiment of an MIM structure 200 constructed according to the disclosed principles.
  • This structure 200 still includes top and bottom electrodes 210 , 220 , surrounding a high-k dielectric layer 230 .
  • each of the electrodes 210 , 220 are comprised of a magnetic metal 210 a , 220 a adjacent to the high-k dielectric layer 230 .
  • On the other sides of the magnetic metals 210 a , 220 a are antiferromagnetic materials 210 b , 220 b .
  • These antiferromagnetic materials 210 b , 220 b may be comprised of FeMn, PtMn, NiMn, and alloys thereof, or any other similar material.
  • a first annealing process is performed at a relatively high temperature (T).
  • T relatively high temperature
  • the first anneal is performed at about the high Tb (“blocking temperature”).
  • the first magnetic metal 210 a has its magnetic moment polarized in a specific direction.
  • a second annealing process is performed at a relatively lower temperature (T).
  • the second anneal may be performed at about the low Tb.
  • the blocking temperature is used to set the exchange biasing direction above a specific temperature.
  • the MIM film structure may be employed to decrease the leakage current of a dielectric layer having an ultra-thin thickness for increasing the capacitance of the MIM structure (per its size and thickness). In most cases, the thickness of the dielectric layer may be reduced to only a few Angstroms.
  • the disclosed technique involves an antiparallel aligning of the direction of magnetization of the ferromagnetic materials formed adjacent to the dielectric layer. Also, the tunneling current could be fully suppressed by using half metal. (100% polarization). To accomplish such antiparallel alignment on opposing sides of the dielectric layer, only one extra processing step, an annealing process, is provided to a conventional MIM structure manufacturing process.
  • two annealing processes may also be employed to accomplish the antiparallel alignment.
  • the disclosed principles may be employed to arrive at an MIM structure that may be used in almost any application, including RF, mixed-mode, or DRAM applications.

Abstract

Disclosed herein are new MIM structures having increased capacitance with little or no tunneling current, and related methods of manufacturing the same. In one embodiment, the new MIM structure comprises a first electrode comprising a magnetic metal and having a magnetic moment aligned in a first direction, and a second electrode comprising a magnetic metal and having a magnetic moment aligned in a second direction antiparallel to the first direction. In addition, such an MIM structure comprises a dielectric layer formed between the first and second electrodes and contacting the first and second magnetic metals.

Description

TECHNICAL FIELD
Disclosed embodiments herein relate generally to metal-insulator-metal (MIM) structures, and more particularly to new MIM structures having increased capacitance with little or no tunneling current, and related methods of manufacturing the same.
BACKGROUND
Capacitors in electrical integrated circuits (ICs) are typically incorporated between the interconnect layers of a semiconductor wafer in order to maximize the use of the space between the interconnect layers. The capacitors formed between the interconnect layers are preferably of a metal-insulator-metal (MIM) construction, as the conductors of the interconnect layers are metal in construction. MIM capacitors may be used to store a charge in a variety of semiconductor devices, that may be utilized in the IC. For example, such MIM structures are one of the key devices in radio-frequency (RF). mixed-signal integrated circuit, and DRAM application.
Conventional MIM structures consume a relatively large percentage of the surface area of a semiconductor wafer or chip because they are typically constructed as a large flat structure formed by a low dielectric constant (k) silicon dioxide or nitride capacitor dielectric layer sandwiched between upper and lower metal electrodes, positioned parallel to the wafer surface. There is an ongoing challenge to maintain sufficiently high storage capacitance despite decreasing capacitor area, since capacitance is generally a function of electrode area. In order to reduce the area of these structures, yet obtain higher capacitance density per unit size, the prior art has attempted a few different approaches.
One approach has been to replace the low-k material used for the dielectric layer with high-k materials, such as Al2O3, HfO, and Ta2O5, having a k value higher than 9. However, such high-k materials do not adhere well to the metal electrodes, which are still relatively large, thereby leading to delaminations in the MIM structures. Another conventional approach of increasing capacitance has been is to reduce dielectric thickness. Capacitance is set forth in equation (1),
C = k * A t ( 1 )
where C=capacitance, k=dielectric constant, A=electrode area, and t=dielectric thickness).
An even more advantageous approach for gaining capacitance (per device size) would be to shrink the dielectric thickness and employ a high-k material simultaneously. Unfortunately, high-k materials are often incompatible with the idea of decreasing dielectric thickness due to the issue of leakage current. More specifically, as high-k dielectrics are made thinner, the propensity of leakage or “tunneling” current from electrode to electrode across the dielectric increases. Accordingly, an MIM capacitor structure is needed that utilizes wafer area more efficiently than conventional MIM capacitor structures, while using high-k dielectrics without the detrimental effects of leakage current.
SUMMARY
Disclosed herein are new MIM structures having increased capacitance with little or no tunneling current, and related methods of manufacturing the same. By preventing or drastically reducing leakage current across the dielectric insulator layer, an MIM structure constructed according to the disclosed principles allows the thickness of that layer to be extremely thin without the high risk of tunneling/leakage current that is typically present with such thin dielectrics. Such a thin dielectric layer in an MIM stack provides a high capacitance, despite its extremely thin size.
In one aspect, an MIM structure is provided. In one embodiment, the MIM structure comprises a first electrode comprising a magnetic metal and having a magnetic moment aligned in a first direction, and a second electrode comprising a magnetic metal and having a magnetic moment aligned in a second direction antiparallel to the first direction. In addition, such an MIM structure comprises a dielectric layer formed between the first and second electrodes and contacting the first and second magnetic metals.
In another aspect, a method of manufacturing an MIM structure is provided. In one embodiment, the method comprises forming a bottom electrode from a magnetic metal, growing a dielectric layer on the bottom electrode, and then forming a second electrode from a magnetic metal on the dielectric layer. Such a method further provides annealing the top and bottom electrodes to align a magnetic moment of the top electrode in a first direction and a magnetic moment of the bottom electrode in a second direction antiparallel to the first direction.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the principles disclosure herein, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates one embodiment of a metal-insulator-metal (MIM) structure constructed according to the principles disclosed herein;
FIG. 1A illustrates the spin directions of the electrodes shown in the MIM structure of FIG. 1;
FIG. 2 illustrates a graph that shows the relationship between magnetic alignment and resistance;
FIG. 3 illustrates a more detailed view of one embodiment of the MIM structure illustrated in FIG. 1; and
FIG. 4 illustrates another embodiment of an MIM structure constructed according to the disclosed principles, but employing two annealing steps during the manufacturing process.
 DETAILED DESCRIPTION
Referring initially to FIG. 1, illustrated is one embodiment of a metal-insulator-metal (MIM) structure 100 constructed according to the principles disclosed herein. Specifically, the disclosed MIM structure 100 includes a top electrode 110 and a bottom electrode 120, with a high-k dielectric layer 130 interposed between the top and bottom electrodes 110, 120. As used herein, the term “high-k dielectric” means a dielectric material having a dielectric constant of at least 9. Examples of high-k dielectric materials suitable for use with the disclosed principles are Al2O3, SiO2, Ta2O5, MgO and HfO, but no limitation to any particular material is intended.
While the MIM structure 100 in FIG. 1 may appear to be similar to a conventional MIM structure because of the two electrodes surrounding a dielectric layer, this MIM structure 100 is distinct from known structures because of the antiparallel alignment provided between the top and bottom electrodes 110, 120. Specifically, the magnetic moments of the top and bottom electrodes 110, 120 are aligned antiparallel to each other when the MIM stack 100 is constructed. As discussed above, one of the primary concerns with the use of thin high-k dielectric layers in MIM structures is the tunneling current that usually occurs across that dielectric layer. Moreover, when ferromagnetic electrodes are employed, the tunneling current is typically spin-dependent tunneling in such conventional MIM structures.
However, the disclosed principles provide for an MIM structure 100 where the spin directions of the electrodes 110, 120 are antiparallel to each other, as shown in FIG. 1A. When the spin directions of the electrodes 110, 120 are antiparallel (i.e., alignment of magnetic moments is antiparallel), no tunneling (or leakage) current passes across the high-k dielectric layer 130. This principles is set forth below in equation (2).
TMR = I ↑ ↑ - I ↑ ↓ I ↑ ↓ = 2 ⁢ P L ⁢ P R 1 - P L ⁢ P R ( 2 )
In equation (2), parallel magnetizations are defined in equation (3), while antiparallel magnetizations are defined in equation (4).
I↑↑∝nL ↑nR ↑+nL ↓nR ↓  (3)
I↑↓∝nL ↑nR ↓+nL ↓nR ↑  (4)
Also in equation (2), PL and PR are the spin polarizations of left and right ferromagnets (e.g., ferromagnetic metals), and are defined respectively in equations (5) and (6) below.
P L = n L ↑ - n L ↓ n L ↑ + n L ↓ ( 5 ) P R = n R ↑ - n R ↓ n R ↑ + n R ↓ ( 6 )
Turning briefly to FIG. 2, a graph is shown that illustrates the relationship between magnetic alignment and resistance. Specifically, the electrical resistance through a dielectric layer surrounded by magnetic electrodes as the magnetic moments of the surrounding electrodes become larger. Conversely, the resistance decreases as they become more parallel. Referring back to FIG. 1, in an MIM stack, the electrical resistance of the dielectric layer 130 can therefore be controlled by aligning the magnetic moments of the surrounding electrodes 110, 120. As discussed in further detail below, the composition of electrodes 110, 120 can determine the technique used to provide the desired antiparallel alignment.
By preventing or drastically reducing leakage current across the dielectric layer 130, an MIM structure according to the disclosed principles allows the thickness of that dielectric layer to be extremely thin without the high risk of tunneling that is typically present with such thin dielectrics. In many embodiments, the thickness of the dielectric layer 130 may be reduced to only a few Angstroms. For example, if Al2O3 is employed as the dielectric layer 130, a structure 100 according to the disclosed principles may allow the dielectric layer 130 to be formed with an equivalent of oxide thickness (EOT) of only about 3 Angstroms. Of course, as discussed above, such a thin dielectric layer in an MIM stack constructed in accordance with the disclosed principles will provide a high capacitance, despite its extremely thin size.
FIG. 3 illustrates a more detailed view of one embodiment of the MIM structure 100 illustrated in FIG. 1. Specifically, FIG. 3 provides more detail on the construction of the top and bottom electrodes 110, 120 of the structure 100, in order to illustrate how the magnetic moments of these electrodes 110, 120 can be aligned antiparallel to each other, in accordance with the disclosed principles. Specifically, a key principle of the disclosed structure is the antiparallel alignment of the magnetic moments of the portions of the top and bottom electrodes 110 c and 120 a that are adjacent to the dielectric material. In exemplary embodiments of the disclosed structure 100, the first electrode 110 may be comprised of two magnetic metals 110 a, 110 c surrounding a non-magnetic metal spacer 110 b. Likewise, the second electrode 120 may also be comprised of two magnetic metals 120 a, 120 c surrounding a non-magnetic metal spacer 120 b. For either electrode 110, 120, the metal spacers 110 b, 120 b may comprise copper, chromium, ruthenium, or other beneficial metal. The upper and lower magnetic metals 110 a, 110 c, 120 a, 120 c for each electrode 110, 120 may comprise Fe, Co, Ni, B and alloys thereof.
In this embodiment of the MIM structure 100, the magnetic moments of the layers comprising the electrodes 110, 120 are aligned antiparallel to each other using a single annealing process. In addition, this embodiment provides the beneficial dielectric properties discussed above without the use of antiferromagnetic materials in the structure. More specifically, the upper and lower magnetic metals 110 a, 110 c, 120 a, 120 c for each electrode 110, 120 (respectively) are separated by the illustrated spacers 110 b, 120 b, which introduces the Ruderman-Kittel-Kasuya-Yosida (“RKKY”) effect into the electrodes 110, 120. A single annealing process may then be performed during manufacture of the stack 100 to set the antiparallel configuration of magnetization between the top and bottom electrodes 110, 120. Although layered ferromagnetic structures such as the illustrated electrodes 110, 120 utilize the RKKY effect, and thus are very sensitive to the thickness of the non-magnetic film, this is not a disadvantage in the disclosed structure since a primary purpose of the disclosed principles is decreasing layer thickness within the stack 100. Thus, sensitivity to layer thickness due to the RKKY effect is actually used as an advantage by the disclosed technique.
FIG. 4 illustrates another embodiment of an MIM structure 200 constructed according to the disclosed principles. This structure 200 still includes top and bottom electrodes 210, 220, surrounding a high-k dielectric layer 230. However, instead of the electrodes 210, 220 being constructed of two magnetic metals surrounding a metal spacer (as in the embodiment of FIG. 3), each of the electrodes 210, 220 are comprised of a magnetic metal 210 a, 220 a adjacent to the high-k dielectric layer 230. On the other sides of the magnetic metals 210 a, 220 a are antiferromagnetic materials 210 b, 220 b. These antiferromagnetic materials 210 b, 220 b may be comprised of FeMn, PtMn, NiMn, and alloys thereof, or any other similar material.
During the manufacturing process for the MIM structure 200 of FIG. 4, a first annealing process is performed at a relatively high temperature (T). For example, in exemplary embodiments, the first anneal is performed at about the high Tb (“blocking temperature”). As shown, the first magnetic metal 210 a has its magnetic moment polarized in a specific direction. Then, later in the manufacturing process, a second annealing process is performed at a relatively lower temperature (T). In exemplary embodiments, the second anneal may be performed at about the low Tb. In accordance with the disclosed principles, the blocking temperature is used to set the exchange biasing direction above a specific temperature. By applying two kinds of antiferromagents in the disclosed structure, when the second annealing process is performed, the exchange biasing direction of the high Tb antiferromagnet will not be affected since the annealing temperature of second annealing process would be lower. The second magnetic metal 220 a has its magnetic moment polarized in a specific direction that is substantially antiparallel to the polarization of the magnetic metal 210 a in the top electrode 210. Of course, the manufacturing process may include greater or fewer steps than these two annealing processes, without departing from the broad scope of the disclosed principles.
As disclosed above, the MIM film structure, and methods for producing the same, may be employed to decrease the leakage current of a dielectric layer having an ultra-thin thickness for increasing the capacitance of the MIM structure (per its size and thickness). In most cases, the thickness of the dielectric layer may be reduced to only a few Angstroms. The disclosed technique involves an antiparallel aligning of the direction of magnetization of the ferromagnetic materials formed adjacent to the dielectric layer. Also, the tunneling current could be fully suppressed by using half metal. (100% polarization). To accomplish such antiparallel alignment on opposing sides of the dielectric layer, only one extra processing step, an annealing process, is provided to a conventional MIM structure manufacturing process. In other embodiments, depending on the desired structure of the new MIM stack, two annealing processes may also be employed to accomplish the antiparallel alignment. Moreover, the disclosed principles may be employed to arrive at an MIM structure that may be used in almost any application, including RF, mixed-mode, or DRAM applications.
While various embodiments of the disclosed principles have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the invention(s) should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with any claims and their equivalents issuing from this disclosure. Furthermore, the above advantages and features are provided in described embodiments, but shall not limit the application of such issued claims to processes and structures accomplishing any or all of the above advantages.
Additionally, the section headings herein are provided for consistency with the suggestions under 37 CFR 1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the invention(s) set out in any claims that may issue from this disclosure. Specifically and by way of example, although the headings refer to a “Technical Field,” such claims should not be limited by the language chosen under this heading to describe the so-called technical field. Further, a description of a technology in the “Background” is not to be construed as an admission that technology is prior art to any invention(s) in this disclosure. Neither is the “Brief Summary” to be considered as a characterization of the invention(s) set forth in issued claims. Furthermore, any reference in this disclosure to “invention” in the singular should not be used to argue that there is only a single point of novelty in this disclosure. Multiple inventions may be set forth according to the limitations of the multiple claims issuing from this disclosure, and such claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of such claims shall be considered on their own merits in light of this disclosure, but should not be constrained by the headings set forth herein.

Claims (20)

1. A metal-insulator-metal (MIM) structure, comprising:
a first electrode comprising a magnetized metal and having a permanent magnetic moment aligned in a first direction;
a second electrode comprising a magnetized metal and having a permanent magnetic moment aligned in a second direction antiparallel to the first direction; and
a dielectric layer formed between the first and second electrodes and contacting the first and second magnetized metals.
2. An MIM structure according to claim 1, wherein the magnetized metal is selected from the consisting of at least one of Ni, Fe, Co, B and alloys thereof.
3. An MIM structure according to claim 1, wherein the magnetized metal of the first and second electrodes comprises a first magnetized metal and a second magnetized metal separated by a magnetized metal spacer, the first magnetized metal contacting the dielectric layer and having a permanent magnetic moment aligned in one of the first or second directions, and the second magnetized metal having a permanent magnetic moment aligned in the other of the first or second directions.
4. An MIM structure according to claim 3, wherein the metal spacer comprises at least one selected from the group consisting of ruthenium, chromium, and copper.
5. An MIM structure according to claim 1, wherein the first and second electrodes each further comprise an antiferromagnetic material formed on the magnetized metal.
6. An MIM structure according to claim 5, wherein the antiferromagnetic material comprises at least one selected from the group consisting of PtMn, NiMn and IrMn.
7. An MIM structure according to claim 5, wherein the antiferromagnetic material of the first electrode comprises a high Tb and the antiferromagnetic material of the second electrode comprises a low Tb.
8. An MIM structure according to claim 1, wherein the dielectric layer comprises a high-k dielectric material having a dielectric constant of at least 9.
9. An MIM structure according to claim 8, wherein the high-k dielectric material is selected from the consisting of Al2O3, SiO2, Ta2O5, MgO, ZrO and HfO.
10. An MIM structure according to claim 8, wherein the dielectric layer comprises a thickness of about 3 Angstroms.
11. A method of manufacturing a metal-insulator-metal (MIM) structure, the method comprising:
forming a bottom electrode from a magnetized metal;
growing a dielectric layer on the bottom electrode;
forming a second electrode from a magnetized metal on the dielectric layer;
annealing the top and bottom electrodes to align a permanent magnetic moment of the top electrode in a first direction and a permanent magnetic moment of the bottom electrode in a second direction antiparallel to the first direction.
12. A method according to claim 11, wherein forming the top and bottom electrodes comprises forming the top and bottom electrodes from a magnetized metal selected from the consisting of at least one of Ni, Fe, Co, B and alloys thereof.
13. A method according to claim 11, wherein forming the top and bottom electrodes comprises forming the top and bottom electrodes by:
forming a first magnetized metal,
forming a metal spacer on the first magnetized metal, and
forming a second magnetized metal on the metal spacer, wherein the first magnetized metal contacts the dielectric layer,
wherein the annealing further comprises annealing the top and bottom electrodes to align a permanent magnetic moment of the first magnetized metal of the top electrode in the first direction, to align a permanent magnetic moment of the first magnetized metal of the bottom electrode in the second direction, and to align a permanent magnetic moment of the second magnetized metal of the top electrode in the second direction, and to align a permanent magnetic moment of the first magnetized metal of the bottom electrode in the first direction.
14. A method according to claim 13, wherein forming a metal spacer comprises forming metal spacer comprising at least one selected from the group consisting of ruthenium, chromium, and copper.
15. A method according to claim 11, wherein forming the top and bottom electrodes further comprises forming an antiferromagnetic over the magnetized metal of top and bottom electrodes, and wherein the annealing further comprises performing a high temperature anneal to permanently align the magnetic moment of the top electrode in the first direction, and performing a low temperature anneal to permanently align the magnetic moment of the bottom electrode in the second direction.
16. A method according to claim 15, wherein performing a high temperature anneal to permanently align the magnetic moment of the top electrode in the first direction comprises performing an anneal at high Tb, and performing a low temperature anneal to permanently align the magnetic moment of the bottom electrode in the second direction comprises performing an anneal at low Tb.
17. A method according to claim 15, wherein forming an antiferromagnetic comprises forming an antiferromagnetic comprising at least one selected from the group consisting of PtMn, NiMn and IrMn.
18. A method according to claim 11, wherein growing a dielectric layer comprises growing a high-k dielectric layer having a dielectric constant of at least 9.
19. A method according to claim 18, wherein growing a dielectric layer comprises growing a high-k dielectric layer comprising a high-k dielectric material selected from the consisting of Al2O3, SiO2, Ta2O5, MgO, ZrO and HfO.
20. A method according to claim 18, wherein growing a dielectric layer comprises growing a high-k dielectric layer to a thickness of about 3 Angstroms.
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