US7317323B2 - Signal test procedure for testing semi-conductor components and a test apparatus for testing semi-conductor components - Google Patents
Signal test procedure for testing semi-conductor components and a test apparatus for testing semi-conductor components Download PDFInfo
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- US7317323B2 US7317323B2 US10/948,741 US94874104A US7317323B2 US 7317323 B2 US7317323 B2 US 7317323B2 US 94874104 A US94874104 A US 94874104A US 7317323 B2 US7317323 B2 US 7317323B2
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- 238000012360 testing method Methods 0.000 title claims abstract description 137
- 239000004065 semiconductor Substances 0.000 title claims abstract description 127
- 238000010998 test method Methods 0.000 title claims description 29
- 238000000034 method Methods 0.000 claims description 24
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000012956 testing procedure Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 21
- 238000005259 measurement Methods 0.000 description 19
- 230000015654 memory Effects 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000969 carrier Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229920000747 poly(lactic acid) Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31901—Analysis of tester Performance; Tester characterization
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
- G01R31/3191—Calibration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5002—Characteristic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
Definitions
- the invention relates to a signal test procedure, in particular to be used for testing semi-conductor components, and to a test apparatus for testing semi-conductor components.
- Semi-conductor components for instance corresponding integrated (analog and/or digital) computer circuits, semi-conductor memory components, for instance functional memory components (PLAs, PALs, etc.) and table memory components (e.g. ROMs or RAMs, in particular SRAMs and DRAMs) are subjected to extensive testing during the manufacturing process.
- PLAs functional memory components
- PALs PALs
- table memory components e.g. ROMs or RAMs, in particular SRAMs and DRAMs
- a so-called wafer i.e. a thin disk of monocrystalline silicon
- the wafer is appropriately treated (for instance subjected in succession to numerous coating, exposure, etching, diffusion and implantation process steps, etc.), and then for instance sliced up (or scored and snapped off), so that the individual components become available.
- semi-conductor components for instance DRAMs (Dynamic Random Access Memories and/or dynamic read-write memories), in particular of DDR-DRAMs (Double Data Rate-DRAMs and/or DRAMs with double data rate)
- semi-completed components still on the wafer
- DRAMs Dynamic Random Access Memories and/or dynamic read-write memories
- DDR-DRAMs Double Data Rate-DRAMs and/or DRAMs with double data rate
- the semi-conductor components are subjected to further test procedures at one or more (further) test stations. For instance, completed components—still present on the wafer—can be appropriately tested with the aid of corresponding (additional) test equipment (“slice tests”).
- carrier i.e. a suitable mounting
- one or more further tests can be performed, for instance after the semi-conductor components have been mounted onto the corresponding semi-conductor component housing, and/or for instance after the semi-conductor component housing (together with the semi-conductor components mounted onto it in each case) has been mounted (for so-called module tests) into a corresponding electronic module.
- This invention discloses a novel signal testing procedure, in particular one to be used for testing semi-conductor components, as well as a novel test apparatus for testing semi-conductor components.
- the procedure may advantageously include:
- FIG. 2 a shows the stations that are passed through during the manufacture of corresponding semi-conductor components, and of several further test apparatuses provided at each of the stations.
- FIG. 4 shows the resulting signal detected while performing the signal test procedure, at various voltage levels of the signal to be tested, and various voltage levels of the reference signal.
- FIG. 5 shows a video screen on which the results of the signal-test procedure can be visualized.
- FIGS. 2 a and 2 b some of the stations A, B, C, D, E, F, G (of several further stations not shown here) passed through by the corresponding semi-conductor components 103 a , 103 b , 103 c , 103 d during the manufacture of the semi-conductor components 103 a , 103 b , 103 c , 103 d (and/or electronic modules) are—schematically—shown.
- functional memory components i.e. PLAs, PALs, etc.
- table memory components for instance ROMs or RAMs
- an appropriate silicon disk or an appropriate wafer 102 is subjected to corresponding conventional coating, exposure, etching, diffusion, and/or implantation process steps, etc.—for instance at the corresponding stations placed in series upstream and downstream from the station A shown in FIG. 2 a (for instance, station B placed after station A—as well as numerous further stations—not shown here—(placed before and after station A)).
- Station A serves to subject the semi-conductor components 103 a , 103 b , 103 c , 103 d —still present on wafer 102 —to one or more test procedures, for instance the so-called kerf measurements at the wafer scoring frame—(in fact—as is apparent from the embodiments above—even before all the above process steps required for wafer 102 have been completed (i.e. already during the semi-completed state of the semi-conductor components 103 a , 103 b , 103 c , 103 d )).
- wafer 102 is (in particular fully automatically) transported to station B (and from there possibly to numerous further stations not shown here), where—as already mentioned above—wafer 102 is subjected to further appropriate process steps (in particular to corresponding coating, exposure, etching, diffusion, and/or implantation process steps, etc.), and/or to further test procedures—correspondingly similar to those applied at station A.
- wafer 102 is transported from the corresponding—previous—processing station (for instance from station B, or other further—downstream—stations)—in particular completely automatically—to the next station C.
- Station C serves to subject the semi-conductor components 103 a , 103 b , 103 c , 103 d —completed and still present on wafer 102 to—one or more—further test procedures (for instance so-called slice tests) by means of a test apparatus 116 .
- the voltages/currents and/or test signals required at station C for testing the semi-conductor components 103 a , 103 b , 103 c , 103 d on the wafer 102 are generated by test apparatus 116 , and fed by means of a semi-conductor component test card 118 , connected to the test apparatus 116 , to the corresponding connections of the semi-conductor components 103 a , 103 b , 103 c , 103 d (more precisely: by means of corresponding contact pins 119 a , 119 b provided on test card 118 ).
- wafer 102 Before being transported to station D, wafer 102 —and/or the components 103 a , 103 b 103 c , 103 d present on it—may be subjected to one or more further test procedures at one or several stations corresponding with station C.
- the carriers 111 a , 111 b , 111 c , 111 d are inserted into a corresponding carrier socket and/or carrier adapters and/or sockets, which are connected via corresponding lines 129 a , 129 b , 129 c , 129 d , to one (or more) corresponding test apparatus(es) 126 a , 126 b , 126 c , 126 d.
- the voltages/currents and/or test signals required at station E for testing the semi-conductor components 103 a , 103 b , 103 c , 103 d in the carriers 111 a , 111 b , 111 c , 111 d are generated by the test apparatus(es) 126 a , 126 b , 126 c , 126 d , and fed to corresponding connections on the semi-conductor components 103 a , 103 b , 103 c , 103 d via the carrier socket connected by the lines 129 a , 129 b , 129 c , 129 d to the test apparatus(es) 126 a , 126 b , 126 c , 126 d , and to the carriers 111 a , 111 b , 111 c , 111 d connected to them.
- the semi-conductor components 103 a , 103 b , 103 c , 103 d are further transported (in particular fully automatically) to one or more station(s)—not shown here—where the semi-conductor components 103 a , 103 b , 103 c , 103 d are mounted into the corresponding housings 112 a , 112 b , 112 c , 112 d (for instance corresponding plug-in or surface-mounted component housings, etc.).
- the semi-conductor component housings 112 a , 112 b , 112 c , 112 d are inserted into corresponding component housing sockets and/or component housing adapters connected—via corresponding lines 139 a , 139 b , 139 c , 139 d —to one (or more) corresponding test apparatus(es) 136 a , 136 b , 136 c , 136 d.
- test procedures used for testing the semi-conductor components 103 a , 103 b , 103 c , 103 d (for instance at station A, and/or station C, and/or station E, and/or station F, and/or station G, and/or further stations not shown here) and/or corresponding further test procedures performed by the test apparatuses 106 and/or 116 , and/or the test apparatuses 126 a , 126 b , 126 c , 126 d and/or 136 a , 136 b , 136 c , 136 d , and/or the test apparatus 146 , and/or by other test apparatuses—not shown here—(kerf measurements, slice tests, carrier tests, module tests, etc.)—may in each case involve the so-called DC tests, and/or for instance the so-called AC tests.
- FIG. 1 shows a schematic representation of a switching device installed on one of the semi-conductor components 103 a , 103 b , 103 c shown in FIGS. 2 a and 2 b , for performing a signal test procedure, in particular a procedure for assessing the signal quality of the test signal present at the semi-conductor component connection in question.
- the switching device contains a signal receiver switching section 1 , constructed similarly to conventional signal receiver switching sections from conventional semi-conductor components, and one which in the present embodiment example contains a reference circuit 2 and signal relay circuit 3 .
- a first input of the reference circuit 2 is connected via a line 4 a to an external connection of the semi-conductor components 103 a , 103 b , 103 c (for instance to a corresponding pad of the semi-conductor components 103 a , 103 b , 103 c ).
- a conventional input signal (voltage U e ), for instance one to be appropriately processed by the semi-conductor component 103 a , 103 b , 103 c , is applied to this connection, or, during a test operation of the semi-conductor components, a conventional test signal (voltage U e ), of which the quality can be assessed with the help of the signal-test procedure described here and which is made available by a corresponding test apparatus (for instance by one of the above test apparatuses 106 , 116 , 126 a , 126 b , 126 c , 126 d , 136 a , 136 b , 136 c , 136 d , 146 ), is applied.
- the bulk connections of both the n-channel MOSFET 5 a , 5 b are interconnected via a line 9 a , and connected to the earth potential via line 9 b connected to line 9 a.
- the source of the n-channel MOSFET 5 b is also connected to the current source device 6 (in fact, via a line 10 b , and the line 10 c connected to it).
- the current source device 6 is connected—via a line 10 d —to the earth potential.
- a direct current voltage at a particular level—for instance DC voltage V interface,internal , for instance V interface,internal 0.9 V, obtained from the above external supply voltage, is present at the line 14 a (which voltage is relayed—during the normal operation of the semi-conductor components—via switching device 13 and the line 4 b , to the above second input of the reference circuit 2 , where it is used as the reference voltage Vref, to be compared with the voltage U e present at the first input of the reference circuit).
- V interface,internal 0.9 V
- the level of the voltage V interface,internal present at line 14 a is lower, for instance about half as high as the level of the voltage V_DC, made available by the DC voltage source 12 and present at the above line 11 c.
- the switching device 13 is switched over from the state illustrated in FIG. 1 to a state in which line 4 b (and thereby the second input the reference circuit 2 ) is electrically connected to line 14 b —via the switching device 13 —and line 4 b is electrically disconnected from line 14 a —for instance by means of a corresponding control signal, fed by any one of the test apparatuses 106 , 116 , 126 a , 126 b , 126 c , 126 d , 136 a , 136 b , 136 c , 136 d , 146 to the above control input of the switching device 13 —not shown here.
- a “high logic” or a “low logic” output signal (voltage U a ) is emitted at the output of the signal relay circuit 3 (i.e.
- a test signal (voltage U e ) made available by a corresponding test apparatus 106 , 116 , 126 a , 126 b , 126 c , 126 d , 136 a , 136 b , 136 c , 136 d , 146 (and/or by a corresponding signal generating device of each test apparatus 106 , 116 , 126 a , 126 b , 126 c , 126 d , 136 a , 136 b , 136 c , 136 d , 146 ), of which the quality can be assessed with the aid of the signal test procedure described here, is applied—during the test operation of the semi-conductor components 103 a , 103 b , 103 c —to the connection of the semi-conductor components 103 a , 103 b , 103 c , which is connected to line 4 a.
- the reference circuit 2 compares the level of the voltage U e —present at line 4 a (i.e. at the first input of the reference circuit 2 )—with the voltage V interface,external correspondingly relayed via the switching device 13 during the test operation described above, to the (second) input of the reference circuit 2 (i.e. the line 4 b ).
- a “high logic” or a “low logic” output signal (voltage U a ) is emitted at the output of the signal relay circuit 3 (i.e.
- the output signal (voltage U a ) emitted at the output of the signal relay circuit 3 (and inverted in relation to the signal present at the input of the signal relay circuit 3 ) in every case “clearly” carries either a “high logic”, or a “low logic” signal level (and not for instance—as may be the case with the output signal 2 emitted by the reference circuit 2 —a level somewhere between a “high logic” and a “low logic” level).
- the level of the voltage U e present at the first input of the reference circuit 2 is higher or lower than the level of the voltage V interface,external present at the (second) input of the reference circuit 2 —at each measuring point t 1,0 , t 1,1 , t 1,2 , t 1,3 , t 1,4 .
- a voltage U e, mecanic may for instance therefore be regarded as an approximate “measurement result” for voltage U e , which lies between those two voltages V interface,external , in which the voltage U a has changed its state from “high logic” to “low logic” (or more correctly, a voltage U e, mecanic , lying between the lowest voltage V interface,external used, in which the voltage U a has (just) been “high logic” (or “low logic”), and the highest voltage V interface,external used, in which the voltage U a has (just) been “low logic” (or “high logic”).
- a measurement for voltage U e is then, as illustrated in FIG. 3 , also performed for the measurement interval t 2 —following on the (first) measurement interval t 1 —(i.e. at particular, chronologically adjacent measurement points t 2,0 , t 2,1 , t 2,2 , t 2,3 , t 2,4 —at voltages V interface,external changed in each case—the voltage V interface,external is compared with the voltage U e ), etc.
- the measurement results can—for instance as illustrated in FIG. 5 —be visualized for instance on a display device, for instance a video screen 20 , whereby every measurement result allocated to a particular measurement interval t 1 , t 2 etc. is in each case displayed in superimposed (or juxtaposed) rows (especially for instance—depending on whether at a particular measurement point t 1,0 , t 1,1 , t 1,2 , t 1,3 , t 1,4 , . . .
- the voltage U a is “high logic” or “low logic”—a display element (or several similar elements) allocated to each measurement point t 1,0 , t 1,1 , t 1,2 , t 1,3 , t 1,4 , . . . t 1,n , t 1,n+1 , t 1,n+2 is activated or deactivated (and/or for instance is made to light up “dimly” or “brightly” or to shine in various colors etc.)).
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
-
- a) Applying a signal (Ue), of which the quality is to be tested, to a connection of a semi-conductor component, wherein the procedure includes:
- b) Applying a reference signal (Vinterface,external) at a particular voltage level to a further connection of the semi-conductor component;
- c) Comparing the signal (Ue) with the reference signal (Vinterface,external);
- d) Changing the voltage level of the reference signal (Vinterface,external); and
- e) Again comparing the signal (Ue) with the reference signal (Vinterface,external).
- f) Changing the voltage level of the reference signal (Vinterface,external) to one which differs from the reference signal voltage level used in b) and d);
- g) Again comparing the signal (Ue) with the reference signal (Vinterface,external).
- 1 Signal receiver circuit section
- 2 Reference circuit
- 3 Signal relay circuit
- 4 a Line
- 4 b Line
- 5 a N-channel MOSFET
- 5 b N-channel MOSFET
- 6 Current source device
- 7 a Resistor
- 7 b Resistor
- 8 a Line
- 8 b Line
- 9 a Line
- 9 b Line
- 10 a Line
- 10 b Line
- 10 c Line
- 11 a Line
- 11 b Line
- 11 c Line
- 12 DC current source device
- 13 Switching device
- 14 a Line
- 14 b Line
- 15 Line
- 16 Line
- 17 a P-channel MOSFET
- 17 b N-channel MOSFET
- 18 a Line
- 18 b Line
- 18 c Line
- 18 d Line
- 18 e Line
- 19 Line
- 20 Video screen
- 102 Wafer
- 103 a Semi-conductor component
- 103 b Semi-conductor component
- 103 c Semi-conductor component
- 103 d Semi-conductor component
- 106 Test apparatus
- 107 Slicing machine
- 108 Test card
- 109 a Contact pin
- 109 b Contact pin
- 111 a Carrier
- 111 b Carrier
- 111 c Carrier
- 111 d Carrier
- 112 a Component housing
- 112 b Component housing
- 112 c Component housing
- 112 d Component housing
- 113 Electronic module
- 116 Test apparatus
- 118 Test card
- 119 a Contact pin
- 119 b Contact pin
- 126 a Test apparatus
- 26 b Test apparatus
- 126 c Test apparatus
- 126 d Test apparatus
- 129 a Line
- 129 b Line
- 129 c Line
- 129 d Line
- 136 a Test apparatus
- 136 b Test apparatus
- 136 c Test apparatus
- 136 d Test apparatus
- 139 a Line
- 139 b Line
- 139 c Line
- 139 d Line
- 146 Test apparatus
- 149 Line
Claims (19)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10344641.9 | 2003-09-25 | ||
DE10344641A DE10344641B4 (en) | 2003-09-25 | 2003-09-25 | Signal test method for testing of semiconductor devices, as well as test device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050093564A1 US20050093564A1 (en) | 2005-05-05 |
US7317323B2 true US7317323B2 (en) | 2008-01-08 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/948,741 Expired - Fee Related US7317323B2 (en) | 2003-09-25 | 2004-09-24 | Signal test procedure for testing semi-conductor components and a test apparatus for testing semi-conductor components |
Country Status (2)
Country | Link |
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US (1) | US7317323B2 (en) |
DE (1) | DE10344641B4 (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3772595A (en) * | 1971-03-19 | 1973-11-13 | Teradyne Inc | Method and apparatus for testing a digital logic fet by monitoring currents the device develops in response to input signals |
US3976940A (en) * | 1975-02-25 | 1976-08-24 | Fairchild Camera And Instrument Corporation | Testing circuit |
US20020109524A1 (en) | 2001-02-15 | 2002-08-15 | Udo Hartmann | Test system for conducting a function test of a semiconductor element on a wafer, and operating method |
US20030046624A1 (en) | 2001-08-28 | 2003-03-06 | Ali Muhtaroglu | Structural input levels testing using on-die levels generators |
US6657452B2 (en) * | 1999-12-17 | 2003-12-02 | Infineon Technologies Ag | Configuration for measurement of internal voltages of an integrated semiconductor apparatus |
US6747470B2 (en) * | 2001-12-19 | 2004-06-08 | Intel Corporation | Method and apparatus for on-die voltage fluctuation detection |
US6879175B2 (en) * | 2003-03-31 | 2005-04-12 | Teradyne, Inc. | Hybrid AC/DC-coupled channel for automatic test equipment |
-
2003
- 2003-09-25 DE DE10344641A patent/DE10344641B4/en not_active Expired - Fee Related
-
2004
- 2004-09-24 US US10/948,741 patent/US7317323B2/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3772595A (en) * | 1971-03-19 | 1973-11-13 | Teradyne Inc | Method and apparatus for testing a digital logic fet by monitoring currents the device develops in response to input signals |
US3976940A (en) * | 1975-02-25 | 1976-08-24 | Fairchild Camera And Instrument Corporation | Testing circuit |
US6657452B2 (en) * | 1999-12-17 | 2003-12-02 | Infineon Technologies Ag | Configuration for measurement of internal voltages of an integrated semiconductor apparatus |
US20020109524A1 (en) | 2001-02-15 | 2002-08-15 | Udo Hartmann | Test system for conducting a function test of a semiconductor element on a wafer, and operating method |
DE10107180A1 (en) | 2001-02-15 | 2002-09-26 | Infineon Technologies Ag | Test system for functional testing of a semiconductor component on a wafer and operating method |
US20030046624A1 (en) | 2001-08-28 | 2003-03-06 | Ali Muhtaroglu | Structural input levels testing using on-die levels generators |
US6747470B2 (en) * | 2001-12-19 | 2004-06-08 | Intel Corporation | Method and apparatus for on-die voltage fluctuation detection |
US6879175B2 (en) * | 2003-03-31 | 2005-04-12 | Teradyne, Inc. | Hybrid AC/DC-coupled channel for automatic test equipment |
Also Published As
Publication number | Publication date |
---|---|
US20050093564A1 (en) | 2005-05-05 |
DE10344641A1 (en) | 2005-05-12 |
DE10344641B4 (en) | 2007-07-12 |
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