US7197627B1 - Multiple processor arrangement for conserving power - Google Patents
Multiple processor arrangement for conserving power Download PDFInfo
- Publication number
- US7197627B1 US7197627B1 US09/830,719 US83071999A US7197627B1 US 7197627 B1 US7197627 B1 US 7197627B1 US 83071999 A US83071999 A US 83071999A US 7197627 B1 US7197627 B1 US 7197627B1
- Authority
- US
- United States
- Prior art keywords
- processor
- shadow
- host
- computer system
- interrupt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012545 processing Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 12
- 230000008569 process Effects 0.000 claims abstract description 12
- 230000002093 peripheral effect Effects 0.000 claims description 9
- 230000008859 change Effects 0.000 claims description 5
- 238000004891 communication Methods 0.000 claims 2
- 230000008901 benefit Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30116—Shadow registers, e.g. coupled registers, not forming part of the register space
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
Definitions
- the present invention relates to processing arrangements for computer architectures.
- co-processor adds functionality that the main processor in the architecture does not have or does not perform particularly efficiently.
- the co-processor generally uses instructions which are not implemented in the instruction set of the main processor. As such, many co-processors are used to address very specific code requirements, for example floating point arithmetic or signal processing. In most applications, this means that the instruction set of the co-processor is specific to that co-processor.
- main processors use real time operating systems to service multiple tasks and exceptions, such as interrupts. Servicing multiple tasks can result in context changes which can absorb significant amounts of the processing power available in the processor.
- a context change occurs when the task being executed by a processor is changed.
- the context of a task relates to the code corresponding to the task, and the state of the internal registers of the processor.
- sleep modes are used from which the processor must be reactivated when interrupt or service requests occur. When the processor is reactivated the context must be loaded and then the service performed, the processor then returns to an inactive state. Such a process can consume a large amount of power.
- a processing arrangement for a computer comprising:
- second processor means for processing a second set of instructions, the second set of instructions being a subset of the first set of instructions, wherein the second processor means is arranged to receive control signals and to process instructions in dependence upon those control signals without reference to the first processor means.
- FIG. 1 is a block diagram illustrating a computer processor architecture in accordance with the present invention
- FIG. 2 shows a computer architecture including multiple processors
- FIG. 3 is a diagramatic illustration of how processors embodying the present invention can realise the functionality of a desired virtual processor.
- FIG. 1 shows a block diagram illustrating a host (or first) processor 1 connected with a shadow (or second) processor 2 .
- the shadow processor 2 is used to control interrupts received from peripherals connected to the processor system.
- the host processor 1 communicates with an external bus 3 by way of an external bus interface 4 .
- the external bus 3 is used for transferring data to and from the main processor and memory devices (not shown).
- the host processor 1 also includes a memory controller 5 for controlling data access with memory devices.
- the memory controller 5 is controlled itself by an execution unit 6 which has overall control of the main processor 1 .
- the host processor 1 also include an arithmetic logic unit (ALU) 7 and a number of registers 8 , sixteen in the example shown.
- ALU arithmetic logic unit
- a shadow processor 2 is connected to the main processor 1 .
- the shadow processor 2 includes an interrupt controller 10 which receives interrupt signals via interrupt inputs 12 .
- the shadow processor also includes registers which correspond to selected ones of the registers of the host processor 1 .
- the interrupt controller can be connected, as in the example of FIG. 1 , to peripherals connected to a peripheral bus 11 .
- the shadow processor 2 also includes an execution unit 14 , code memory 15 , and data memory 16 .
- the shadow processor 2 operates to process a selected subset of the instructions from which the host processor operates, and these instructions are stored in the code memory 15 .
- the shadow processor 2 has access to the host processor memory by way of a memory controller 17 which interfaces with the external bus 3 by way of the host external bus interface 4 .
- the Host Interrupt Controller 18 is a module which allows the shadow processor to issue an interrupt to the host processor in order to cause a change in task execution, a context change, appropriate to the requirements of the system. It generates an interrupt to the host using the host interrupt protocol and indicating the source of the interrupt as a vector programmed by the shadow process related to the new task required.
- a peripheral raises an interrupt request on the interrupt input lines 12 .
- the input controller 10 operates to interpret the interrupt request, and if the interrupt request is of the type able to be processed by the shadow processor 2 , then the shadow processor 2 will service that interrupt.
- An example of an interrupt is if an external device such as a serial port has received data from a system to which it is attached. The data from such a serial port may be contained within a message body including information about the source and content of the data.
- the shadow processor 2 then services the interrupts required by receiving the message then removing the data from that message.
- the main processor 1 Once the data has been removed and checked it issues an interrupt to the main processor 1 via the Host Interrupt Contoller 18 having first set up the context needed by the task to service the data within the message.
- the main processor 1 would begin processing the data while the shadow processor 2 stores the context of the interrupted task.
- the Register Bridge unit 19 allows multiple access to a set of registers by both host and shadow processor. It allows physical registers to appear in both processor systems while resolving any conflict in their access and mapping of those registers within the physical resource space of the processors.
- This unit contains multiplexers to allow dual access to either processor buses, arbitration logic to prevent access conflict, and logic to allow access addresses to be altered to allow re-mapping of the location of the registers in the address map of either processor.
- registers mapped to positions 4 – 7 in the host may appear also in positions 4 – 7 in the shadow or be re-mapped to 8 – 11 of the shadow.
- registers x-y of the host may be exchanged for equivalent registers in the shadow and vice-versa. This allows registers x-y of the shadow to be loaded with a new context then swapped in to the host in a context change. The registers replaced in the shadow would contain the old host context and can be stored or re-stored by the shadow while the host is processing the new context.
- the shadow processor 2 While the host processor 1 is processing a task or is in an unactive (“sleep”) mode, the shadow processor 2 will accept interrupts to determine the requirement and decide on the action required. If the action can be handled by the shadow processor alone then it is serviced without reference to the host, but if it does require some intervention by the host, the shadow processor 2 will activate the host processor by way of the host interrupt controller 18 .
- the shadow processor 2 can service routine requests from the peripherals without the need for host intervention.
- Data to be processed is shared between the host processor and the shadow processor by way of the register bridge unit 19 , in order that the same data can be operated on by both processors.
- the shadow processor 2 is able to use a subset of the instruction set of the host processor.
- the main advantage of such a shadow processor is that instruction code can be readily shared between the host and the shadow, without the need for processor emulation or complex code conversion.
- the other significant advantage is that any work needed to develop the shadow processor can be based on the host processor development work.
- the shadow processor design can be optimised, based specifically on the processing of a limited range of instructions of the host processor. Code written for such an application can be analysed to identify the most frequently used instructions, and shadow processors can be provided for those most frequently used instructions. The shadow processor can then be based on the common instruction set but minimum register and addressing range requirements.
- the shadow processor has access to all the relevant register and memory areas used by the host processor and so the host and shadow processor can work in tandem, the shadow processor performing tasks for which it is designed independently of any reference to the host processor. It will be appreciated that a plurality of shadow processors can be used with a single host processor to provide efficient data processing without the need to refer directly to the host processor itself.
- shadow processor can service interrupt requests and other routine tasks without the need to move the host processor into an active state. This can reduce the power consumption of the processing system in total.
- FIGS. 2 and 3 show that shadow processors can be arranged to share data and registers so that processing of program steps can have continuity.
- FIG. 2 is an application of a shadow processor concept without the use of a host processor.
- a number of shadow processors are arranged in sequence; each processor performs a particular process on data derived from previous shadow processors and passes the processed data on to the next in the sequence.
- the sequence has input/output ports on the end shadow processors for connection to other system components. Processing occurs in both directions from shadow processor (i.e. 1 to 5 and 5 to 1).
- sections 3 and 4 contain two shadow processors (A&B) with additional input/output to be combined with the main sequence.
- Shadow processor 6 performs the task of memory control and ensures that appropriate code is loaded into the shadow processors from main memory as required. It also performs the main co-ordination task for the system.
- shadow processor 1 An application is of such a configuration could be a telecommunications terminal.
- the I/O of shadow processor 1 would be attached to the RF subsystem, I/O of processor 5 to the Audio sub-system.
- the secondary I/O of shadow processors 3 b / 4 b to the data processing, and user interfaces e.g. LCD and keyboard.
- Each of the shadow processors 1 – 5 perform specific tasks required such as audio codec, interleaving/de-interleaving, etc.
- FIG. 3 is an example of a virtual processor concept.
- the main processor is provided as a virtual processor, which may only exist in concept and as a simulation. From this virtual processor various applications are analysed and specific implementations derived. Three such implementations 1–3 are drawn below the Host. Each of the implementations contains specific components of the host required by the applications.
- Shadow processor A. (1) could be characteristic of a RISC CPU
- Shadow processor B (2) could be an example of a logic processor
- Shadow processor C (3) could be an example of a memory management processor.
- FIG. 3 The important distinction of FIG. 3 is that the host is a virtual processor it may not physically exist.
- the shadow processors are optimised fragments of the virtual processor synthesised to a physical implementation on a chip.
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Multi Processors (AREA)
- Advance Control (AREA)
- Control By Computers (AREA)
Abstract
Description
Claims (12)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9823819A GB2343269A (en) | 1998-10-30 | 1998-10-30 | Processing arrangements |
PCT/EP1999/008058 WO2000026772A1 (en) | 1998-10-30 | 1999-10-25 | Processing arrangements |
Publications (1)
Publication Number | Publication Date |
---|---|
US7197627B1 true US7197627B1 (en) | 2007-03-27 |
Family
ID=10841599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/830,719 Expired - Lifetime US7197627B1 (en) | 1998-10-30 | 1999-10-25 | Multiple processor arrangement for conserving power |
Country Status (11)
Country | Link |
---|---|
US (1) | US7197627B1 (en) |
EP (1) | EP1125194B1 (en) |
JP (1) | JP2002529810A (en) |
KR (1) | KR20010080349A (en) |
CN (1) | CN1135469C (en) |
AU (1) | AU763319B2 (en) |
BR (1) | BR9914966A (en) |
EE (1) | EE200100237A (en) |
GB (1) | GB2343269A (en) |
MY (1) | MY121811A (en) |
WO (1) | WO2000026772A1 (en) |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040187126A1 (en) * | 2003-02-21 | 2004-09-23 | Sharp Kabushiki Kaisha | Asymmetrical multiprocessor system, image processing apparatus and image forming apparatus using same, and unit job processing method using asymmetrical multiprocessor |
US20070234007A1 (en) * | 2006-03-31 | 2007-10-04 | Ho-Hsin Lin | Electronic data processing device with dual-cpu |
US20080256551A1 (en) * | 2005-09-21 | 2008-10-16 | Freescale Semiconductor. Inc. | System and Method For Storing State Information |
US20100250987A1 (en) * | 2009-03-26 | 2010-09-30 | Brother Kogyo Kabushiki Kaisha | Processing Device |
US20100250989A1 (en) * | 2002-08-14 | 2010-09-30 | Hamilton Tony G | Method and apparatus for a computing system having an active sleep mode cpu that uses the cache of a normal active mode cpu |
US20100262742A1 (en) * | 2009-04-14 | 2010-10-14 | Andrew Wolfe | Interrupt Arbitration For Multiprocessors |
US20100274879A1 (en) * | 2009-04-24 | 2010-10-28 | Andrew Wolfe | Dynamic Scheduling Interrupt Controller For Multiprocessors |
US20100274941A1 (en) * | 2009-04-24 | 2010-10-28 | Andrew Wolfe | Interrupt Optimization For Multiprocessors |
US20110087815A1 (en) * | 2009-10-13 | 2011-04-14 | Ezekiel John Joseph Kruglick | Interrupt Masking for Multi-Core Processors |
CN102360278A (en) * | 2011-09-07 | 2012-02-22 | 苏州科雷芯电子科技有限公司 | Separating type computer system of control instructions and calculation instructions |
US8468009B1 (en) * | 2006-09-28 | 2013-06-18 | Cadence Design Systems, Inc. | Hardware emulation unit having a shadow processor |
US20140101383A1 (en) * | 2012-10-04 | 2014-04-10 | Texas Instruments Incorporated | Register bank cross path connection method in a multi core processor system |
US20170017486A1 (en) * | 2015-07-16 | 2017-01-19 | Nxp B.V. | Method and system for processing instructions in a microcontroller |
US11321091B2 (en) * | 2019-10-29 | 2022-05-03 | Nuvoton Technology Corporation | Storage devices mapped to registers and mapping methods thereof |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5090591B2 (en) | 2000-04-12 | 2012-12-05 | ソニー株式会社 | Electronic device control method, electronic device, and function recognition method of electronic device |
GB2382674B (en) * | 2001-10-31 | 2005-11-16 | Alphamosaic Ltd | Data access in a processor |
US7069442B2 (en) * | 2002-03-29 | 2006-06-27 | Intel Corporation | System and method for execution of a secured environment initialization instruction |
JP4194953B2 (en) | 2002-04-18 | 2008-12-10 | エヌエックスピー ビー ヴィ | Multiple instruction issue processor |
KR100663709B1 (en) | 2005-12-28 | 2007-01-03 | 삼성전자주식회사 | Apparatus and method of exception handling for reconfigurable architecture |
CN105204393B (en) * | 2015-08-13 | 2017-12-26 | 彭增金 | Single-chip microcomputer R&D and production instrument and its implementation based on empty core single-chip microcomputer |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1576276A (en) | 1976-02-25 | 1980-10-08 | Siemens Ag | Data processing system comprising a plurality of processor |
EP0174231A1 (en) | 1984-08-02 | 1986-03-12 | Telemecanique | Programmable controller ("PC") with co-processing architecture |
US5021991A (en) * | 1983-04-18 | 1991-06-04 | Motorola, Inc. | Coprocessor instruction format |
US5226127A (en) * | 1989-04-07 | 1993-07-06 | Intel Corporation | Method and apparatus providing for conditional execution speed-up in a computer system through substitution of a null instruction for a synchronization instruction under predetermined conditions |
US5283881A (en) | 1991-01-22 | 1994-02-01 | Westinghouse Electric Corp. | Microcoprocessor, memory management unit interface to support one or more coprocessors |
US5495588A (en) | 1993-11-18 | 1996-02-27 | Allen-Bradley Company, Inc. | Programmable controller having joined relay language processor and general purpose processor |
US5614847A (en) * | 1992-04-14 | 1997-03-25 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction mechanism |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4395758A (en) * | 1979-12-10 | 1983-07-26 | Digital Equipment Corporation | Accelerator processor for a data processing system |
US5588118A (en) * | 1991-08-21 | 1996-12-24 | Zilog, Inc. | Single chip dual processor |
-
1998
- 1998-10-30 GB GB9823819A patent/GB2343269A/en not_active Withdrawn
-
1999
- 1999-10-25 WO PCT/EP1999/008058 patent/WO2000026772A1/en not_active Application Discontinuation
- 1999-10-25 EE EEP200100237A patent/EE200100237A/en unknown
- 1999-10-25 JP JP2000580087A patent/JP2002529810A/en not_active Withdrawn
- 1999-10-25 US US09/830,719 patent/US7197627B1/en not_active Expired - Lifetime
- 1999-10-25 EP EP99950777A patent/EP1125194B1/en not_active Expired - Lifetime
- 1999-10-25 CN CNB99812768XA patent/CN1135469C/en not_active Expired - Lifetime
- 1999-10-25 AU AU63424/99A patent/AU763319B2/en not_active Ceased
- 1999-10-25 KR KR1020017005385A patent/KR20010080349A/en not_active Application Discontinuation
- 1999-10-25 BR BR9914966-4A patent/BR9914966A/en not_active IP Right Cessation
- 1999-10-29 MY MYPI99004679A patent/MY121811A/en unknown
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1576276A (en) | 1976-02-25 | 1980-10-08 | Siemens Ag | Data processing system comprising a plurality of processor |
US5021991A (en) * | 1983-04-18 | 1991-06-04 | Motorola, Inc. | Coprocessor instruction format |
EP0174231A1 (en) | 1984-08-02 | 1986-03-12 | Telemecanique | Programmable controller ("PC") with co-processing architecture |
EP0174231B1 (en) | 1984-08-02 | 1990-11-14 | Telemecanique | Programmable controller ("pc") with co-processing architecture |
US5226127A (en) * | 1989-04-07 | 1993-07-06 | Intel Corporation | Method and apparatus providing for conditional execution speed-up in a computer system through substitution of a null instruction for a synchronization instruction under predetermined conditions |
US5283881A (en) | 1991-01-22 | 1994-02-01 | Westinghouse Electric Corp. | Microcoprocessor, memory management unit interface to support one or more coprocessors |
US5614847A (en) * | 1992-04-14 | 1997-03-25 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction mechanism |
US5495588A (en) | 1993-11-18 | 1996-02-27 | Allen-Bradley Company, Inc. | Programmable controller having joined relay language processor and general purpose processor |
Non-Patent Citations (1)
Title |
---|
International Search Report as completed by the ISA/EP on Jan. 31, 2000 in connection with International Patent Application No. PCT/EP99/08058 as mailed Feb. 4, 2000. |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8301916B2 (en) * | 2002-08-14 | 2012-10-30 | Intel Corporation | Method and apparatus for a computing system having an active sleep mode CPU that uses the cache of a normal active mode CPU |
US20100250989A1 (en) * | 2002-08-14 | 2010-09-30 | Hamilton Tony G | Method and apparatus for a computing system having an active sleep mode cpu that uses the cache of a normal active mode cpu |
US7587716B2 (en) * | 2003-02-21 | 2009-09-08 | Sharp Kabushiki Kaisha | Asymmetrical multiprocessor system, image processing apparatus and image forming apparatus using same, and unit job processing method using asymmetrical multiprocessor |
US20040187126A1 (en) * | 2003-02-21 | 2004-09-23 | Sharp Kabushiki Kaisha | Asymmetrical multiprocessor system, image processing apparatus and image forming apparatus using same, and unit job processing method using asymmetrical multiprocessor |
US20080256551A1 (en) * | 2005-09-21 | 2008-10-16 | Freescale Semiconductor. Inc. | System and Method For Storing State Information |
US20070234007A1 (en) * | 2006-03-31 | 2007-10-04 | Ho-Hsin Lin | Electronic data processing device with dual-cpu |
US7490222B2 (en) * | 2006-03-31 | 2009-02-10 | Micro-Star International Co., Ltd. | High and low power dual CPU cardiograph data processing system with gathering an display |
US8468009B1 (en) * | 2006-09-28 | 2013-06-18 | Cadence Design Systems, Inc. | Hardware emulation unit having a shadow processor |
US20100250987A1 (en) * | 2009-03-26 | 2010-09-30 | Brother Kogyo Kabushiki Kaisha | Processing Device |
US8261115B2 (en) * | 2009-03-26 | 2012-09-04 | Brother Kogyo Kabushiki Kaisha | Sub-processor configured to execute a specific program stored in the first memory or second memory on behalf of the main processor |
US7996595B2 (en) * | 2009-04-14 | 2011-08-09 | Lstar Technologies Llc | Interrupt arbitration for multiprocessors |
US20100262742A1 (en) * | 2009-04-14 | 2010-10-14 | Andrew Wolfe | Interrupt Arbitration For Multiprocessors |
US20100274941A1 (en) * | 2009-04-24 | 2010-10-28 | Andrew Wolfe | Interrupt Optimization For Multiprocessors |
US20100274879A1 (en) * | 2009-04-24 | 2010-10-28 | Andrew Wolfe | Dynamic Scheduling Interrupt Controller For Multiprocessors |
US8260996B2 (en) | 2009-04-24 | 2012-09-04 | Empire Technology Development Llc | Interrupt optimization for multiprocessors |
US8321614B2 (en) | 2009-04-24 | 2012-11-27 | Empire Technology Development Llc | Dynamic scheduling interrupt controller for multiprocessors |
US20110087815A1 (en) * | 2009-10-13 | 2011-04-14 | Ezekiel John Joseph Kruglick | Interrupt Masking for Multi-Core Processors |
US8234431B2 (en) | 2009-10-13 | 2012-07-31 | Empire Technology Development Llc | Interrupt masking for multi-core processors |
CN102360278A (en) * | 2011-09-07 | 2012-02-22 | 苏州科雷芯电子科技有限公司 | Separating type computer system of control instructions and calculation instructions |
US20140101383A1 (en) * | 2012-10-04 | 2014-04-10 | Texas Instruments Incorporated | Register bank cross path connection method in a multi core processor system |
US9153295B2 (en) * | 2012-10-04 | 2015-10-06 | Texas Instruments Incorporated | Register bank cross path connection method in a multi core processor system |
US20170017486A1 (en) * | 2015-07-16 | 2017-01-19 | Nxp B.V. | Method and system for processing instructions in a microcontroller |
US10942748B2 (en) * | 2015-07-16 | 2021-03-09 | Nxp B.V. | Method and system for processing interrupts with shadow units in a microcontroller |
US11321091B2 (en) * | 2019-10-29 | 2022-05-03 | Nuvoton Technology Corporation | Storage devices mapped to registers and mapping methods thereof |
Also Published As
Publication number | Publication date |
---|---|
MY121811A (en) | 2006-02-28 |
BR9914966A (en) | 2001-07-10 |
EP1125194A1 (en) | 2001-08-22 |
GB2343269A (en) | 2000-05-03 |
KR20010080349A (en) | 2001-08-22 |
EP1125194B1 (en) | 2005-12-28 |
JP2002529810A (en) | 2002-09-10 |
CN1325511A (en) | 2001-12-05 |
EE200100237A (en) | 2002-08-15 |
WO2000026772A1 (en) | 2000-05-11 |
CN1135469C (en) | 2004-01-21 |
AU763319B2 (en) | 2003-07-17 |
AU6342499A (en) | 2000-05-22 |
GB9823819D0 (en) | 1998-12-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7197627B1 (en) | Multiple processor arrangement for conserving power | |
US6223279B1 (en) | Single chip microcomputer having a dedicated address bus and dedicated data bus for transferring register bank data to and from an on-line RAM | |
US5428779A (en) | System and method for supporting context switching within a multiprocessor system having functional blocks that generate state programs with coded register load instructions | |
AU628524B2 (en) | Modular crossbar interconnection network for data transactions between system units in a multi-processor system | |
EP0794492B1 (en) | Distributed execution of mode mismatched commands in multiprocessor computer systems | |
KR100879825B1 (en) | Instruction set architecture-based inter-sequencer communications with a heterogeneous resource | |
US20030093648A1 (en) | Method and apparatus for interfacing a processor to a coprocessor | |
JP4226085B2 (en) | Microprocessor and multiprocessor system | |
KR20170036035A (en) | Apparatus and method for configuring sets of interrupts | |
US5832280A (en) | Method and system in a data processing system for interfacing an operating system with a power management controller. | |
JPH08305585A (en) | Interruption controller | |
KR100288170B1 (en) | Data processor with a compute unit that shares a set of register files | |
US5666510A (en) | Data processing device having an expandable address space | |
US6339808B1 (en) | Address space conversion to retain software compatibility in new architectures | |
US5933613A (en) | Computer system and inter-bus control circuit | |
KR100277805B1 (en) | Data processing device | |
US6701388B1 (en) | Apparatus and method for the exchange of signal groups between a plurality of components in a digital signal processor having a direct memory access controller | |
KR100385493B1 (en) | Microcontroller with a reconfigurable program status word | |
JP2000298652A (en) | Multiprocessor | |
JP2004537809A (en) | Efficient interrupt system for system-on-chip design | |
US6195747B1 (en) | System and method for reducing data traffic between a processor and a system controller in a data processing system | |
EP1193607A2 (en) | Apparatus and method for the exchange of signal groups between a plurality of components in a digital signal processor having a direct memory access controller | |
JPH05165641A (en) | Single chip microcomputer | |
CN114327751A (en) | Virtual PCI equipment facing multi-domain isolated communication and implementation method thereof | |
JPH06259385A (en) | Multiprocessor system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL), SWEDEN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NAYLOR, ROWAN NIGEL;REEL/FRAME:012432/0616 Effective date: 20010925 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |