US6515905B2 - Nonvolatile semiconductor memory device having testing capabilities - Google Patents
Nonvolatile semiconductor memory device having testing capabilities Download PDFInfo
- Publication number
- US6515905B2 US6515905B2 US09/578,915 US57891500A US6515905B2 US 6515905 B2 US6515905 B2 US 6515905B2 US 57891500 A US57891500 A US 57891500A US 6515905 B2 US6515905 B2 US 6515905B2
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- Prior art keywords
- cell
- signal
- counter
- value
- semiconductor memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
Definitions
- the present invention generally relates to an electrically erasable, rewritable nonvolatile semiconductor memory device (EEPROM) with testability, more particularly to a semiconductor memory device such as a flash memory with an automatic write or erase function.
- EEPROM electrically erasable, rewritable nonvolatile semiconductor memory device
- Flash memories have been in greatly increased demand in recent years due to non-volatility, easiness of erase and rewrite operations and adoption of single transistor cells.
- a flash memory cell is of a stacked gate type in which a floating gate electrode is buried in the gate oxide film of a MOS transistor, and in a read operation, a high voltage is applied to the control gate while a voltage is applied between the drain and the source of the transistor to inject channel electrons into the floating gate electrode. With this electron injection, the threshold voltage of the transistor rises.
- an erase operation is required before a write operation.
- the erase operation a high voltage is applied to the source while leaving the drain in an open state to release electrons held in the floating electrode by a tunnel effect.
- the floating gate in the memory cell is charged positive and thereby, a current flows between the source and the drain even if the control gate is set to OV, resulting in an erroneous read.
- a write operation in order to prevent excessive write, there is repeated the process of providing a write pulse having a short width to the memory cell, performing a read operation on the memory cell and judging whether or not a write operation has been performed properly.
- Such a repetition is performed automatically by a control circuit in a flash memory in response to an automatic write command or an automatic erase command, and when the repetition count exceeds a predetermined value before the operation of the automatic write or automatic erase has been completed, an error signal from the counter is activated to abnormally terminate the control operation.
- a nonvolatile semiconductor memory comprising a cell array, each cell having a floating gate; a sense amplifier for determining a logic value of a signal read from an addressed cell by comparing the signal with a reference signal; a counter for activating an error signal when a count thereof reaches a first predetermined value; and a control circuit, for repeating a write or erase operation on the addressed cell in response to an automatic write or erase command until the logic value reaches an expected value, for providing a counting signal to the counter at every repetition of the operation, for abnormally terminating the repetitions when the error signal has been activated, wherein the control circuit makes the counter load a second predetermined value for decreasing the number of the repetitions, prior to starting of the repetitions when a test signal is active.
- the second predetermined value is loaded into the counter by activating the test signal in the test prior to product shipment, thereby it can be judged whether or not an error signal is outputted normally prior to a write or erase operation on a memory cell, or by smaller times of repetitions of write or erase operations. Accordingly the test can be performed with a shorter time and with certainty even if no error cell is present. Further, since in the test, the memory cell array receives no or less stress, a product lifetime will be extended.
- FIG. 1 is a schematic block diagram showing a flash memory of the first embodiment according to the present invention
- FIG. 2 is a circuit diagram of the memory cell block of FIG. 1;
- FIG. 3 is a flow chart showing an automatic write operation
- FIG. 4 is a flow chart showing an automatic erase operation on a selected cell row of a selected memory cell block
- FIG. 5 is a schematic circuit diagram showing part of a flash memory of the second embodiment according to the present invention.
- FIG. 6 is a graph of characteristics of relations between control gate voltages and drain currents of the four reference cells of FIG. 5;
- FIG. 7 is a flow chart showing an automatic write operation
- FIG. 8 is a flow chart showing an automatic erase operation on a selected cell row of a selected memory cell block.
- FIG. 9 is a circuit diagram showing one memory cell block and one row decoder of a flash memory of the third embodiment according to the present invention.
- FIG. 1 is a schematic block diagram showing a flash memory of the first embodiment according to the present invention.
- a memory cell array 10 includes memory cell blocks BLK 0 to BLK 3 with the same configuration as one another, and memory cells are erasable in units of blocks.
- FIG. 2 shows a circuit of the memory cell block BLK 0 .
- the BLK 0 is a memory cell array having 256 rows and 64 columns, and each memory cell is a stacked gate EEPROM cell in which a floating gate is buried in the gate oxide film of an NMOS transistor.
- the control gates in the i-th row are connected to a word line WLi
- the sources of the cell transistors in the k-th column are connected to a bit line BLk
- the sources of all the cell transistors in the memory cell block BLK 0 are connected to a source line SL 0 .
- Write, erase and read operations on a memory cell are the same as those in the prior art well known to persons skilled in the art and therefore, descriptions thereof are omitted.
- an address ADDR and an data DATA from the outside are provided to an address input circuit 11 and a data input circuit 12 , respectively.
- Each of the circuits 11 and 12 has a buffer gate circuit and a buffer register connected to the buffer gate.
- the outputs from the address input circuit 11 and the data input circuit 12 are provided to a command decoder 13 , and the decoded result is provided to a control circuit 14 .
- the circuit 14 performs various controls to execute a read command, a write command, an erase command, an automatic write command or an automatic erase command in response to the activation thereof.
- a multiplexer 16 selects one of the outputs of the address input circuit 11 and the address counter 15 in response to a control signal from the control circuit 14 and provides, for example, the upper order 8 bits A 15 to A 8 of the address bits A 15 to A 0 to a row decoder 17 , the next 2 bits to a source decoder 18 and the lower order 6 bits A 5 to A 0 to a column decoder 19 .
- one of word lines WL 0 to WL 255 is selected by the output of the row decoder 17 , one of the source lines SL 0 to SL 3 by the output of the source decoder 18 and one column switch in a column gate circuit 20 by the output of the column decoder 19 .
- a signal read out from a cell selected by the row decoder 17 , the source decoder 18 and the column decoder 20 is compared with a reference value, and its result is amplified by a sense amplifier 21 to transform into a data DO of ‘0’ or ‘1’, which is provided to the data input circuit 12 and the control circuit 14 .
- the DATA is provided through the data input circuit 12 and the column gate 20 to a selected bit line.
- a power supply circuit 22 supplies predetermined power-supply voltages to the row decoder 17 , the source decoder 18 and the column decoder 19 in response to a control signal from the control circuit 17 , depending on a command from the command decoder 13 . With this and address value, the voltages applied onto the word lines, source lines and bit lines are determined.
- a counter 23 In an automatic write operation or an automatic erase operation, a counter 23 is used. To its clear input CLR, clock input CK and load control input LD, a signal from the control circuit 14 is provided. To the data loading input of the counter 23 , a set value CNmax is provided. When the count of the counter 23 reaches the set value CNmax, e.g., the maximum value, the output ERR of the counter 23 is activated.
- the error signal ERR is not only provided to the input of the control circuit 14 , but also externally outputted through an interconnection between the input and an external terminal. Further, a test signal TS is provided from an external terminal to the control circuit 14 .
- FIG. 3 is a flow chart showing an automatic write operation. Reference characters in parentheses below are step identifications in FIG. 3 .
- test signal TS If the test signal TS is active, then the process goes to step S 2 , or else the process goes to step S 3 .
- the test signal TS is inactive, while in a test, the test signal TS is activated.
- step S 4 In a case of the test, since the error signal ERR is activated by processing of step S 2 , the operation of the control circuit 14 stops abnormally.
- a test device (not shown) can confirm whether or not the error signal is outputted normally from the flash memory by detecting whether or not the error signal ERR is active. In a case where the error signal ERR is inactive, the flash memory is regarded as defective since the automatic write operation or automatic erase operation in the use by a end user gets into an endless loop.
- step S 5 In cases of the flash memory being in use by an end user or being defective, the process goes to step S 5 since the error signal ERR is inactive. In the case of use by an end user, when the error signal ERROR is activated after repetitions of from step S 4 to step S 8 at CNmax times, the operation of the control circuit 14 stops abnormally.
- the control circuit 14 provides a pulse to the clock input CL of the counter 23 to increment the count thereof.
- step S 8 If the data DO is not equal to an expected value, that is, a value to be written, the process returns to step S 4 , or else the control circuit 14 normally completes a write operation for one address.
- FIG. 4 is a flow chart showing an automatic erase operation on a selected cell row of a selected memory block.
- the fundamental operation of the automatic erase operation is the same as that of the automatic write operation.
- step S 5 A the erase operation on a selected cell row is carried out by one time.
- step S 6 A read operations are performed on the cells of a selected row and step S 8 A, it is judged whether or not all of the cells of the row are equal to an expected value.
- the process of FIG. 4 is carried out sequentially and automatically on each cell row of a memory cell block to be erased.
- the set value CNmax is loaded into the counter 23 and it can be confirmed whether or not the error signal ERR is outputted normally, prior to execution of a write operation or an erase operation on a memory cell, and therefore, the test can be carried out at a high speed and with certainty even if no error cell is present. Further, since in the test, no stress is imposed on the memory cell array 10 , a product lifetime will be extended.
- FIG. 5 is a schematic circuit diagram showing part of a flash memory of the second embodiment according to the present invention.
- a cell in a written state is referred to as being “0” state and a cell in an erased state as being “1” state.
- the reference cell array 30 includes a “0” judgment reference cell TR 0 in a test, a “0” judgment reference cell R 0 in a normal use, a “1” judgment reference cell R 1 in a normal use, and a “1” judgment reference cell TR 1 in a test, wherein the cells are all same as those of the memory cell array 10 in configuration and size.
- reference cells used in execution of a read command is omitted.
- each of the relations between the control gate voltages VG and the drain currents ID is as shown in FIG. 6 .
- the sources are connected to a source line SLX, the control gates to a word line WLX and the drains through bit lines BL 0 to BL 3 to the respective inputs of a selector 31 .
- a reference cell selection signal RS To the selection control input of the selector 31 , there are provided a reference cell selection signal RS and the test signal TS.
- the signal RS is outputted from the control circuit 14 of FIG. 1 . Assume that the signal RS has a logic value ‘0 ’ in a write operation and a logic value ‘1’ in an erase operation.
- no signal is provided from the control circuit 14 to the load control input LD of the counter 23 , and no set value CNmax is loaded into the counter 23 either.
- FIGS. 7 and 8 are similar to FIGS. 3 and 4, respectively, and same as FIGS. 3 and 4 with the exception that steps S 1 and S 2 of FIGS. 3 and 4 are omitted.
- the count of the counter 23 reaches the set value by repeat even if no error cell is present, the error signal ERR is activated and thereby, the same test as that of the first embodiment can be carried out.
- FIG. 9 shows one memory block BLK 0 A and one row decoder 17 A of a flash memory of the third embodiment according to the present invention.
- the memory block BLK 0 A has a configuration in which a redundant cell row 33 is added to the memory cell block BLK 0 of FIG. 2 .
- the row address bits A 15 to A 8 and the test signal TS are provided to the row decoder 17 A.
- the test signal TS is inactive, one of the word lines WL 0 to WL 255 are selected same as the case of FIG. 2 in response to the row address bits A 15 to A 8 .
- the test signal is active, none of the word lines WL 0 to WL 255 are selected regardless of the row address bits A 15 to A 8 , and a word line 256 is selected.
- a down-counter may be adopted as the counter 23 of FIG. 1, and in the automatic write operation, in normal use, the set value CNmax is loaded into the counter 23 , while in a test, the counter is cleared to zero. And when a count of the counter 23 is 0 or ⁇ 1, the error signal is activated. This is applicable to a case of the automatic erase operation. Different set values CNmax may be used in cases of the automatic write operation and the automatic erase operation.
Abstract
Description
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP15585699A JP4251717B2 (en) | 1999-06-03 | 1999-06-03 | Nonvolatile semiconductor memory device |
JP11-155856 | 1999-06-03 |
Publications (2)
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US20010048609A1 US20010048609A1 (en) | 2001-12-06 |
US6515905B2 true US6515905B2 (en) | 2003-02-04 |
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US09/578,915 Expired - Lifetime US6515905B2 (en) | 1999-06-03 | 2000-05-26 | Nonvolatile semiconductor memory device having testing capabilities |
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US (1) | US6515905B2 (en) |
JP (1) | JP4251717B2 (en) |
KR (1) | KR100572166B1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6781878B2 (en) * | 2002-08-12 | 2004-08-24 | Matrix Semiconductor, Inc. | Dynamic sub-array group selection scheme |
US20040218420A1 (en) * | 2003-04-29 | 2004-11-04 | Dialog Semiconductor Gmbh | Flash memory with pre-detection for data loss |
US20050012868A1 (en) * | 2003-07-18 | 2005-01-20 | Samsung Electronics Co., Ltd. | Analog-to-digital converting apparatus for processing a plurality of analog input signals at high rate and display device using the same |
US20060181955A1 (en) * | 2005-02-16 | 2006-08-17 | Renesas Technology Corp. | Semiconductor integrated circuit device |
US20150294736A1 (en) * | 2014-04-15 | 2015-10-15 | SK Hynix Inc. | Semiconductor device, semiconductor memory device and memory system |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2851843B1 (en) * | 2003-02-27 | 2005-08-05 | St Microelectronics Sa | FLASH MEMORY COMPRISING AN ERASURE VERIFICATION ALGORITHM INTEGRATED IN A PROGRAMMING ALGORITHM |
JP2005056394A (en) * | 2003-07-18 | 2005-03-03 | Toshiba Corp | Storage device and memory card |
US7558149B2 (en) * | 2006-01-24 | 2009-07-07 | Macronix International Co., Ltd. | Method and apparatus to control sensing time for nonvolatile memory |
US11335426B2 (en) * | 2020-10-16 | 2022-05-17 | Micron Technology, Inc. | Targeted test fail injection |
Citations (3)
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US5163021A (en) * | 1989-04-13 | 1992-11-10 | Sundisk Corporation | Multi-state EEprom read and write circuits and techniques |
US5621687A (en) * | 1995-05-31 | 1997-04-15 | Intel Corporation | Programmable erasure and programming time for a flash memory |
US5751647A (en) * | 1995-02-13 | 1998-05-12 | Micron Technology, Inc. | On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same |
-
1999
- 1999-06-03 JP JP15585699A patent/JP4251717B2/en not_active Expired - Fee Related
-
2000
- 2000-05-26 US US09/578,915 patent/US6515905B2/en not_active Expired - Lifetime
- 2000-05-31 KR KR1020000029494A patent/KR100572166B1/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5163021A (en) * | 1989-04-13 | 1992-11-10 | Sundisk Corporation | Multi-state EEprom read and write circuits and techniques |
US5751647A (en) * | 1995-02-13 | 1998-05-12 | Micron Technology, Inc. | On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same |
US5621687A (en) * | 1995-05-31 | 1997-04-15 | Intel Corporation | Programmable erasure and programming time for a flash memory |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6781878B2 (en) * | 2002-08-12 | 2004-08-24 | Matrix Semiconductor, Inc. | Dynamic sub-array group selection scheme |
US20040218420A1 (en) * | 2003-04-29 | 2004-11-04 | Dialog Semiconductor Gmbh | Flash memory with pre-detection for data loss |
US6819589B1 (en) * | 2003-04-29 | 2004-11-16 | Dialog Semiconductor Gmbh | Flash memory with pre-detection for data loss |
US20050012868A1 (en) * | 2003-07-18 | 2005-01-20 | Samsung Electronics Co., Ltd. | Analog-to-digital converting apparatus for processing a plurality of analog input signals at high rate and display device using the same |
US20060012498A1 (en) * | 2003-07-18 | 2006-01-19 | Samsung Electronics Co., Ltd. | Analog-to-digital converting apparatus for processing a plurality of analog input signals at high rate and display device using the same |
US7026969B2 (en) * | 2003-07-18 | 2006-04-11 | Samsung Electronics Co., Ltd. | Analog-to-digital converting apparatus for processing a plurality of analog input signals at high rate and display device using the same |
US7030796B2 (en) * | 2003-07-18 | 2006-04-18 | Samsung Electronics Co., Ltd. | Analog-to-digital converting apparatus for processing a plurality of analog input signals at high rate and display device using the same |
US20060181955A1 (en) * | 2005-02-16 | 2006-08-17 | Renesas Technology Corp. | Semiconductor integrated circuit device |
US7423909B2 (en) * | 2005-02-16 | 2008-09-09 | Renesas Technology Corp. | Semiconductor integrated circuit device |
US20080279033A1 (en) * | 2005-02-16 | 2008-11-13 | Masao Shinozaki | Semiconductor integrated circuit device |
US20150294736A1 (en) * | 2014-04-15 | 2015-10-15 | SK Hynix Inc. | Semiconductor device, semiconductor memory device and memory system |
US9362004B2 (en) * | 2014-04-15 | 2016-06-07 | SK Hynix Inc. | Semiconductor device, semiconductor memory device and memory system |
TWI633546B (en) * | 2014-04-15 | 2018-08-21 | 愛思開海力士有限公司 | Semiconductor device, semiconductor memory device and memory system |
Also Published As
Publication number | Publication date |
---|---|
JP2000348500A (en) | 2000-12-15 |
KR20010069201A (en) | 2001-07-23 |
US20010048609A1 (en) | 2001-12-06 |
KR100572166B1 (en) | 2006-04-19 |
JP4251717B2 (en) | 2009-04-08 |
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