US6507917B1 - Data memory - Google Patents
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- US6507917B1 US6507917B1 US09/444,553 US44455399A US6507917B1 US 6507917 B1 US6507917 B1 US 6507917B1 US 44455399 A US44455399 A US 44455399A US 6507917 B1 US6507917 B1 US 6507917B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/835—Masking faults in memories by using spares or by reconfiguring using programmable devices with roll call arrangements for redundant substitutions
Definitions
- the present invention relates generally to a data memory, and more particularly to a data memory with a RAM or ROM that includes a redundancy circuit.
- Data memories such as those that can include a random access memory (RAM) or read only memory (ROM) are currently prevalent in many types of electronic devices. Increasingly, it is desirable to increase the capacity and/or degree of integration in such data memories.
- RAM random access memory
- ROM read only memory
- data memories continue to increase in size, it can be difficult to fabricate high capacity, high integration data memories that are always defect free.
- data memories typically include one or more spare memory cells.
- Data memories can often be fabricated as integrated circuits in a substrate material, such as a semiconductor.
- a data memory may be one of many “dies” in a “wafer.” A die may be subsequently “packaged.”
- Data memories are typically tested, prior to packaging, for defective memory cells. In the event a defective memory cell is detected, the defective memory cell may be replaced by a spare memory cell.
- address data of the defective memory cell can be set to the address data of a spare memory cell. In this way, if a data memory has one or more defective memory cells, it can still be used by replacing such defective memory cells with spare memory cells.
- a laser may open selected fusible links to thereby redirect a defective memory cell address to a spare memory cell. In other words, a laser can “set” address data for a defective memory cell.
- a data memory in die form is typically packaged.
- One of the many types of packages is an epoxy resin package. Once placed in an epoxy resin package, it is usually no longer possible to observe the programmed redundancy information.
- One way to determine if an access is to a normal memory cell or a spare memory is to utilize a “roll call” circuit.
- One particular type of roll call circuit can provide a predetermined output when an address results in the activation of a redundancy circuit (such as one that may include fusible links).
- a predetermined roll call output can be provided externally to the data memory package.
- FIG. 5 is a schematic top view illustrating the internal layout of a data memory in the form of a memory “chip”.
- FIG. 6 is a block diagram of a conventional redundancy circuit and result output circuit.
- a memory chip is designated by the general reference character 500 , and is shown to include memory circuits 502 .
- memory circuits 502 there are four memory circuits 502 formed in a body substrate 504 .
- the memory circuits 502 and body substrate 504 can have a rectangular shape.
- the four memory circuits 502 are arranged into two rows and two columns.
- Memory circuits 502 can include a number of normal memory cells, at least one spare memory cell, and a row/column decoder (all not illustrated). Normal memory cells may be accessed according to predetermined address data. A spare memory cell is normally not used. A row/column decoder can decode address data to select a particular memory cell or cells.
- the memory chip 500 may also include a number of external connection terminals connected to address input circuits (not illustrated). Address data can be applied to the memory chip 500 by way of such external connection terminals.
- address data When address data is input to the memory chip 500 , such address data can be decoded by row/column decoders and one or more normal memory cells can be accessed. In the case of a write operation, write data on external connection terminals can be written into the accessed normal memory cells. In the case of a read operation, read data can be provided on external connection terminals.
- address data can access normal memory cells in the memory circuits 502 .
- the memory chip 500 can be set so that particular address data accesses one or more spare memory cells. In particular, prior to any testing, no spare memory cells can be accessed by an address. However, if the memory chip is inspected and a defective normal memory cell is detected, the memory chip 500 can be set so that the address of the defective normal memory cell accesses a spare memory cell.
- the memory chip 500 is shown to further include six redundancy circuits 506 - a to 506 - f situated between the memory circuits 502 .
- Redundancy circuits 506 - a to 506 - d can be row redundancy circuits.
- One row redundancy circuit ( 506 - a to 506 - d ) can be connected to each memory circuit 502 .
- Redundancy circuits 506 - e to 506 - f can be column redundancy circuits.
- One column redundancy circuit ( 506 - e to 506 - f ) can be connected to two memory circuits 502 .
- Redundancy circuits can include fuse include fusible links and an address comparison circuit, or the like.
- a fuse circuit can thus provide address changing functions and signal generating functions.
- a fuse circuit may particularly include a fuse ROM. Address data within the fuse ROM may be set by laser cutting to the address of a defective normal memory cell.
- An address comparison circuit can compare address data received by external connection terminals. When the received address data corresponds to an address programmed into a fuse ROM, the access destination is changed from a normal memory cell to a spare memory cell. In addition, an address comparison circuit can further output a redundancy signal that indicates a spare memory cell access has taken place. Such a redundancy signal may be provided on one or more external connection terminals as a roll call signal.
- a memory chip 500 can also include a result decision circuit 508 and result output circuit 510 .
- the result decision circuit 508 and result output circuit 510 can include logic OR gates.
- the result decision circuit 508 is situated centrally with respect to the memory circuits 502 and redundancy circuits ( 506 - a to 506 - f ) to minimize connection wiring 512 to the redundancy circuits ( 506 - a to 506 - f ).
- FIG. 6 shows how six redundancy circuits ( 506 - a to 506 - f ) can be connected to a result decision circuit 508 and result output circuit 510 .
- six redundancy circuits ( 506 - a to 506 - f ) can be connected to one result decision circuit 508 by six signal wirings 512 .
- the result decision circuit 508 can be connected to result output circuit 510 by signal wiring 514 .
- the result decision circuit 508 can determine if the access is to a normal memory cell or a spare memory cell. This determination can be provided to the result output circuit 510 .
- the result output circuit 510 can provide the determination on one or more external connection terminals. Such a determination can be a “roll call” signal.
- circuits ( 502 , 506 - a to 506 - f , 508 and 510 ) and wirings ( 512 and 514 ) can be formed by various film layers formed on the body substrate 504 .
- Such circuits and wirings, as well as other portions of the memory chip 500 can be sealed in an epoxy resin when the memory chip 500 is packaged.
- External connection terminals can have ends that extend out of the epoxy resin package.
- a memory chip 500 such as that shown in FIG. 5 may execute data write operations and data read operations that access memory circuits 502 . If the memory access is to a defective memory cell, a data write or data read operation can access a spare memory cell.
- address data can be received on particular external connection terminals.
- the address information can then be decoded by row/column decoders in the memory circuits 502 .
- a corresponding normal memory cell can then be accessed.
- address data can be compared with address data set in a fuse ROM of the redundancy circuits. Such a comparison can occur prior to decoding by the row/column decoders of the memory circuits 502 .
- a spare memory cell is accessed.
- the entire memory chip 500 does not have to be discarded because such defective normal memory cells can be replaced by spare memory cells. In this way the overall yield of such memory chips 500 can be increased.
- defects can be detected and address data can be set within redundancy circuits ( 506 - a to 506 - f ) prior to a memory chip 50 being packaged. However, defects may still be detected after the memory chip 500 is packaged.
- a roll call function can be performed on a completed memory chip 500 .
- a roll call function can include performing a memory access with address data while monitoring a roll call signal. The roll call signal will be activated when an address accesses a redundancy circuit ( 506 - a to 506 - f ).
- one of the redundancy circuits can output an active redundancy signal (low for example).
- the active redundancy signal indicates access to a spare memory cell.
- a result decision circuit 508 can detect an active redundancy signal and provide this information to the result output circuit 510 , which can provide the information as output roll call data.
- FIGS. 5 and 6 can make it possible to determine for each address, whether the address accesses a normal memory cell or a spare memory cell within a memory circuit 502 . Further, when a defect occurs in a packaged memory chip, it can be possible to determine if the defect occurs in an access to a normal memory cell or a spare memory cell.
- the result decision circuit 508 can include a NAND gate.
- a NAND gate is essentially the equivalent of a “negative” logic OR gate. That is, when an address corresponds to a replaced normal memory cell, a redundancy circuit ( 506 - a to 506 - f ) is accessed. As a result, one of the redundancy signals RED 1 to RED 6 can transition from an inactive level to an active level (high to low, for example). The NAND gate can output an active internal roll call signal (high, in this case).
- the internal roll call signal can be received by a result output circuit 510 .
- the result output circuit 510 can activate (drive high in this case) an external roll call signal on an external connection terminal.
- a single external connection terminal can be included for providing an external roll call signal, because all the redundancy circuits ( 506 - a to 506 - f ) can be connected to a single result decision circuit 508 (which can include OR-like gates arranged in common).
- a number of signal wirings 512 are connected to a centrally located result decision circuit 508 .
- Such a wiring arrangement, and position of a result decision circuit 508 can require a predetermined amount of area and/or introduce line routing constraints into the wiring patterns of the memory chip 500 . Such area and routing constraints can make it difficult to reduce the size of the memory chip 500 .
- a smaller memory chip 500 can be less expensive to produce and/or operate faster and/or consume less power and/or operate at a lower voltage.
- FIG. 7 is a schematic top view illustrating the internal layout of a data memory in the form of a memory chip.
- the memory chip is designated by the general reference character 700 , and can include some of the same, or similar, general constituents as the memory chip of FIG. 5 . To that extent, like constituents will be referred to by the same reference character, but with the first reference number being a “7” instead of a “5.”
- a result decision circuit (such as 508 ) and a decision output circuit (such as 510 ) can be integrated to form a decision and output circuit 716 .
- a decision and output circuit 716 may be situated on the outer margin of the memory chip 700 . Redundancy circuits 706 - a to 706 - f can be connected to the decision and output circuit 716 by signal wiring 718 .
- the memory chip 700 arrangement of FIG. 7 does not have to include a centrally situated result decision circuit. Further, by using a decision and output circuit 716 , the memory chip 700 does not have to include a wiring between a result decision circuit and a decision output circuit. However, the memory chip 700 does include signal wirings 718 . Such wirings 718 can introduce the area and routing constraints mentioned in conjunction with FIG. 5 .
- the official gazette of Japanese Patent Laid-Open No. 47196/1993 discloses a data memory that can address the drawbacks of the embodiment of FIG. 7 .
- the above-mentioned laid-open publication shows a data memory having redundancy circuits that are connected to a decision and output circuit by a single wiring.
- FIG. 8 is a schematic top view illustrating the internal layout of a data memory in the form of a memory chip 800 .
- FIG. 9 is a block diagram illustrating redundancy circuits and a decision and output circuit.
- FIG. 10 is a timing diagram illustrating various signals that may be used in the circuits of FIG. 9 .
- the memory chip 800 can include some of the same, or similar, general constituents as the memory chip of FIG. 7 . To that extent, like constituents will be referred to by the same reference character, but with the first reference number being an “8” instead of a “7.”
- the memory chip 800 has a single signal wiring 820 connected to one decision and output circuit 816 .
- the decision and output circuit 816 is situated at the outer margin of the memory chip 800 .
- a number of redundancy circuits 806 - a to 806 - f can be connected to the single signal wiring 820 by a number of branch wirings 822 - a to 822 - f .
- redundancy circuits 900 - a to 900 - f can include a p-type transistor 902 .
- a p-type transistor can be a metal-oxide-semiconductor field effect transistor (MOSFET).
- MOSFET metal-oxide-semiconductor field effect transistor
- p-type channel transistors are distinguished from n-type transistors by presence or absence of a “circle.”
- Each p-type transistor 902 may include an input terminal 904 that can receive a redundancy signal RED 1 to RED 6 .
- Each p-type transistor 902 can include a gate coupled to an input terminal 904 , a source coupled to a power supply node 906 , and a drain coupled to a signal wiring 908 .
- a decision and output circuit 910 can include a result decision circuit 912 in series with result output circuit 914 .
- a roll call signal from the result decision circuit 912 can be output by result output circuit 914 on an external connection.
- the result decision circuit 912 can receive an output permit signal ROLLEN, and the result output circuit 914 can buffer a roll call signal from the result decision circuit 912 .
- the particular example of a result decision circuit 912 set forth in FIG. 9 can include a p-type transistor 916 and an n-type transistor 918 .
- the output permit signal ROLLEN which can also be conceptualized as a “roll call entry signal,” can be received on an external roll call terminal 920 .
- the external roll call terminal 920 can be coupled to the gates of transistors 916 and 918 .
- the source and drain of p-type transistor 916 can be connected to a power supply node 906 and signal wiring 908 , respectively.
- the source and drain of n-type transistor 918 can be connected to a ground node 922 and signal wiring 908 , respectively.
- N-type transistor 918 can function as a “pull-down” device in a “wired-OR” circuit.
- the transistor channel widths of p-type transistors 902 can be larger than the transistor channel width of n-type transistor 918 .
- FIGS. 8 and 9 can include one signal wiring ( 820 or 908 ) connected to a single decision and output circuit ( 816 or 910 ), and to branch wirings ( 822 - a to 822 - f ) that function as portions of a wired-OR type circuit.
- the roll call entry signal ROLLEN in a “normal” mode, can be maintained at an inactive level (low, in this case).
- P-type transistor 916 can be turned on and n-type transistor 918 can be turned off.
- the potential of the single signal wiring 908 shown as REDOR, can be maintained at an inactive level (high, in case).
- the roll call entry signal ROLLEN is activated (driven high in this case).
- P-type transistor 916 can be turned off and n-type transistor 918 can be turned on. With n-type transistor 918 turned on, signal wiring 908 can be initially connected to a ground potential.
- address information can be applied to a memory chip 800 . If an applied address accesses a normal memory cell, redundancy signals RED 1 to RED 6 will be inactive (high, in this case). The p-type transistors 902 will remain off, and signal wiring 908 can remain at the ground potential.
- one of the redundancy signals RED 1 to RED 6 can be activated (driven low, in this case).
- One of the p-type transistors 902 can be turned on.
- the turned on p-type transistor 902 can have greater current driving capacity than n-type transistor 918 , and signal wiring 908 can be driven to a high potential.
- the high potential can be detected by the decision and output circuit 910 .
- the conventional approaches illustrated in FIGS. 8 and 9 can include one signal wiring ( 820 or 908 ) that is spread across a memory chip 800 . Further, because branch wirings ( 822 - a to 822 - f ) are not necessarily parallel to the signal wiring, it can be possible to reduce the size of the memory chip 800 over other approaches. Still further, because a number of redundancy circuits ( 806 - a to 806 - f ) are connected to a signal wiring ( 820 or 908 ) in a wired-OR arrangement, the resulting structure can be simpler than other conventional approaches. Such simplicity can make manufacturing and/or design easier.
- Vcc can be a power supply voltage
- R ONN can be the “on” resistance of n-type transistor 918
- R can be the wiring resistance of signal wiring 908
- R ONP can be the on resistance of a p-type transistor 902 .
- the wiring resistance R can be a resistance value between an activated redundancy circuit 900 - a to 900 - f and the result decision circuit 912 .
- the inherent resistance of signal wiring 908 is shown in portions as R 1 , R 2 , R 3 . . . to R 6 .
- the wiring resistance would be R 2 +R 3 +R 4 +R 5 +R 6 .
- the wiring resistance would be R 6 .
- the wiring resistance R of signal wiring 908 can vary according to which redundancy circuit 900 - a to 900 - f is activated. Accordingly, when a redundancy circuit is situated at a relatively far distance from a result decision circuit 912 , the wiring resistance R is higher, and the resulting signal wiring 908 potential REDOR is lower.
- a drawback to the arrangement of FIG. 9 is that if a redundancy circuit ( 900 - a to 900 - f ) is activated, the signal wiring 908 potential REDOR should ideally rise to a predetermined potential.
- the result output circuit 914 could detect this rise, and provide a high output signal.
- the REDOR potential may not rise to a sufficiently high potential, and the result output circuit 914 can erroneously output a low output value.
- the result output circuit 914 can be considered a “level” detect circuit. If it assumed the level detect circuit has a threshold of 0.5 Vcc, the resulting wiring resistance R of signal wiring 908 should meet the condition R ⁇ (R ONN ⁇ R ONP ).
- Resistance can be reduced by moving a result decision circuit 912 closer to the redundancy circuits ( 900 - a to 900 - f ).
- the width of signal wiring 908 can be increased. While such approaches can reduce the possibility of an erroneous result output circuit 914 output, such approaches can introduce layout constraints into a memory chip.
- FIG. 10 shows four waveforms, including the roll call entry signal ROLLEN, one redundancy signal RED 4 , another redundancy signal RED 1 , and the resulting potential of a signal wiring REDOR.
- the result decision circuit 912 can be enabled. This can force the REDOR potential low.
- the redundancy signal RED 4 is activated, causing the REDOR potential to be driven high. Because the redundancy circuit 900 - d that receives the RED 4 signal is closer to the result decision circuit 912 , the wiring resistance R is relatively small, and the REDOR can rise to a relatively high potential. The RED 4 can return high, resulting in the REDOR signal being driven low again.
- the redundancy signal RED 1 is activated, causing the REDOR potential to be driven high again. Because the redundancy circuit 900 - a that receives the RED 1 signal is further from the result decision circuit 912 , the wiring resistance R is relatively high, and the REDOR can rise to a lower potential than the RED 4 case.
- FIG. 11 is a fourth example of a conventional data memory in the form of redundancy circuits and a decision and output circuit.
- FIG. 12 is a timing diagram illustrating the operation of the circuits in FIG. 11 .
- FIG. 11 includes many of the same, or similar, general constituents as FIG. 9 . To that extent, like constituents will be referred to by the same reference character, but with the first reference number being an “11” instead of a “10.”
- the arrangement of FIG. 11 includes a roll call decision circuit 1124 that includes a p-type transistor 1116 and an n-type transistor 1118 .
- the roll call decision circuit 1124 can receive a one-shot signal ROLLC at an external one-shot terminal 1126 in addition to a roll call entry signal ROLLEN at an external roll call terminal 1120 .
- the one-shot signal ROLLC is applied to the gate of n-type transistor 1118 , while the roll call entry signal ROLLEN can be applied to the gate of p-type transistor 1116 .
- a roll call entry signal ROLLEN can be inactive (low in this case) and the one-shot signal ROLLC can be inactive (maintained low in this example).
- P-type transistor 1116 can be turned on, and n-type transistor 1118 can be turned off.
- the signal wiring 1108 potential REDOR can thus be at a high potential.
- a normal mode is shown at time tO in FIG. 12 .
- the roll call entry signal ROLLEN is activated (driven high in this case). Further, the one-shot signal ROLLC can transition high and then return low. With the ROLLEN signal high, p-type transistor 1116 can be turned off. When the ROLLC signal pulses high, n-type transistor 1118 can turn on, pulling the REDOR potential to a low level. The REDOR potential may then change, depending upon whether a normal memory cell or a spare memory cell is accessed.
- the redundancy signals RED 1 to RED 6 can remain inactive (high).
- P-type transistors 1102 within the redundancy circuits ( 1100 - a to 1100 - f ) will remain turned off. Because n-type transistor 1118 was initially turned on by the ROLLC signal, when the ROLLC signal returns low, the signal wiring 1108 potential REDOR will remain at a low level.
- An example of a roll call operation to a normal memory is shown to begin at time t 3 in FIG. 12 .
- one of the redundancy signals RED 1 to RED 6 can be activated (transition low) turning on a p-type transistor 1102 within one of the redundancy circuits ( 1100 - a to 1100 - f ).
- Signal wiring 1108 can be connected to a power supply node 1106 . While n-type transistor 1118 is initially turned on by the ROLLC signal, when the ROLLC signal returns low, n-type transistor 1118 can be turned off.
- n-type transistor 1118 turned off and a p-type transistor 1102 turned on, the potential of signal wiring 1108 can rise to a relatively high potential.
- FIG. 12 One skilled in the art would recognize that two roll call operations to spare memory cells are illustrated in FIG. 12 .
- the first such operation begins at time t 1 and represents the activation of a p-type transistor 1102 in response to the RED 4 signal. Because the p-type transistor 1102 that is turned on is in relative close proximity to roll call decision circuit 1124 , wiring resistance can be relatively small.
- the second such operation begins at time t 2 and represents the activation of a p-type transistor 1102 in response to the RED 1 signal. Because the p-type transistor 1102 that is turned on is relatively far from roll call decision circuit 1124 , wiring resistance can be relatively high. However, because n-type transistor 1118 is turned off, the REDOR potential can rise to higher level than the conventional approach illustrated in FIG. 9 .
- the signal wiring 1108 potential REDOR can be driven to a high level in accordance with redundancy signals RED 1 to RED 6 essentially independently of the channel width sizes of p-type transistors 1102 and n-type transistor 1118 . This can make the output of the roll call decision circuit 1124 more accurate than other conventional wired-OR approaches.
- redundancy circuits ( 1100 - a to 1100 - f ) can be situated at further distances from a roll call decision circuit 1124 .
- the width of signal wiring 1108 does not have to be increased to reduce wiring resistance.
- a memory chip can have fewer layout restrictions.
- FIGS. 11 and 12 can have drawbacks however.
- signal wiring 1108 can float, and thus be susceptible to noise that can generate an erroneous signal.
- a redundancy signal such as RED 1 to RED 6
- n-type transistor 1118 is turned off
- signal wiring 1108 can float. This is shown in FIG. 12 by time period 1200 .
- signal wiring 1108 can be floating while n-type transistor 1118 is turned off. This is shown in FIG. 12 by time period 1202 .
- an inspection unit in order to inspect a data memory according to the above-described example, an inspection unit must include a control circuit dedicated to generating a one-shot signal that can be applied to an external one-shot terminal 1126 . Further, the data memory would have to provide a dedicated external connection for the external one-shot terminal 1126 . Such requirements can make inspection units complicated, and prevent the further reductions in the size of a data memory and/or an inspection unit.
- a data memory can include one or more memory circuits, a number of redundancy circuits, and a decision and output circuit.
- a memory circuit can include a plurality of normal memory cells that store data and can be accessed by predetermined addresses, at least one spare memory cell, and access circuits that can access normal memory cells according to address data.
- data can be stored in binary form. Further, according to various embodiments, data may be read and/or written and/or programmed and/or erased in the memory cells.
- a redundancy circuit may include an address setting circuit, an access changing circuit, and a signal generating circuit.
- the address of a normal memory cell may be set within the address setting circuit to access a spare memory cell according to the set address.
- the access changing circuit can change the access destination from a normal memory cell to a spare memory cell when an externally applied address coincides with the address set in the address setting circuit.
- the signal generating circuit can activate a redundancy signal when the access changing circuit is activated.
- a decision and output circuit can detect a redundancy signal and output it on an external connection terminal.
- the various signal generating circuits can be connected to the decision and output circuit by logic circuits arranged in series.
- Each logic circuit can include an active device that can buffer a redundancy signal to a predetermined potential.
- logic circuits may have an OR-type function.
- addresses can correspond to each normal memory cell in a memory circuit.
- access circuits can access corresponding normal memory cells.
- data can then be read from or written into the accessed normal memory cell.
- the addresses of a defective normal memory cell can be set within the address setting circuit of a redundancy circuit. Then, if an externally applied address coincides with an address set within a redundancy circuit, the access destination is changed from the defective normal memory cell to a spare memory cell. Thus, even if the data memory includes a defective normal memory cell, a memory access may still be performed, but to a spare memory cell. In this way it is not necessary to dispose of a whole data memory when only a few normal memory cells are defective.
- signal generating circuits within the redundancy circuits can generate a redundancy signal when their respective access changing circuit is activated. Such a redundancy signal can be detected by a decision and output circuit and output on an external connection terminal. This can make it possible to determine if the access destination of an applied address is a normal memory cell or a spare memory cell during a data memory inspection. Because the signal generating circuits are successively connected to the decision and output circuit by a series of logic circuits, a redundancy signal generated by any of the redundancy circuits can be detected by the decision and output circuit.
- each logic circuit can include an active device, each such logic circuit can buffer a received redundancy signal to a predetermined potential. Therefore, redundancy signals that are input to the decision and output circuit can be of the predetermined potential, regardless of the distance between the decision and output circuit and the redundancy circuit that generates the redundancy signal.
- a data memory can include redundancy circuits with signal generating circuits.
- the signal generating circuits can be successively connected to a decision and output circuit by logic circuits arranged in series.
- Each logic circuit can include output buffer circuits that can buffer a received redundancy signal to at least a predetermined potential.
- logic circuits may be OR-type circuits.
- a redundancy signal generated by a redundancy circuit can be transferred up to a decision and output circuit through logic circuits.
- the output circuit of each logic circuit can buffer the redundancy circuit to the predetermined potential.
- a buffered redundancy signal can be input to a decision and output circuit at the predetermined potential independent of the distance between the decision and output circuit and the redundancy circuit that generates the redundancy signal.
- a data memory can include a number of redundancy circuits.
- the redundancy circuits can include signal generating circuits that are successively connected to a decision and output circuit by logic circuits arranged in series.
- Each logic circuit includes output circuits that can buffer a received redundancy signal to a predetermined potential.
- logic circuits may be OR-type circuits.
- a redundancy signal generated by a redundancy circuit can be transferred up to a decision and output circuit through logic circuits.
- the output circuit of each logic circuit can buffer the redundancy circuit to the predetermined potential.
- a buffered redundancy signal can be input to a decision and output circuit at the predetermined potential independent of the distance between the decision and output circuit and the redundancy circuit that generates the redundancy signal.
- the logic circuits of the above-described data memory may further include input switching circuits.
- Input switching circuits can selectively switch input signals into a logic circuit.
- one or more redundancy signals can be switched into a logic circuit and applied to a decision and output circuit.
- non-redundancy signals can be switched into a logic circuit and applied to the decision and output circuit.
- input switching circuits can include an active element for buffering a selected input signal to at least a predetermined potential. In this case, because the selected signal is buffered to the predetermined potential, the input to the decision and output circuit can be at the predetermined potential.
- logic circuits can provide an OR-type function, and include a NAND gate and an inverter.
- logic circuits and/or decision and output circuit are operated according to “negative” logic, such a redundancy signal can be provided to the decision and output circuit.
- FIG. 1 shows a data memory according to one embodiment.
- FIG. 2 is block diagram illustrating redundancy circuits, a decision and output circuit, and other circuits that may be used in the embodiment of FIG. 1 .
- FIG. 3 is a block diagram of a redundancy circuit that may be used in an embodiment.
- FIG. 4 is a block diagram of input switching according to one embodiment.
- FIG. 5 shows a first example of a conventional data memory.
- FIG. 6 shows conventional redundancy circuits and a result output circuit.
- FIG. 7 is a second example of a conventional data memory.
- FIG. 8 is a third example of a conventional data memory.
- FIG. 9 is a block diagram of conventional redundancy circuits and a decision and output circuit.
- FIG. 10 is a timing diagram of signals that may be used in the circuits of FIG. 9 .
- FIG. 11 is another block diagram of conventional redundancy circuits and a decision and output circuit.
- FIG. 12 is a timing diagram of signals that may be used in the circuits of FIG. 11 .
- FIGS. 1 to 4 One embodiment of the present invention will now be described in conjunction with FIGS. 1 to 4 .
- the described embodiment can include some, or similar constituents to the conventional example set forth in FIG. 8 . To that extent, like constituents will be referred to by the same reference character, but with the first digit being a “1” instead of an “8.”
- FIG. 1 is a schematic top view illustrating the internal layout of a data memory in the form of a memory chip 100 .
- FIG. 2 is block diagram illustrating redundancy circuits, a decision and output circuit, as well as other circuits according to one embodiment.
- FIG. 3 is a block diagram of a fuse circuit according to a particular embodiment.
- a memory chip 100 can include a number of memory circuits 102 formed in a body substrate 104 .
- the memory chip 100 includes four memory circuits 102 arranged in two rows and two columns.
- Memory circuits 102 and a body substrate 104 can have rectangular shapes.
- a memory chip 100 may also include redundancy circuits ( 106 - a to 106 - f ).
- the particular embodiment of FIG. 1 includes six redundancy circuits ( 106 - a to 106 - f ).
- a memory chip 100 may also include a decision and output circuit 124 that is situated on an outer margin of the memory chip 100 .
- the embodiment of FIG. 1 can include redundancy circuits 106 - a to 106 - f that are connected to a single decision and output circuit 124 by a number of logic circuits 126 - 1 to 126 - 4 and output wirings 128 .
- Redundancy circuits are shown as items 200 - a to 200 - f .
- Decision and output circuit is shown as item 202 .
- Logic circuits are shown as item 204 - 1 to 204 - 4 , and output wirings are shown as items 206 .
- Logic circuits may each include a NAND gate 208 and an inverter 210 .
- a NAND gate 208 and/or inverter 210 can buffer received input signals.
- NAND gate 208 and inverter 210 can be supplied with power from a connection that is common to a closest redundancy circuit ( 200 - a to 200 - f ).
- NAND gate 208 in conjunction with inverter 210 can provide a “negative” OR type function. Accordingly, logic circuits ( 204 - 1 to 204 - 4 ) can be conceptualized as “OR” type circuits.
- each logic circuit can have a power supply wiring connection that is common to a closely situated redundancy circuit ( 200 - a to 200 - f ).
- the output signal of a logic circuit situated remotely from decision and output circuit 202 such as 204 - d
- the output signal of a logic circuit situated remotely from decision and output circuit 202 can have an output signal driven by a power supply node that is also remote with respect to decision and output circuit 202 .
- a remotely generated signal can be buffered by intervening logic circuits until it can be driven by a logic circuit (such as 204 - a ) having a power supply node that is situated relatively close to the decision and output circuit 202 .
- a redundancy circuit 300 may include a number of fuse circuits 302 - a to 302 - c . As shown by fuse circuit 302 - a , each fuse circuit ( 302 - a to 302 - c ) may include an address comparison circuit 304 and a fuse read only memory (ROM) 306 . An address comparison circuit 304 can change the access of a data memory from an access to a normal memory cell to an access of a spare memory cell. A fuse ROM may be used to set the address of a defective normal memory cell. A redundancy circuit 300 may also include a NOR gate 308 that can generate a redundancy signal REDn.
- the address data corresponding to a defective normal memory cell can be set within a fuse ROM 306 by laser cutting or the like. The set address will thus designate access to a particular spare memory cell. Address information can then be applied to an address comparison circuit 304 . Address comparison circuit 304 can compare the applied address information to the information set within its corresponding fuse ROM 306 . If the address data does not coincide, address comparison circuit 304 can maintain an inactive (low in this case) output signal level. However, if the address data coincides, address comparison circuit 304 can provide an active output signal (high in this case).
- the outputs of the fuse circuits ( 302 - a to 302 - c ) can be provided to a memory circuit (such as 102 ). Such an arrangement can enable an applied address to access a spare memory cell instead of a normal memory cell. Further, because the outputs of the fuse circuits ( 302 - a to 302 - c ) are provided to NOR gate 308 , in the event any of the outputs transitions high, the output of NOR gate 308 REDn will go low.
- a decision and output circuit 202 can include a result decision circuit 212 and a result output circuit 214 arranged in series with one another.
- the result decision circuit 212 can include an inverter, or the like, that can make the output of the decision circuit 212 have logic levels that correspond to conventional approaches.
- the result output circuit 214 can receive the output of result decision circuit 212 .
- the result output circuit 214 can receive a roll call entry signal ROLLEN from an external roll call terminal 216 .
- the result output circuit 214 can provide a roll call signal.
- redundancy circuits may be arranged between two columns and two rows of memory circuits 102 .
- a logic circuit 126 - 3 situated at the common corners of the memory circuits 102 can have three inputs.
- Redundancy circuits 106 - e and 106 - f and logic circuit 126 - 4 can be coupled to the three inputs of logic circuit 126 - 3 from three different directions.
- one of a number of redundancy circuits can activate a redundancy signal during a roll call operation. Such a redundancy signal can then be buffered through a series of logic circuits ( 126 - 1 to 126 - 4 ).
- each logic circuit ( 126 - 1 to 126 - 4 ) does not necessarily form a portion of a wired-OR type circuit, but instead can include active devices coupled to power supply nodes.
- a redundancy signal is buffered whenever it is logically combined (ORed in this case) in a logic circuit ( 126 - 1 to 126 - 4 ).
- an arrangement such as that set forth in FIGS. 1 and/or 2 can include redundancy circuits ( 106 - a to 106 - f ) that can activate a redundancy signal.
- the active redundancy signal can result in an input signal to a decision and output circuit 124 .
- the potential of an input signal to the decision and output circuit 124 does not vary according to the distance between the activated redundancy circuit ( 106 - a to 106 - f ) and the decision and output circuit 124 . In this way, the described embodiments may more accurately detect redundancy signals.
- a memory chip 100 may be reduced in area as it does not include a number of signal wirings arranged in parallel.
- signal routing may also be simplified by such an arrangement.
- such a memory chip 100 may accurately detect redundancy signals regardless of the distance between a redundancy circuit ( 106 - a to 106 - f ) and a decision and output circuit 124 .
- a single wiring does not have to have a certain width to assure a low enough resistance.
- the described embodiments illustrate a data memory that may accurately execute roll call operations with a relatively simple structure.
- the described embodiments include logic circuits ( 126 - 1 to 126 - 4 and 204 - 1 to 204 - 4 ) that can include described embodiments may be greater than the conventional memory chip 800 of FIG. 8 . However, such an increase in area is slight compared to approaches that lay multiple signal wirings in parallel.
- the above described embodiments illustrate a case where redundancy signals (RED 1 to RED 6 ) generated by redundancy circuits ( 106 - a to 106 - f ) are transmitted to a decision and output circuit ( 124 or 202 ) by a number of logic circuits ( 126 - 1 to 126 - 4 and 204 - 1 to 204 - 4 ) connected in series.
- the number of input signals to a logic circuit may be increased.
- the series of logic circuits ( 126 - 1 to 126 - 4 and 204 - 1 to 204 - 4 ) can buffer signals other than redundancy signals.
- FIG. 4 illustrates one of the many possible variations in a logic circuit.
- the logic circuit is designated by the general reference character 400 and can include a number of input switching circuits 402 - 1 to 402 - 4 .
- Input switching circuits ( 402 - 1 to 402 - 4 ) in one particular arrangement can include OR gates.
- Selected input switching circuits 402 - 1 and 402 - 2 can receive redundancy signals REDn and REDn ⁇ 1.
- those input switching circuits ( 402 - 1 and 402 - 2 ) that receive redundancy signals can be commonly enabled by a roll call enable signal ROLLEN (in this case active low).
- ROLLEN in this case active low
- Other input switching circuits can receive other input signals, such as test signals (TEST 2 and TEST 3 ) aw well as other predetermined enable signals (TEST 2 EN and TEST 3 EN) (also active low).
- test signals TEST 2 and TEST 3
- predetermined enable signals TEST 2 EN and TEST 3 EN
- test signals can thus be output on an external connection terminal.
- various test signals may be transferred up to a decision and output circuit ( 124 or 202 ) without unduly increasing the number of signal wirings and/or the number of external connection terminals for providing test results.
- logic circuits ( 126 - 1 to 126 - 4 and 204 - 1 to 204 - 4 ) should not be construed as limiting to the present invention.
- an embodiment could include a number of redundancy circuits connected to one signal wiring in a wired-OR type fashion.
- the signal wiring could be connected to a decision and output circuit at one end and to a buffer circuit, such as a logic circuit ( 126 - 1 to 126 - 4 and 204 - 1 to 204 - 4 ) at the other end.
- a data memory according the present invention may have a number of advantages over conventional approaches.
- a semiconductor memory can include redundancy circuits with access change circuits.
- redundancy circuits When access change circuits change an access from a normal memory cell to a spare memory cell, a redundancy signal can be generated.
- a decision and output circuit can detect the redundancy signal and provide the signal on an external connection terminal. In this way it can be possible to determine for specific address data whether an access destination is a normal memory cell or a spare memory cell.
- a number of redundancy circuits can be connected in series up to the decision and output circuit making it possible to detect the activation of any one of the redundancy circuits. Redundancy signals can be transferred to the decision and output circuit by a number of logic circuits in series.
- each logic circuit can include active devices that buffer a redundancy signal to predetermined potentials, it can be possible to apply an input signal to the decision and output circuit that does not vary according to the distance between a redundancy circuit and the decision and output circuit. This may enable more accurate roll call operations and/or allow for reductions in memory chip size, without introducing substantial layout restrictions and/or requiring a test device with particular timing control circuits.
- a semiconductor memory can include a number of redundancy circuits that generate redundancy signals.
- a redundancy signal can be transferred to a decision and output circuit through circuits providing an OR-type function.
- a redundancy signal can be buffered to at least a predetermined potential by output circuits in each OR-type circuit.
- an input signal can be provided to the decision and output circuit of at least the predetermined potential.
- This may allow for more accurate detection of a redundancy signal.
- Such detection can be independent of the distance between an activated redundancy circuit and the decision and output circuit. Further, such an arrangement can allow for reductions in memory chip size while not necessarily introducing substantial layout restrictions and/or requiring a test device with particular timing control circuits.
- Other embodiments can include logic circuits, such as those that provide OR-type functions, that include input switching circuits.
- Such input switching circuits can enable non-redundancy signals, such as test signals, to be applied to a decision and output circuit.
- non-redundancy signals that are buffered and/or of a predetermined potential can be provided to the decision and output circuit. This may allow for accurate detection of non-redundancy signals with a relatively simple structure.
- Embodiments that include input switching can include input switches with active devices. Such active devices can buffer input signals allowing a signal of a predetermined potential to be applied to a decision and output circuit.
- Embodiments that include logic circuits can include a NAND gate and an inverter. Thus, when redundancy circuits operate according to “negative” logic, such logic circuits can transfer a buffered redundancy signal to a decision and output circuit.
- DRAMs dynamic random access memories
- SRAMs static RAMs
- FRAMs ferroelectric RAMs
- ROMs read only memories
- PROMs programmable ROMs
- EPROMs electrically PROMs
- EEPROMs electrically erasable PROMs
- An integrated memory can be a memory formed in a larger integrated circuit.
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
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Abstract
Description
Claims (20)
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JP10-335837 | 1998-11-26 | ||
JP33583798A JP3219148B2 (en) | 1998-11-26 | 1998-11-26 | Data memory device |
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US6507917B1 true US6507917B1 (en) | 2003-01-14 |
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US09/444,553 Expired - Lifetime US6507917B1 (en) | 1998-11-26 | 1999-11-22 | Data memory |
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US11270310B2 (en) | 2017-07-31 | 2022-03-08 | Advanced New Technologies Co., Ltd. | Biometric feature database establishing method and apparatus |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5343429A (en) * | 1991-12-06 | 1994-08-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having redundant circuit and method of testing to see whether or not redundant circuit is used therein |
US5353253A (en) * | 1992-10-14 | 1994-10-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
US5416740A (en) * | 1991-12-12 | 1995-05-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device including redundant memory cell array for repairing defect |
US5625596A (en) * | 1994-09-09 | 1997-04-29 | Fujitsu Limited | Semiconductor memory device with improved operating speed |
US5859804A (en) * | 1991-10-16 | 1999-01-12 | International Business Machines Corporation | Method and apparatus for real time two dimensional redundancy allocation |
US5875194A (en) * | 1992-05-28 | 1999-02-23 | Texas Instruments Incorporated | Repairing efficiency by gray code |
US5983358A (en) * | 1996-09-27 | 1999-11-09 | Hitachi, Ltd. | Semiconductor memory having redundancy circuit |
US5983367A (en) * | 1996-10-29 | 1999-11-09 | Mitsubishi Denki Kabushiki Kaisha | Microprocessor having a CPU and at least two memory cell arrays on the same semiconductor chip, including a shared sense amplifier |
JP2000149590A (en) | 1998-11-10 | 2000-05-30 | Oki Micro Design Co Ltd | Semiconductor storage device |
-
1998
- 1998-11-26 JP JP33583798A patent/JP3219148B2/en not_active Expired - Fee Related
-
1999
- 1999-11-22 US US09/444,553 patent/US6507917B1/en not_active Expired - Lifetime
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5859804A (en) * | 1991-10-16 | 1999-01-12 | International Business Machines Corporation | Method and apparatus for real time two dimensional redundancy allocation |
US5343429A (en) * | 1991-12-06 | 1994-08-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having redundant circuit and method of testing to see whether or not redundant circuit is used therein |
US5416740A (en) * | 1991-12-12 | 1995-05-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device including redundant memory cell array for repairing defect |
US5875194A (en) * | 1992-05-28 | 1999-02-23 | Texas Instruments Incorporated | Repairing efficiency by gray code |
US5353253A (en) * | 1992-10-14 | 1994-10-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
US5625596A (en) * | 1994-09-09 | 1997-04-29 | Fujitsu Limited | Semiconductor memory device with improved operating speed |
US5983358A (en) * | 1996-09-27 | 1999-11-09 | Hitachi, Ltd. | Semiconductor memory having redundancy circuit |
US5983367A (en) * | 1996-10-29 | 1999-11-09 | Mitsubishi Denki Kabushiki Kaisha | Microprocessor having a CPU and at least two memory cell arrays on the same semiconductor chip, including a shared sense amplifier |
JP2000149590A (en) | 1998-11-10 | 2000-05-30 | Oki Micro Design Co Ltd | Semiconductor storage device |
Non-Patent Citations (1)
Title |
---|
Copy of Office Action from Japanese Patent Office for Counterpart Japanese Patent Application Translation of Japanese Examiner's Comments for above Japanese Office Action as concise explanation of relevance. |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11270310B2 (en) | 2017-07-31 | 2022-03-08 | Advanced New Technologies Co., Ltd. | Biometric feature database establishing method and apparatus |
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JP3219148B2 (en) | 2001-10-15 |
JP2000163987A (en) | 2000-06-16 |
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