US6351434B2 - Synchronous counter for electronic memories - Google Patents

Synchronous counter for electronic memories Download PDF

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Publication number
US6351434B2
US6351434B2 US09/767,762 US76776201A US6351434B2 US 6351434 B2 US6351434 B2 US 6351434B2 US 76776201 A US76776201 A US 76776201A US 6351434 B2 US6351434 B2 US 6351434B2
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Prior art keywords
counter
counter stages
stages
memory
circuit
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US09/767,762
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US20010014041A1 (en
Inventor
Luigi Pascucci
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STMicroelectronics SRL
Micron Technology Inc
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STMicroelectronics SRL
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Assigned to STMICROELECTRONICS S.R.L. reassignment STMICROELECTRONICS S.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PASCUCCI, LUIGI
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Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STMICROELECTRONICS S.R.L. (FORMERLY KNOWN AS SGS-THOMSON MICROELECTRONICS S.R.L.)
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Definitions

  • the present invention relates to the field of electronic circuits, and, more particularly, to a synchronous counter for electronic memories. Moreover, the invention relates to a fast synchronous counter for memories which is faster than conventional counters.
  • the structures that make up the memory are formed to ensure a normal read cycle.
  • This read cycle begins with a request stimulus (i.e., switching of the addressing lines) and ends with the extraction of the data related to the addressed memory location.
  • these conventional memories are capable of performing only one reading process at a time. Furthermore, each read cycle is identical to every other in terms of response of the memory. In order to be able to provide an efficient read cycle whose outcome is certain, it is necessary to allow the entire propagation of the read stimuli to evolve completely and always in the same manner to be able to extract the data from the memory.
  • the overall duration of a read cycle is given by the sum of elementary signal propagation times, and in particular: address transition request detection (signal ATD); identification of the memory location to be read (addressing); selection of the paths for access to the location to be read (word line, bit line); pre-charging of the data lines (PC); evaluation of the responses of the individual memory cells by a sense amplifier; and transfer of the read data to the output analysis time memories (buffer).
  • address transition request detection signal ATD
  • identification of the memory location to be read addressing
  • selection of the paths for access to the location to be read word line, bit line
  • PC pre-charging of the data lines
  • evaluation of the responses of the individual memory cells by a sense amplifier evaluation of the responses of the individual memory cells by a sense amplifier
  • the read times for each read cycle remain unchanged even if the new location to be read is adjacent to a location read in the directly preceding cycle. In this case it would be advantageous to be able to utilize the fact that the new read occurs in a position which is physically close to the preceding read position to provide increased read speed.
  • An object of the present invention is to provide a synchronous counter for electronic memories which may be used with memories of the interleaved type and thus may be synchronized with an external control signal for reading the memory.
  • Another object of the present invention is to provide a synchronous counter for electronic memories whose configuration may be defined substantially immediately from outside the counter at each count start.
  • Still another object of the present invention is to provide a synchronous counter for electronic memories which may be updated internally during counting.
  • Yet another object of the present invention is to provide a synchronous counter for electronic memories which is substantially functionally insensitive to external stimuli during counting.
  • a further object of the present invention is to provide a synchronous counter for electronic memories whose functionality may be monitored from outside the memory without requiring additional circuits.
  • Still another object of the present invention is to provide a synchronous counter for electronic memories which is protected against unwanted loading of addresses which are not expressly intended for the memory.
  • Yet another object of the present invention is to provide a synchronous counter for electronic memories which allows for assignment of the maximum possible time for carry calculation, maximizing the operating frequency.
  • a further object of the present invention is to provide a synchronous counter for electronic memories in which the corresponding control signals are not simultaneously active.
  • Another object of the present invention is to provide a synchronous counter for electronic memories which is highly reliable and relatively easy to manufacture at competitive costs.
  • a memory counter circuit that includes a plurality of mutually connected counter stages, an internal address bus interfaced with each one of the counter stages for sending an external address signal to each one of the counter stages, and a circuit or means for loading the external address signal onto the internal address bus.
  • the memory counter may further include an enabling circuit or means for enabling the connection between the internal bus and each one of the counter stages. This enabling means may be driven by a true address latch enable signal.
  • the memory counter may also include a circuit or means for generating the true address latch enable signal starting from an external address latch signal and a fast address latch enable signal. The fast address latch enable signal may be adapted to drive the means for loading the external address onto the internal address bus.
  • a signal generation circuit for generating clock signals for synchronizing each one of the counter stages is also included. The synchronization signals are preferably not simultaneously active.
  • FIG. 1 is a schematic block diagram of a synchronous counter according to the present invention
  • FIG. 2 is a schematic circuit diagram of a clock or timing generation circuit used in the synchronous counter according to the invention
  • FIG. 3 is a schematic circuit diagram of a stage of the counter according to the present invention.
  • FIG. 4 is a schematic circuit diagram of the first stage of the counter according to the present invention.
  • the memory uses interleaved read streams which allow a reduction, by at least half, of the access time and the cycle time.
  • the memory array is advantageously organized into two functionally identical banks capable of allowing the development of two simultaneous read processes.
  • the two read processes which are simultaneously active but independent, are appropriately synchronized with respect to each other. They are also advantageously concatenated to ensure the evolution of the read cycles on two banks in an interleaved mode and to allow (without any reduction in the read intervals) halving of the signal propagation times. Therefore, ultimately, a much faster reading of the memory cells is provided.
  • Each one of the separate memory banks has its own independent addressing system. Yet, at the same time the addressing systems are mutually compatible and may be mutually synchronized with an external timing signal which sets their timing.
  • the addressing system must have the characteristic of being directly configurable from outside the memory. It must also have an entirely autonomous updating capability, handled inside the memory, under the control of a stimulus which is activated externally to the memory.
  • FIGS. 1 to 4 The synchronous counter according to the present invention, particularly adapted for memories of the interleaved type, is now described with reference to FIGS. 1 to 4 .
  • Memories of the interleaved type which are the subject of co-pending patent applications also assigned to the present assignee, utilize the situation in which the new location to be read is adjacent to the previously read location to provide faster memory reading.
  • Adjacency allows the possibility of sequential reads, which are inherently associated with the concept of predictability of the subsequent location to be read.
  • the possibility of taking advantage of adjacency is the main characteristic of the interleaved memory type, which is characterized by interleaved read streams. This approach allows a reduction (by at least half) of both the time for access to the memory and the cycle time.
  • the memory array is conveniently organized into two separate memory banks. These memory banks are functionally dual and allow the simultaneous existence of two read processes.
  • the two simultaneously active but independent read processes are mutually appropriately synchronized and concatenated. This is done to ensure the evolution of the read cycles on the two separate banks in interlaced mode and to allow, without any reduction in the read intervals, halving of the read signal propagation times.
  • the data, extracted alternatively from the two memory banks, allows for a reduction of the overall read times.
  • the two separate banks that form the memory of the interleaved type each have their own independent addressing system. Yet, at the same time the addressing systems can be mutually synchronized by an external timing signal which regulates their evolution times.
  • the addressing system must have the characteristic of being directly configurable externally but also of having the possibility of autonomous updating, handled inside the memory itself, under the control of a stimulus activated from outside.
  • the counter according to the invention can conveniently be isolated from external stimuli and can be reconfigured autonomously whenever it is appropriately stimulated.
  • the base counter includes a plurality of N stages 1 in which the first stage is designated by the reference numeral 1 a .
  • the structure of the first stage can be particular, as described in detail hereinafter.
  • connection means 3 may conveniently include, for example, a pass gate driven by an address latch enable signal ALE.
  • the signal ALE is generated by an appropriately provided structure described hereinafter. The connection between the internal address bus 2 and the stages 1 of the counter therefore occurs from the bus 2 toward each stage through the pass gates 3 .
  • Each counter stage is further connected to a fast carry structure which is formed by a NAND gate 5 to which an inverter 6 is cascade-connected.
  • Output lines 7 from each counter stage 1 each provide an input to the NAND gate 5 , an output of which is sent to the inverter 6 and to a successive stage 1 of the counter.
  • the stages of the counter are divided into blocks of three, four, four and four, for example, and there are four NAND gates 5 and a matching number of inverters 6 . Therefore, the first group of three counter stages 1 has a corresponding NAND gate 5 to which it sends its outputs.
  • the output of the NAND gate 5 is sent to the first counter stage 1 of the second group of four counter stages, whose outputs are in turn sent to a second NAND gate 5 to which an inverter 6 is in turn cascade-connected.
  • the second group of four counter stages has a third NAND gate 5 to which its outputs (lines 7 ) are sent.
  • the output of the third NAND gate 5 is sent to the first counter stage 1 of the third group of four counter stages.
  • the third group of four counter stages has a fourth NAND gate 5 to which it sends its outputs.
  • the number of counter stages shown in FIG. 1 is of course merely an example.
  • the fast carry structures are used to reduce the carry propagation time.
  • the output of the second NAND gate 5 (and of the corresponding inverter 6 ) and the output of the fourth NAND gate 5 and of the corresponding inverter 6 are, respectively, a column carry signal COL_CARRY and its inverted equivalent COL_CARRYN, and a row carry signal ROW_CARRY.
  • the output of the fourth inverter 6 which is cascade-connected to the fourth NAND gate 5 , is provided to a further pass-gate 8 .
  • the pass-gate 8 is driven by a signal COUNT_CHECK which is used during counter testing before the device is deemed suitable for the intended operation.
  • the pass-gate 8 is directly interfaced with a data bus DATA_BUS, which is the main bus of the memory and transfers all the data to and from the memory.
  • the lines 7 output from each of the counter stages 1 are further directly interfaced with an internal row address bus 10 and with an internal column address bus 11 , which are respectively connected to row and column redundancy structures (not shown).
  • the signal ALE address latch enable
  • ALE address latch enable
  • a circuit structure 15 which generates, from a signal ALE 16 which is external to the memory, a signal ALE-fast. After an appropriate delay 17 , the circuit structure 15 generates a signal ALE which is true. That is, the signal ALE is a genuine address latch enable signal which is not dictated by false stimuli that reach the memory.
  • a structure 15 for generating the signal ALE is the subject of a co-pending patent application also assigned to the present assignee, which is hereby incorporated herein in its entirety by reference.
  • the signal ALE-fast drives the transfer of an external address 18 of the memory through an inverter 19 to a latch structure 20 .
  • the external address 18 is stored in the latch structure 20 and then sent on the internal address bus 2 .
  • the signal ALE i.e., the signal ALE which is assuredly intended for the memory, is instead used to drive the transfer of the external address 18 present on the address bus 2 from the address bus to each counter stage 1 .
  • FIG. 1 is a schematic block diagram of a counter for a memory in which, in summary, some stages 1 of the counter, specifically the stages arranged above the internal address bus 2 in the figure, are meant to count the column address.
  • the stages arranged below the internal bus 2 are dedicated to row carry.
  • the two groups of stages, arranged above and below the internal address bus 2 are in turn divided into two sub-groups which are mutually connected by the fast carry structures, as explained earlier.
  • the counter is further driven by an increment pulse INC which is generated by an appropriate circuit structure.
  • INC increment pulse
  • This circuit structure is the subject of a co-pending patent application assigned to the present assignee, which is hereby incorporated herein in its entirety by reference.
  • the pulse is input to a clock signal generation circuit 21 which emits signals M_INC and S_INC, which are respectively sent to each stage 1 of the counter according to the invention.
  • the increment pulse INC is, by construction, very narrow (with respect to the interval between two successive increments), to allow frequency maximization, since:
  • stage updating is substantially instantaneous and simultaneous for all the stages 1 .
  • the clock signals M_INC and S_INC are therefore derived from the increment pulse INC and do not temporally overlap (i.e., they are not simultaneously active). This reduces the possibility of internal acceleration of the counter (i.e., “runaway” effects).
  • FIG. 2 is a diagram of the circuit 21 for generating clock signals M_INC and S_INC and the respective inverted signals M_INCn and S_INCn.
  • Each counter stage 1 is connected to the adjacent counter stage and outputs to it an output carry signal 24 and an address signal 25 , which are then transferred to the adjacent stage 1 . This connection applies to each stage 1 of the counter.
  • the circuit details of one of the stages 1 of the counter according to the invention (shown in FIG. 1) and the first stage 1 a of the counter are now described with reference to FIGS. 3 and 4, respectively.
  • the column carry signal COL_CARRY and its inverted form COL_CARRYN, produced by the second NAND gate 5 and by the corresponding second inverter 6 are input to the first counter stage 1 of the counter stages meant to provide row carry counting.
  • the column carry signal COL_CARRY is also input to the third NAND gate 5 .
  • FIG. 4 shows the first stage 1 a of the counter according to the invention and the circuit structure upstream of each counter stage.
  • This circuit is formed by the external address 18 , by the inverter 19 which is driven by the signal ALE-fast, by the latch means 20 which interfaces with the bus 2 , and the pass-gate 3 which is driven by the signal ALE.
  • the counter stage 1 a is illustratively shown with dashed-lines in FIG. 4 and includes two latch structures. These are a master latch structure 30 and a slave latch structure 31 .
  • the master latch structure 30 and the slave latch structure 31 are mutually connected by first and second means 33 , 34 for enabling connection between the latch structures.
  • the means 33 , 34 may be pass gates, for example.
  • the enabling means 33 and 34 are respectively driven by the clock signals S_INC (S_INCn) and M_INC (M_INCn), explained earlier, and generated by the clock signal generation circuit 21 .
  • the output of the first counter stage includes a carry output signal CARRY_OUT, by its inverted form CARRY_OUTN, and by the address signal ADD.
  • FIG. 3 illustrates a stage 1 of the counter according to the invention, i.e., one of the stages that follows the first stage 1 a .
  • the difference between the first counter stage 1 a shown in FIG. 4 and the generic counter stage 1 shown in FIG. 3 is that each counter stage 1 after the first counter stage 1 a has a connection between the latch structure 30 and the latch structure 31 . This connection may occur along two mutually different paths following an inversion produced by the inverter 14 .
  • each counter stage after the first counter stage 1 a has a first path between the master structure 30 including means 40 for enabling connection between the latch structure 30 and the latch structure 31 , which are enabled by the presence (or absence) of an input carry signal CARRY_IN.
  • the connection enabling means may conveniently be a pass gate.
  • the second path for connection between the master latch structure 30 and the slave latch structure 31 i.e., the path from the output of the inverter 14 to the slave structure (latch) 11
  • a second connection enabling means 41 which may also conveniently be a pass gate.
  • the input carry signal CARRY_IN is fed to the N-channel transistor of the connection enabling means 40 , while the signal CARRY_INN (i.e., the inverted form of the preceding signal) is fed to the P-channel transistors of the first connection enabling means 40 and to the N-channel transistors of the second connection enabling means 41 .
  • the inverted input carry signal (CARRY_INN) is also input to carry forming means, conveniently including a pass gate 42 and a P-channel transistor 43 whose gate terminal receives as an input the carry signal CARRY_IN.
  • the inverted input carry signal (CARRY_INN) is instead sent to the P-channel transistor of the pass gate 42 , whose N-channel transistor is connected to the gate terminal of the P-channel transistor 43 .
  • the drain terminal is connected to means 44 for buffering the output carry (CARRY_OUT) which outputs the output carry.
  • the inverted output carry CARRY_OUTN is instead emitted by the pass gate 42 .
  • the counter circuit according to the invention therefore can be configured externally by the external address signal at each count start, internally updated during counting, and is substantially functionally insensitive to external stimuli during counting activity (i.e., when the signal ALE is off).
  • Each stage of the counter may be updated simultaneously and instantaneously with respect to all the other stages.
  • the association with the fast carry network allows reduction of the carry propagation time, thus increasing the operating frequency.
  • the fast carry network allows for monitoring the functionality of the counter from outside. By initializing the counter in the all-zero configuration and stimulating the counter with an adapted number of clock pulses (equal to the maximum count) it is possible, by observing the compatibility of the switching (from 0 to 1) of the row carry signal ROW_CARRY (global carry) with the number of the clock pulses, to monitor the correctness of the count and therefore the integrity of the counter.
  • This particular monitoring method allows selection, at the beginning of the testing activities, of the integrity of the addressing structures, limiting the long validation sequences only to the functionally addressable devices.
  • the particular input stage of the counter allows two-step acquisition of an external address, driven by the signal ALE, which accordingly allows protection against improper external loading.
  • the particular input stage of the counter allows isolation of the internal lines of the counter. This reduces unnecessary consumption in the interface section, facilitates noise immunity and freezes the initial configuration of the bus at its first loading so that at a generic instant both the current address and the initial address are present. This is due to the fact that the external address 18 is loaded in the latch structure 20 and the subsequent transfer from the bus 2 to the stages 1 of the counter is driven by the signal ALE. In the absence of such signal, the counter produces the current address and its initial address is still loaded in the bus.
  • the counter circuit according to the invention fully achieves the intended objects. That is, it provides greater speed of operation, adequate insensitivity to improper loading, and allows monitoring of its functional integrity from outside.

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US09/767,762 2000-02-14 2001-01-23 Synchronous counter for electronic memories Expired - Fee Related US6351434B2 (en)

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EP00830100 2000-02-14
EP00830100.4 2000-02-14
EP00830100A EP1126467B1 (fr) 2000-02-14 2000-02-14 Compteur synchrone pour mémoires électroniques

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Publication number Priority date Publication date Assignee Title
EP1884955A1 (fr) 2006-07-28 2008-02-06 STMicroelectronics S.r.l. Compteur d'adresses pour dispositif de mémoire non-volatile
CN102474950A (zh) * 2009-07-24 2012-05-23 皇家飞利浦电子股份有限公司 联网控制***设备的网格互联

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JPS5754432A (ja) 1980-09-19 1982-03-31 Hitachi Ltd Kauntodeetanyuryokukairo
JPS61281622A (ja) 1985-06-06 1986-12-12 Mitsubishi Electric Corp 計数回路
JPS62132425A (ja) 1985-12-04 1987-06-15 Nec Corp カウンタ
JPH0213128A (ja) 1988-06-30 1990-01-17 Sharp Corp 同期式プログラマブルカウンタ
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JPS5754432A (ja) 1980-09-19 1982-03-31 Hitachi Ltd Kauntodeetanyuryokukairo
JPS61281622A (ja) 1985-06-06 1986-12-12 Mitsubishi Electric Corp 計数回路
JPS62132425A (ja) 1985-12-04 1987-06-15 Nec Corp カウンタ
JPH0213128A (ja) 1988-06-30 1990-01-17 Sharp Corp 同期式プログラマブルカウンタ
US5361365A (en) 1989-11-06 1994-11-01 Sharp Kabushiki Kaisha Microprocessor for selectively performing cold and warm starts
US5339344A (en) * 1990-06-01 1994-08-16 Mitsubishi Denki Kabushiki Kaisha Counter device and method of operating the same
US5561674A (en) 1994-05-26 1996-10-01 Samsung Electronics Co., Ltd. Synchronous counter and method for propagation carry of the same
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US5781500A (en) 1996-05-06 1998-07-14 Hyundai Electronics Industries Co., Ltd. Method and circuit for generating internal pulse signals in synchronous memory

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EP1126467B1 (fr) 2009-04-08
EP1126467A1 (fr) 2001-08-22
US20010014041A1 (en) 2001-08-16
DE60041954D1 (fr) 2009-05-20

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