US6171939B1 - Method for forming polysilicon gate electrode - Google Patents
Method for forming polysilicon gate electrode Download PDFInfo
- Publication number
- US6171939B1 US6171939B1 US09/348,389 US34838999A US6171939B1 US 6171939 B1 US6171939 B1 US 6171939B1 US 34838999 A US34838999 A US 34838999A US 6171939 B1 US6171939 B1 US 6171939B1
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- United States
- Prior art keywords
- polysilicon layer
- forming
- layer
- undoped polysilicon
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 133
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 133
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 25
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 25
- 229910052785 arsenic Inorganic materials 0.000 claims description 16
- -1 arsenic ions Chemical class 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 15
- 239000002019 doping agent Substances 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims 3
- 239000010410 layer Substances 0.000 description 120
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000007943 implant Substances 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 238000005280 amorphization Methods 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910021341 titanium silicide Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Definitions
- the present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a polysilicon gate electrode.
- a metal silicide layer is frequently formed as part of a gate electrode in addition to a polysilicon layer. Because the metal silicide layer can be formed without performing a photolithographic operation, the method of forming a silicide layer is often referred to as a self-aligned silicide (Salicide) process. Most salicide layers are formed using titanium silicide (TiSi x ). Titanium silicide is often used because it has a low resistivity. In addition, a titanium silicide layer can be formed in a controlled manner so that quality and reliability can always be maintained.
- FIGS. 1A through 1C are schematic, cross-sectional view showing the progression of steps for forming a conventional gate electrode.
- a semiconductor substrate 100 having device isolation structures 102 therein is provided.
- a gate oxide layer 104 and a doped polysilicon layer 106 are sequentially formed over the substrate 100 .
- the gate oxide layer 104 and the doped polysilicon layer 106 are patterned to form a gate electrode 108 .
- an anti-reflection coating 110 typically made from silicon oxynitride, is formed over the polysilicon layer 106 before the gate oxide layer 104 and the polysilicon layer 106 are patterned.
- hot phosphoric acid is used to remove the anti-reflection coating 110 .
- a portion of the doped polysilicon layer 106 may be damaged by phosphoric acid. Therefore, a portion of the polysilicon layer in the gate structure may peel off resulting in a degradation of device's performance characteristics.
- an pre-amorphization implant is carried out implanting arsenic ions into the polysilicon gate electrode 108 so that a surface layer of the polysilicon layer 106 is broken down into an amorphous silicon layer 112 .
- the amorphization of the polysilicon layer 106 facilitates the subsequent formation of a silicide layer.
- Source/drain regions 114 having a lightly doped drain (LDD) structure is formed in the substrate 100 on each side of the gate electrode 108 .
- a layer of titanium (not shown in the figure) is sputtered over the substrate 100 .
- metal in the titanium layer reacts with silicon in the doped polysilicon layer 106 and silicon in the source/drain regions 114 to form a titanium silicide layer 116 .
- the unreacted titanium is removed by wet etching to form the structure as shown in FIG. 1 C.
- the purpose of the present invention is to provide a method for forming polysilicon gate electrode capable of reducing the peeling of polysilicon gate layer due to the removal of anti-reflection coating by phosphoric acid.
- the method is also capable of moderating kink effect due to penetration of ions in PAI, and dopant effect due to the prevention of silicon diffusion by dopants within the polysilicon gate layer.
- the invention provides a method for forming a polysilicon gate electrode.
- a semiconductor substrate is provided.
- a gate oxide layer, a partially doped polysilicon layer and an undoped polysilicon layer are sequentially formed over the semiconductor substrate.
- the undoped polysilicon layer, the partially doped polysilicon layer and the gate oxide layer are patterned to form a gate electrode.
- the invention also provides a method for forming a metal-oxide-semiconductor (MOS) transistor.
- a semiconductor substrate having device isolation structures therein is provided.
- a gate oxide layer, a partially doped polysilicon layer and an undoped polysilicon layer are sequentially formed over the substrate.
- the partially doped polysilicon layer and the undoped polysilicon layer are patterned to form a gate electrode.
- a lightly doped drain region is formed in the substrate on each side of the gate electrode.
- Spacers are formed on the sidewalls of the gate electrode.
- a heavily doped region is formed in the substrate.
- a metal silicide layer is formed at a top surface of the gate electrode and a top surface of the heavily doped region of the substrate.
- An anti-reflection coating can be formed prior to the patterning of the partially doped polysilicon layer and the undoped polysilicon layer.
- the stacked polysilicon gate electrode of this invention includes an undoped polysilicon layer and a doped polysilicon layer. Since the undoped polysilicon layer is on top to protect the doped polysilicon layer when hot phosphoric acid is used to remove the anti-reflection coating, the doped polysilicon layer is less likely to peel off due to the acid.
- the stacked polysilicon gate electrode structure of this invention is able to provide an additional interface. Consequently, when arsenic ions are implanted in a PAI, less arsenic ions will be able to pass through the gate electrode and ends up in the substrate. Without additional arsenic ions in the channel of the substrate, kink effect will be subdued.
- FIGS. 1A through 1C are schematic, cross-sectional view showing the progression of steps for forming a conventional gate electrode
- FIGS. 2A through 2F are schematic, cross-sectional view showing the progression of steps for forming a polysilicon gate electrode according to a preferred embodiment of this invention.
- FIGS. 2A through 2F are schematic, cross-sectional view showing the progression of steps for forming a polysilicon gate electrode according to a preferred embodiment of this invention.
- fabrication of a polysilicon gate electrode of an N-type metallic-oxide-semiconductor (NMOS) transistor is chosen as an example.
- a substrate 200 such as a P-type semiconductor substrate is provided.
- Device isolation structures for example, shallow trench isolation (STI) structures are formed in the substrate 200 so that an active region 204 is marked out.
- a gate oxide layer 206 is formed over the substrate 200 .
- the gate oxide layer 206 can be formed, for example, by performing a thermal oxidation.
- An undoped polysilicon layer 208 is formed over the gate oxide layer 206 .
- the undoped polysilicon layer 208 having a thickness of between 1200 ⁇ to 1800 ⁇ , and preferably about 1500 ⁇ , is formed, for example, by chemical vapor deposition.
- an ion implant is carried out to convert a top layer of the undoped polysilicon layer 208 into a doped polysilicon layer 212 .
- Arsenic or phosphorus ions for example, can be used in the ion implant.
- an energy level of between 20 eV to 40 eV and a dosage of between 1E15 to 5E15 atoms/cm 2 are used in the implantation.
- the undoped polysilicon layer 208 and the doped polysilicon layer 212 together form a partially doped polysilicon layer 208 a.
- another undoped polysilicon layer 214 is formed over the partially doped polysilicon layer 208 a .
- the undoped polysilicon layer 214 having a thickness of between 300 ⁇ to 800 ⁇ , preferably about 500 ⁇ , can be formed, for example, by chemical vapor deposition (CVD).
- An anti-reflection coating 216 is formed over the undoped polysilicon layer 214 .
- the anti-reflection coating 216 can be formed using a material such as silicon oxynitride (SiON).
- SiON silicon oxynitride
- the gate oxide layer 206 , the partially doped polysilicon layer 208 a , the undoped polysilicon layer 214 and the anti-reflection coating 216 are patterned to form a gate electrode 220 .
- the anti-reflection coating 216 is removed using hot phosphoric acid, for example. Since the partially doped polysilicon layer 208 a is protected by the overlying undoped polysilicon layer 214 , peeling of the polysilicon gate electrode due to the removal of anti-reflection coating 216 by hot phosphoric acid is avoided.
- an ion implant is carried out to form lightly doped regions 222 in the substrate 200 on each side of the gate electrode 220 .
- Spacers 224 are formed on the sidewalls of the gate electrode 220 .
- the spacers 224 can be a silicon nitride layer or a silicon oxide layer, for example.
- another ion implant is carried out to form heavily doped regions 226 in the substrate 200 just outside the lightly doped regions 222 .
- the lightly doped regions 222 and the heavily doped regions 226 together constitute source/drain regions 228 that have a lightly doped drain (LDD) structure.
- LDD lightly doped drain
- a pre-amorphization implant is next carried out converting a surface layer of the gate electrode 220 into an amorphous layer 230 .
- the PAI is carried out using arsenic ions, for example. Up to this stage, a MOS transistor is formed.
- CMOS complementary MOS
- the stacked gate electrode 220 includes the undoped polysilicon layer 214 and the partially doped polysilicon layer 208 a , an interface is formed between the undoped polysilicon layer 214 and the partially doped polysilicon layer 208 a .
- arsenic ions bombards the polysilicon gate electrode 220 to form a top amorphous silicon layer 230 , movement of the arsenic ions is hindered at the interface. Due to the presence of the interface, movement of arsenic ions down to the substrate 200 following the boundaries of grains within the polysilicon and the gate oxide layer 206 has almost stopped. Therefore, performance degradation due to kink effect is greatly reduced.
- a silicide layer 232 is formed over the source/drain regions 228 and the amorphous silicon layer 230 of the gate electrode 220 .
- the silicide layer 232 is formed, for example, by sputtering to form a metallic layer such as a titanium layer over the substrate 200 and the gate electrode 220 . This is followed by performing a rapid thermal process (RTP) so that metal in the metallic layer and silicon in the substrate and the amorphous silicon layer 230 is able to react. Any unreacted metal is subsequently removed by wet etching.
- RTP rapid thermal process
- dopants within the polysilicon layer often prevent the diffusion of silicon and hinder the formation of the silicide layer.
- the situation is changed using the stacked polysilicon gate electrode of this invention because there is an undoped polysilicon layer 214 above the partially doped polysilicon layer 208 a .
- the undoped polysilicon layer 214 has no dopants to hinder the silicide-forming process.
- the heat generated by the silicide-forming process is able to drive, by diffusion, the dopants inside the partially doped polysilicon layer 208 a into undoped polysilicon layer 214 .
- the undoped polysilicon layer 214 will be converted into a partially doped polysilicon layer 214 a , thereby increasing its electrical conductivity.
- the advantages of this invention includes:
- the partially doped polysilicon layer is less likely to peel off when hot phosphoric acid is used to remove the anti-reflection coating.
- the stacked polysilicon gate electrode structure of this invention is able to provide an additional interface.
- arsenic ions are implanted in a PAI, less arsenic ions are able to pass through the gate electrode and ends up in the channel region of the substrate. Consequently, kink effect is alleviated.
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Abstract
Description
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/348,389 US6171939B1 (en) | 1999-07-07 | 1999-07-07 | Method for forming polysilicon gate electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/348,389 US6171939B1 (en) | 1999-07-07 | 1999-07-07 | Method for forming polysilicon gate electrode |
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US6171939B1 true US6171939B1 (en) | 2001-01-09 |
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US09/348,389 Expired - Lifetime US6171939B1 (en) | 1999-07-07 | 1999-07-07 | Method for forming polysilicon gate electrode |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6376342B1 (en) * | 2000-09-27 | 2002-04-23 | Vanguard International Semiconductor Corporation | Method of forming a metal silicide layer on a source/drain region of a MOSFET device |
US20050236667A1 (en) * | 2003-05-30 | 2005-10-27 | Fujitsu Limited | Manufacture of semiconductor device with selective amorphousizing |
US7109555B1 (en) * | 2004-04-28 | 2006-09-19 | Spansion Llc | Method for providing short channel effect control using a silicide VSS line |
US20080194072A1 (en) * | 2007-02-12 | 2008-08-14 | Chen-Hua Yu | Polysilicon gate formation by in-situ doping |
US20100068873A1 (en) * | 2008-09-16 | 2010-03-18 | Jing-Cheng Lin | Depletion-Free MOS using Atomic-Layer Doping |
US20100330789A1 (en) * | 2009-06-25 | 2010-12-30 | Hynix Semiconductor Inc. | Method of Forming Nonvolatile Memory Device |
US7892909B2 (en) | 2007-02-12 | 2011-02-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polysilicon gate formation by in-situ doping |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US5605848A (en) * | 1995-12-27 | 1997-02-25 | Chartered Semiconductor Manufacturing Pte Ltd. | Dual ion implantation process for gate oxide improvement |
US5877050A (en) * | 1996-09-03 | 1999-03-02 | Advanced Micro Devices, Inc. | Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals |
US6037204A (en) * | 1998-08-07 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company | Silicon and arsenic double implanted pre-amorphization process for salicide technology |
US6037228A (en) * | 1999-02-12 | 2000-03-14 | United Microelectronics Corp. | Method of fabricating self-aligned contact window which includes forming a undoped polysilicon spacer that extends into a recess of the gate structure |
-
1999
- 1999-07-07 US US09/348,389 patent/US6171939B1/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US5605848A (en) * | 1995-12-27 | 1997-02-25 | Chartered Semiconductor Manufacturing Pte Ltd. | Dual ion implantation process for gate oxide improvement |
US5877050A (en) * | 1996-09-03 | 1999-03-02 | Advanced Micro Devices, Inc. | Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals |
US6037204A (en) * | 1998-08-07 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company | Silicon and arsenic double implanted pre-amorphization process for salicide technology |
US6037228A (en) * | 1999-02-12 | 2000-03-14 | United Microelectronics Corp. | Method of fabricating self-aligned contact window which includes forming a undoped polysilicon spacer that extends into a recess of the gate structure |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6376342B1 (en) * | 2000-09-27 | 2002-04-23 | Vanguard International Semiconductor Corporation | Method of forming a metal silicide layer on a source/drain region of a MOSFET device |
US20050236667A1 (en) * | 2003-05-30 | 2005-10-27 | Fujitsu Limited | Manufacture of semiconductor device with selective amorphousizing |
US7109555B1 (en) * | 2004-04-28 | 2006-09-19 | Spansion Llc | Method for providing short channel effect control using a silicide VSS line |
US20080194072A1 (en) * | 2007-02-12 | 2008-08-14 | Chen-Hua Yu | Polysilicon gate formation by in-situ doping |
US7892909B2 (en) | 2007-02-12 | 2011-02-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polysilicon gate formation by in-situ doping |
US20100068873A1 (en) * | 2008-09-16 | 2010-03-18 | Jing-Cheng Lin | Depletion-Free MOS using Atomic-Layer Doping |
US7790535B2 (en) | 2008-09-16 | 2010-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Depletion-free MOS using atomic-layer doping |
US20110018069A1 (en) * | 2008-09-16 | 2011-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Depletion-Free MOS using Atomic-Layer Doping |
US8395221B2 (en) | 2008-09-16 | 2013-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Depletion-free MOS using atomic-layer doping |
US20100330789A1 (en) * | 2009-06-25 | 2010-12-30 | Hynix Semiconductor Inc. | Method of Forming Nonvolatile Memory Device |
US8058160B2 (en) * | 2009-06-25 | 2011-11-15 | Hynix Semiconductor Inc. | Method of forming nonvolatile memory device |
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