US6169311B1 - Semiconductor integrated circuit having an input and output protective circuit - Google Patents
Semiconductor integrated circuit having an input and output protective circuit Download PDFInfo
- Publication number
- US6169311B1 US6169311B1 US09/179,412 US17941298A US6169311B1 US 6169311 B1 US6169311 B1 US 6169311B1 US 17941298 A US17941298 A US 17941298A US 6169311 B1 US6169311 B1 US 6169311B1
- Authority
- US
- United States
- Prior art keywords
- channel transistor
- semiconductor substrate
- integrated circuit
- protective resistance
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 230000001681 protective effect Effects 0.000 title claims abstract description 61
- 239000000758 substrate Substances 0.000 claims description 27
- 238000009792 diffusion process Methods 0.000 claims description 22
- 229910021332 silicide Inorganic materials 0.000 claims description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- 239000010410 layer Substances 0.000 description 19
- 230000003068 static effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000005611 electricity Effects 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Definitions
- This invention relates to a semiconductor integrated circuit, and more particularly to, a semiconductor integrated circuit composed to protect an input buffer from breakage caused by static discharge.
- part of internal element of the semiconductor device may be deteriorated or broken by static discharge.
- a semi-custom integrated circuit such as a gate array and a standard cell is often composed combining several common transistors in advance provided with input and output circuits including a static electricity protection function, without discriminating between input pad and output pad to facilitate the formation of LSI designing library.
- a conventional CMOS (complementary metal-oxide semiconductor) type input and output circuit is, for example as shown in FIG.1, composed by, in advance, providing p-channel transistors 3 , 4 , 5 and 6 with same gate length and gate width and n-channel transistors 7 , 8 , 9 and 10 with same gate length and gate.
- CMOS complementary metal-oxide semiconductor
- the p-channel transistors 3 , 4 are connected between a power source line 16 and an input pad 1 and the n-channel transistors 7 , 8 are connected between a ground line 17 and the input pad 1 .
- the gate electrodes of the p-channel transistors 3 , 4 are connected to the power source line 16
- the gate electrodes of the n-channel transistors 7 , 8 are connected to the ground line 17 .
- the p-channel transistor 3 and the n-channel transistor 7 compose an input protective circuit 50
- the p-channel transistor 4 and the n-channel transistor 8 compose an input protective circuit 19 .
- the p-channel transistors 5 , 6 are connected between the power source line 16 and the output pad 2 and the n-channel transistors 9 , 10 are connected between the ground line 17 and the output pad 2 .
- the gate electrodes of the p-channel transistor 5 and the n-channel transistor 9 are connected to an internal circuit 20 .
- the p-channel transistor 5 and the n-channel transistor 9 compose an output circuit 52 .
- the p-channel transistor 6 and the n-channel transistor 10 which do not contribute to the signal outputting from the internal circuit 20 , compose an output protective circuit 53 , like the input protective circuit.
- the input and output circuit including the static electricity protection function can be efficiently realized.
- the placement of the resistance elements 11 , 12 restricts current flow to the n-channel transistors 7 , 8 thereby preventing the n-channel transistors 7 , 8 from breaking down, the gate oxide film in the internal circuit 20 may be damaged before the protective circuit operates because the input pad 1 is directly connected to the gate electrodes of a p-channel transistor 21 and a n-channel transistor 22 inside the internal circuit 20 .
- a conventional technique to solve this problem is, for example, disclosed in Japanese patent application laid-open No. 9-97844 (1997), regarding an input protective circuit.
- the p-channel transistor 3 is connected between the power source line 16 and the input pad 1
- the n-channel transistor 7 is connected between the ground line 17 and the input pad 1 .
- the gate electrode of the p-channel transistor 3 is connected to the power source line 16
- the gate electrode of the n-channel transistor 7 is connected to the ground line 17 .
- the n-well resistance 11 is inserted between the input pad 1 and the internal circuit 20 .
- Japanese patent application laid-open No. 9-97844 discloses an output protective circuit.
- the p-channel transistor 6 and the n-channel transistor 10 are connected in series, the source electrode of the p-channel transistor 6 is connected to the power source line 16 , and the source electrode of the n-channel transistor 10 is connected to the ground line 17 .
- the gate electrode of the p-channel transistor 6 is connected to the power source line 16 , and the gate electrode of the n-channel transistor 10 is connected to the ground line 17 .
- the resistance element 13 is inserted between the input pad 2 and the connecting part of the p-channel transistor 6 and the n-channel transistor 10 .
- the output protective circuit 55 is connected in parallel to the output circuit 24 .
- the input protective circuit 54 in FIG. 3 the input protection in the internal circuit 20 can be surely performed.
- the n-channel transistor 7 itself cannot be prevented from breaking down because the n-channel transistor 7 as the protective element is, as mentioned earlier, directly connected to the input pad 1 .
- the circuit composition of the input protective circuit 54 is unalteredly applied to the output circuit as well, in particular, when outputting High level in a high drive output buffer, the resistivity of the n-well resistance element 11 becomes unnegligible and the output drive performance must be significantly deteriorated because the elemental performance of p-channel transistor is generally lower than that of n-channel transistor.
- the layout area of the output p-channel transistor must be enlarged and therefore a circuit composition available for both the input circuit and the output circuit cannot be realized. Thus, it cannot be unalteredly applied to a gate array or a standard cell.
- the static electricity protection of the output circuit can be performed without deteriorating the drive performance of the output circuit.
- the n-channel transistor 9 itself cannot be prevented from breaking down because the n-channel transistor 9 is, as mentioned earlier, directly connected to the output pad 2 .
- the resistance element 13 is relatively large, the n-channel transistor 9 may become more likely to be broken down. It is very difficult to choose an optimum resistance value.
- two kinds of circuit compositions, the output circuit 24 and the output protective circuit 55 have to be provided for one pad. Therefore, it is not multipurpose and cannot be unalteredly applied to a gate array or a standard cell.
- a MOS-type semiconductor integrated circuit comprises:
- an input circuit section including an n-channel transistor, a p-channel transistor and a protective resistance connected between the n-channel transistor and the p-channel transistor;
- a MOS-type semiconductor integrated circuit comprises:
- the input circuit section includes a first n-channel transistor, a first p-channel transistor and a first protective resistance connected between the first n-channel transistor and the first p-channel transistor, the input pad being connected between the first p-channel transistor and the first protective resistance, the internal circuit section being connected between the first n-channel transistor and the first protective resistance; and the output circuit section includes a second n-channel transistor, a second p-channel transistor and a second protective resistance connected between the second n-channel transistor and the second p-channel transistor, the output pad being connected between the second p-channel transistor and the second protective resistance, the internal circuit section being connected to the second n-channel transistor and the second p-channel transistor.
- FIG. 1 is a circuit diagram showing an input and output circuit in a conventional semiconductor integrated circuit
- FIG. 2 is a circuit diagram for explaining a problem in the convention semiconductor integrated circuit
- FIG. 3 is a circuit diagram showing an input circuit in another conventional semiconductor integrated circuit
- FIG. 4 is a circuit diagram showing an output circuit in still another conventional semiconductor integrated circuit
- FIG. 5 is a circuit diagram showing a semiconductor integrated circuit in a first preferred embodiment according to the invention.
- FIG. 6 is a layout diagram showing the semiconductor integrated circuit in the first embodiment
- FIG. 7 is a cross section view cut along the line A-A′ in FIG. 6,
- FIG. 8 is a layout diagram showing a semiconductor integrated circuit in a second preferred embodiment according to the invention.
- FIG. 9 is a cross section view cut along the line B-B′ in FIG. 8 .
- FIG. 5 is a circuit diagram showing a semiconductor integrated circuit in the first preferred embodiment according to the invention.
- the input and output circuit with the static electricity protection function is, for example as shown in FIG. 5, composed by in advance providing the p-channel transistors 3 , 4 , 5 and 6 with same gate length and gate width, the n-channel transistors 7 , 8 , 9 and 10 with same gate length and gate width, and the n-well resistance elements 11 , 12 , 13 and 14 , for the input and output pads 1 and 2 , and combining them.
- the p-channel transistors 3 and 4 are connected between the power source line 16 and the input pad 1 .
- the n-channel transistor 7 and the n-well resistance element 11 and the n-channel transistor 8 and the n-well resistance element 12 , respectively, are connected in series between the ground line 17 and the input pad 1 .
- the gate electrodes of the p-channel transistors 3 , 4 are connected to the power source line 16
- the gate electrodes of the n-channel transistors 7 , 8 are connected to the ground line 17 .
- the p-channel transistor 3 , the n-channel transistor 7 and the n-well resistance element 11 compose the input protective circuit 18 . Also, the p-channel transistor 4 , the n-channel transistor 8 and the n-well resistance element 12 compose the input protective circuit 19 .
- connection part between the n-channel transistor 8 and the n-well resistance element 12 in the input protective circuit 19 is connected to the input of the internal circuit 20 , e.g., the gate electrode of the p-channel transistor 21 in the internal circuit 20 and the gate electrode of the n-channel transistor 22 in the internal circuit 20 .
- the p-channel transistors 5 , 6 are connected between the power source line 16 and the output pad 2 .
- the n-channel transistor 9 and the n-well resistance element 13 are connected in series between the ground line 17 and the output pad 2 .
- the gate electrodes of the p-channel transistor 5 and the n-channel transistor 9 are connected to the internal circuit 20 .
- the p-channel transistor 5 , the n-channel transistor 9 and the n-well resistance element 13 compose the output circuit 24 . Also, the p-channel transistor 6 , the n-channel transistor 10 and the n-well resistance element 14 compose the output protective circuit 25 .
- the operation of this embodiment will be explained referring to FIG. 5 .
- the n-channel transistors 7 , 8 , 9 and 10 break down through the resistance elements 11 , 12 , 13 and 14 and serve to lead an excess voltage to the ground line 17 .
- the protective circuit can be surely operated before the gate oxide film of the internal circuit 20 is broken.
- FIG. 6 is a layout diagram showing the semiconductor integrated circuit in the first embodiment
- FIG. 7 is a cross sectional view cut along the line A-A′ in FIG. 6 .
- the silicide layer of n-type diffusion layer regions 28 , 29 and 30 is separated by gate electrodes 26 , 27 with a channel length of, e.g., 0.3 ⁇ m, the minimum size of semiconductor fabrication process, and the n-well resistance's 11 , 12 are formed through a n-well region 32 introduced into a p-type substrate 31 .
- a device-forming region is formed by a LOCOS (local oxidation of silicon) region 33 on the p-type substrate 31 .
- the n-channel transistor 8 is formed by a gate electrode 34 , an n-type diffusion layer source region 35 and an n-type diffusion layer drain region 28 .
- the n-channel transistor 8 is formed by a gate electrode 36 , an n-type diffusion layer source region 37 and an n-type diffusion layer drain region 30 .
- the n-type diffusion layer source regions 35 , 37 are connected through contacts 38 , 39 , respectively, and first-layer aluminum wirings 40 , 41 to the ground line 17 .
- the drain regions 28 , 30 of the n-channel transistors 7 , 8 are connected in series to the n-well resistance's 11 , 12 , respectively, and are connected through a contact 42 and a first-layer aluminum wiring 43 to the input pad 1 .
- the gate electrodes 26 , 27 for separating the silicide layer are connected through a contact 44 to the first-layer aluminum wiring 43
- the gate electrodes 34 , 36 of the n-channel transistors 7 , 8 are connected through contacts 45 , 46 and the first-layer aluminum wirings 40 , 41 to the ground line 17 .
- An input signal from the input protective circuit 12 is connected through the n-well resistance element 12 , the drain region 28 of the n-channel transistor 8 , a contact 47 and a first-layer aluminum wiring 48 to the internal circuit 20 .
- the first-layer aluminum wiring 43 only has to be connected to the output pad 2 while disconnecting the contact 47 for connecting to the internal circuit 20 .
- the gate electrodes 45 , 46 only have to be further connected to the internal circuit 20 . Thus, only by changing the wiring, an excellent input protective circuit can be easy provided.
- FIG. 8 is a layout diagram showing a semiconductor integrated circuit in the second preferred embodiment according to the invention
- FIG. 9 is a cross sectional view cut along the line B-B′ in FIG. 8 .
- the silicide layer of the n-type diffusion layer regions 28 , 29 and 30 is separated.
- the n-well resistance's 11 , 12 are formed through the n-well region 32 introduced in the p-type substrate 31 .
- the other components are same as the first embodiment.
- an input from outside is supplied through protective resistance to the internal circuit even when the static electricity break-down voltage of n-channel transistor is enhanced by the protective resistance and the n-channel transistor becomes hard to break down. Therefore, the protective circuit can operate before the gate oxide film etc. in the internal circuit breaks, thereby performing effectively the static electricity protection. As a result, the reliability of semiconductor integrated circuit can be enhanced.
- the input and output circuit can be composed only by changing the wiring without enlarging the layout area. As a result, it can be easily applied to a semi-custom integrated circuit, such as a gate array and a standard cell.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (18)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9-294286 | 1997-10-27 | ||
JP09294286A JP3102391B2 (en) | 1997-10-27 | 1997-10-27 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
US6169311B1 true US6169311B1 (en) | 2001-01-02 |
Family
ID=17805743
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/179,412 Expired - Lifetime US6169311B1 (en) | 1997-10-27 | 1998-10-27 | Semiconductor integrated circuit having an input and output protective circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US6169311B1 (en) |
JP (1) | JP3102391B2 (en) |
KR (2) | KR100297151B1 (en) |
CN (1) | CN1139991C (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6288428B1 (en) * | 1997-03-12 | 2001-09-11 | Rohm Co., Ltd. | Semiconductor integrated circuit device for disk drive apparatus |
US6320229B1 (en) * | 1998-05-18 | 2001-11-20 | Matsushita Electronics Corporation | Semiconductor device |
US20030184507A1 (en) * | 2002-03-29 | 2003-10-02 | Yoshiaki Nakazaki | Protection circuit for input and output of liquid crystal display |
US20030206048A1 (en) * | 2002-02-05 | 2003-11-06 | Hitachi, Ltd. | Data transmission system |
US20080303093A1 (en) * | 2007-06-05 | 2008-12-11 | Kabushiki Kaisha Toshiba | Semiconductor apparatus |
US20110187475A1 (en) * | 2010-02-01 | 2011-08-04 | Samsung Electro-Mechanics Co., Ltd. | Radio frequency switch circuit |
US20110187417A1 (en) * | 2010-02-01 | 2011-08-04 | Samsung Electro-Mechanics Co., Ltd. | Radio frequency switch circuit |
CN103325784A (en) * | 2013-06-09 | 2013-09-25 | 电子科技大学 | Chip static electricity protection circuit based on memristor |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006313814A (en) * | 2005-05-09 | 2006-11-16 | Oki Electric Ind Co Ltd | Semiconductor device |
JP2005294868A (en) * | 2005-06-27 | 2005-10-20 | Ricoh Co Ltd | Semiconductor device |
JP5586819B2 (en) * | 2006-04-06 | 2014-09-10 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5295185A (en) | 1976-02-06 | 1977-08-10 | Hitachi Ltd | Mis semiconductor unit |
JPS6356952A (en) | 1986-08-28 | 1988-03-11 | Yokogawa Electric Corp | Semiconductor resistance element |
JPH03278571A (en) | 1990-03-28 | 1991-12-10 | Nec Corp | Output buffer |
JPH05218313A (en) | 1992-02-04 | 1993-08-27 | Nec Corp | Semiconductor input protective device |
JPH06244371A (en) | 1992-10-05 | 1994-09-02 | Matsushita Electric Ind Co Ltd | Semiconductor device |
JPH07202009A (en) | 1993-12-28 | 1995-08-04 | Nec Corp | Semiconductor device having output circuit of cmos structure |
JPH08139274A (en) | 1994-11-11 | 1996-05-31 | Sony Corp | Semiconductor device |
-
1997
- 1997-10-27 JP JP09294286A patent/JP3102391B2/en not_active Expired - Fee Related
-
1998
- 1998-10-26 KR KR1019980044832A patent/KR100297151B1/en not_active IP Right Cessation
- 1998-10-27 US US09/179,412 patent/US6169311B1/en not_active Expired - Lifetime
- 1998-10-27 CN CNB981235417A patent/CN1139991C/en not_active Expired - Fee Related
-
2000
- 2000-12-26 KR KR1020000081733A patent/KR20010021489A/en not_active Application Discontinuation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5295185A (en) | 1976-02-06 | 1977-08-10 | Hitachi Ltd | Mis semiconductor unit |
JPS6356952A (en) | 1986-08-28 | 1988-03-11 | Yokogawa Electric Corp | Semiconductor resistance element |
JPH03278571A (en) | 1990-03-28 | 1991-12-10 | Nec Corp | Output buffer |
JPH05218313A (en) | 1992-02-04 | 1993-08-27 | Nec Corp | Semiconductor input protective device |
JPH06244371A (en) | 1992-10-05 | 1994-09-02 | Matsushita Electric Ind Co Ltd | Semiconductor device |
JPH07202009A (en) | 1993-12-28 | 1995-08-04 | Nec Corp | Semiconductor device having output circuit of cmos structure |
JPH08139274A (en) | 1994-11-11 | 1996-05-31 | Sony Corp | Semiconductor device |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6288428B1 (en) * | 1997-03-12 | 2001-09-11 | Rohm Co., Ltd. | Semiconductor integrated circuit device for disk drive apparatus |
US6320229B1 (en) * | 1998-05-18 | 2001-11-20 | Matsushita Electronics Corporation | Semiconductor device |
US20030206048A1 (en) * | 2002-02-05 | 2003-11-06 | Hitachi, Ltd. | Data transmission system |
US7260057B2 (en) * | 2002-02-05 | 2007-08-21 | Hitachi, Ltd. | Data transmission system |
US20030184507A1 (en) * | 2002-03-29 | 2003-10-02 | Yoshiaki Nakazaki | Protection circuit for input and output of liquid crystal display |
US7138987B2 (en) * | 2002-03-29 | 2006-11-21 | Kabushiki Kaisha Ekisho Sentan Gijutsu Kaihatsu Center | Protection circuit for input and output of liquid crystal display |
US20070001949A1 (en) * | 2002-03-29 | 2007-01-04 | Yoshiaki Nakazaki | Protective circuit for a thin film transistor and a liquid crystal display device |
US7863687B2 (en) * | 2007-06-05 | 2011-01-04 | Kabushiki Kaisha Toshiba | Semiconductor apparatus |
US20080303093A1 (en) * | 2007-06-05 | 2008-12-11 | Kabushiki Kaisha Toshiba | Semiconductor apparatus |
US20110073949A1 (en) * | 2007-06-05 | 2011-03-31 | Kabushiki Kaisha Toshiba | Semiconductor apparatus |
US8115257B2 (en) | 2007-06-05 | 2012-02-14 | Kabushiki Kaisha Toshiba | Semiconductor apparatus |
US20110187475A1 (en) * | 2010-02-01 | 2011-08-04 | Samsung Electro-Mechanics Co., Ltd. | Radio frequency switch circuit |
US20110187417A1 (en) * | 2010-02-01 | 2011-08-04 | Samsung Electro-Mechanics Co., Ltd. | Radio frequency switch circuit |
US8461919B2 (en) | 2010-02-01 | 2013-06-11 | Samsung Electro-Mechanics Co., Ltd | Radio frequency switch circuit |
US8476959B2 (en) | 2010-02-01 | 2013-07-02 | Samsung Electro-Mechanics Co., Ltd. | Radio frequency switch circuit |
CN103325784A (en) * | 2013-06-09 | 2013-09-25 | 电子科技大学 | Chip static electricity protection circuit based on memristor |
CN103325784B (en) * | 2013-06-09 | 2015-11-25 | 电子科技大学 | Based on the chip electrostatic protection circuit of memristor |
Also Published As
Publication number | Publication date |
---|---|
KR20010021489A (en) | 2001-03-15 |
JPH11135717A (en) | 1999-05-21 |
CN1139991C (en) | 2004-02-25 |
JP3102391B2 (en) | 2000-10-23 |
KR19990037386A (en) | 1999-05-25 |
KR100297151B1 (en) | 2001-08-07 |
CN1215924A (en) | 1999-05-05 |
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