US6153909A - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
- Publication number
- US6153909A US6153909A US09/217,202 US21720298A US6153909A US 6153909 A US6153909 A US 6153909A US 21720298 A US21720298 A US 21720298A US 6153909 A US6153909 A US 6153909A
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- semiconductor device
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- conduction type
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 230000000694 effects Effects 0.000 claims abstract description 20
- 230000005684 electric field Effects 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000007423 decrease Effects 0.000 claims description 2
- 239000002800 charge carrier Substances 0.000 claims 7
- 239000012212 insulator Substances 0.000 claims 7
- 150000002500 ions Chemical class 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910007277 Si3 N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
Definitions
- the present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same, which is suitable for reducing a hot carrier effect.
- FIG. 1 illustrates a structure provided for reducing the hot carrier effect, wherein an N layer is formed on a drain/source junction to increase a resistance of a drain region for reducing an electric field.
- FIG. 1 illustrates a structure provided for reducing the hot carrier effect, wherein an N layer is formed on a drain/source junction to increase a resistance of a drain region for reducing an electric field.
- the gate fringing effect is an electric field leakage through a periphery of a gate electrode which becomes the greater as a size of an MOSFET device becomes the smaller. If LDD sidewall spacers formed of a material having a high electric permittivity, such as silicon nitride(Si 3 N 4 ), are provided at both sides of the gate electrode, enhancing the gate fringing effect further, the electric field in the drain region can be reduced.
- the material with a high electric permittivity such as silicon nitride employed for using the gate fringing effect
- the hot carrier is liable to be injected to the gate oxide film, that accelerates a device degradation, if the material with a high electric permittivity is used as the sidewall spacers.
- an additional silicon oxide film is formed between the gate and the sidewall spacer, which leads the fabrication process complicated.
- FIG. 3 illustrates a section of an MOSFET with a bent channel.
- An electric potential barrier is formed at the bent portion of the channel, which decreases an energy of the carrier passing through the barrier and reduces the hot carrier effect.
- this structure also has a problem of a complicated fabrication process due to the structure.
- the present invention is directed to a semiconductor device and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a semiconductor device and a method for fabricating the same, which can reduce the hot carrier effect.
- the semiconductor device having a gate electrode, a source electrode, and a drain electrode all of which are over a substrate, includes source/drain regions in regions of the substrate on both sides of the gate electrode, and a barrier block formed in a portion of each of the source/drain regions.
- a semiconductor device including a first conduction type substrate, a gate insulting film formed on a region of the first conduction type substrate, a gate electrode formed on the gate insulating film, second conduction type impurity regions formed in regions of the substrate on both sides of the gate electrode, a barrier block formed in a portion of each of the second conduction type impurity regions, and source/drain electrodes formed in contact with the second conduction type impurity regions, respectively.
- a method for fabricating a semiconductor device including the steps of (1) forming a gate insulting film on a region of a first conduction type substrate and a gate electrode on the gate insulating film, (2) injecting second conduction type impurity ions into the first conduction type substrate using the gate electrode as a mask, to form source/drain regions in regions of the substrate on both sides of the gate electrode, (3) forming sidewall spacers at both sides of the gate electrode, (4) injecting ions selected from oxygen, nitrogen, and a first conduction type impurity ions using the gate electrode and the sidewall spacers as a mask into a portion in each of surfaces of the source and the drain, to form a barrier block therein, and (5) forming source/drain electrode to be in contact with the source/drain regions.
- FIGS. 1, 2 and 3 illustrate sections showing structures of related art MOSFETs
- FIGS. 4a ⁇ 4d illustrate sections showing the steps of a method for fabricating an MOSFET in accordance with a preferred embodiment of the present invention
- FIG. 5 illustrates a section showing an MOSFET in accordance with a preferred embodiment of the present invention
- FIG. 6 illustrates a graph showing a comparison of drain characteristics of a related art LDD MOSFET without a barrier block and an MOSFET of the present invention with a barrier block;
- FIG. 7 illustrates a comparison of substrate current characteristics of a related art LDD MOSFET without a barrier block and an MOSFET of the present invention with a barrier block
- FIG. 8 illustrates a comparison of electric field characteristics in an MOSFET channel of a related art LDD MOSFET without a barrier block and an MOSFET of the present invention with a barrier block.
- FIGS. 4a ⁇ 4d illustrate sections showing the steps of a method for fabricating an MOSFET in accordance with a preferred embodiment of the present invention
- FIG. 5 illustrates a section showing an MOSFET in accordance with a preferred embodiment of the present invention.
- a gate oxide film 42 is deposited on a region of a p type substrate 41 and a gate electrode 43 is formed on the gate oxide film 42.
- n type impurity ions are injected to form a source 44 and a drain 45 in a surface of the substrate 41 on both sides of the gate electrode 43.
- sidewall spacers 46 of silicon oxide(SiO 2 ) are formed at sides of the gate electrode 43, and, as shown in FIG.
- the gate electrode 43 and the sidewall spacers 46 are used as a mask for injecting ions selected from oxygen, nitrogen, and p type impurity ions into a portion in each of surfaces of the source 44 and the drain 45, to form a barrier block 47 with a depth, therein. That is, the barrier block 47 is formed either by injecting ions of oxygen or nitrogen to form an insulating body with a high electric permittivity, such as silicon oxide(SiO 2 ) or silicon nitride(Si 3 N 4 ), or by doping with impurity of a type opposite to the impurity of the source/drain regions. Then, a source electrode. and a drain electrode(not shown) to be in contact with the source 44 and the drain 45 having the barrier blocks formed therein are formed, respectively.
- a source electrode. and a drain electrode(not shown) to be in contact with the source 44 and the drain 45 having the barrier blocks formed therein are formed, respectively.
- a semiconductor device with such barrier blocks substantially reduces generation of hot carriers because the device is involved in an electric field reduction due to the gate fringing effect as shown in the structure of FIG. 2 and has a current path formed around each of the barrier blocks that causes a series resistance greater.
- the barrier block 47 of an insulating body with a high electric permittivity increases an electric field fringing in the vicinity of edges of the drain 45, the hot carrier effect can be reduced, significantly. That is, the high field fringing effect of the insulating body of the silicon oxide or the silicon nitride in the vicinity of the barrier block reduces a high electric field in the vicinity of a drain junction, thereby suppressing generation of the hot carriers.
- a barrier block 47 doped with an impurity opposite to a type of an impurity doped in the source/drain acts as a barrier against a carrier flow
- the barrier block 47 can suppress generation of the hot carrier.
- the doping into the barrier region should be adequate to have a barrier height higher than approx. 0.5 eV.
- the barrier block formed by impurity doping has an electric permittivity the same with the silicon, though the electric filed reduction effect as high as a field fringing caused by a barrier block of an insulating body can not be expected, the barrier block formed by impurity doping is easy to use compared to the barrier block of the insulating body because the barrier block formed by impurity doping can be formed by using a doping process used in an existing MOS fabrication process.
- embodiments of the present invention take the cases of general MOSFETs as examples, the present invention is not limited to this, but applicable even to an LDD MOSFET.
- FIG. 5 illustrates a section showing an MOSFET in accordance with a preferred embodiment of the present invention.
- the MOSFET in accordance with a preferred embodiment of the present invention includes a gate insulating film 42 on a region of a p type substrate 41, a gate electrode 43 on the gate insulating film 42, a source 44 and a drain 45 in surfaces of the substrate 41 on both sides of the gate electrode 44, a barrier block 47 in a portion of each of the surfaces of the source 44 and the drain 45, and a source electrode and a drain electrode(not shown) in contact with the source 44 and the drain 45, respectively.
- FIG. 6 illustrates a graph showing a comparison of currents vs. voltages of drains of a related art LDD MOSFET without a barrier block and an MOSFET of the present invention with a barrier block.
- the gate voltage applied herein is approx. 2V.
- the MOSFET of the present invention with a barrier block has a device breakdown voltage coming later than the related art LDD MOSFET by more than 2V. This is because the carriers are difficult to obtain energies in the channel field, with a less impact ionization caused.
- FIG. 7 illustrates a comparison of substrate current characteristics of a related art LDD MOSFET without a barrier block and an MOSFET of the present invention with a barrier block, wherefrom it can be known that the barrier block of the present invention with an insulating body therein has a substrate current substantially smaller than the related art LDD MOSFET without a barrier block.
- FIG. 8 illustrates a comparison of electric field characteristics in an MOSFET channel of a related art LDD MOSFET without a barrier block and an MOSFET of the present invention with a barrier block, wherefrom it can be known that an electric field of the device of the present invention is significantly reduced in the vicinity of drain edges in a current path direction because a carrier flow of the device of the present invention deviates substantially from a channel field direction.
- the semiconductor device and the method for fabricating the same as has been explained has the following advantages.
- the semiconductor device of the present invention can reduce the hot carrier effect, thereby reducing a device degradation and significantly improving a device reliability.
- the simple process for embodying the semiconductor device of the present invention allows an easy application to an ULSI (Ultra-Large-Scale Integration) fabrication.
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Abstract
Description
Claims (22)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR19970072515 | 1997-12-23 | ||
KR97/72515 | 1997-12-23 | ||
KR98/21555 | 1998-06-10 | ||
KR1019980021555A KR100263710B1 (en) | 1997-12-23 | 1998-06-10 | Semiconductor device and method for fabricating the same |
Publications (1)
Publication Number | Publication Date |
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US6153909A true US6153909A (en) | 2000-11-28 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/217,202 Expired - Lifetime US6153909A (en) | 1997-12-23 | 1998-12-22 | Semiconductor device and method for fabricating the same |
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US (1) | US6153909A (en) |
KR (1) | KR100263710B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6559503B2 (en) * | 2000-11-02 | 2003-05-06 | Infineon Technologies Ag | Transistor with ESD protection |
US20050263817A1 (en) * | 2002-11-27 | 2005-12-01 | Martin Wendel | Transistor comprising fill areas in the source drain and/or drain region |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04326524A (en) * | 1991-04-26 | 1992-11-16 | Nec Corp | Semiconductor device |
US5338960A (en) * | 1992-08-05 | 1994-08-16 | Harris Corporation | Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures |
US5659197A (en) * | 1994-09-23 | 1997-08-19 | Vlsi Technology, Inc. | Hot-carrier shield formation for bipolar transistor |
US5793085A (en) * | 1993-02-26 | 1998-08-11 | Sgs-Thomson Microelectronics S.R.L. | Bipolar transistor compatible with CMOS processes |
US5834793A (en) * | 1985-12-27 | 1998-11-10 | Kabushiki Kaisha Toshiba | Semiconductor devices |
US5864160A (en) * | 1996-05-24 | 1999-01-26 | Advanced Micro Devices, Inc. | Transistor device with reduced hot carrier injection effects |
US5952701A (en) * | 1997-08-18 | 1999-09-14 | National Semiconductor Corporation | Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value |
-
1998
- 1998-06-10 KR KR1019980021555A patent/KR100263710B1/en not_active IP Right Cessation
- 1998-12-22 US US09/217,202 patent/US6153909A/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5834793A (en) * | 1985-12-27 | 1998-11-10 | Kabushiki Kaisha Toshiba | Semiconductor devices |
JPH04326524A (en) * | 1991-04-26 | 1992-11-16 | Nec Corp | Semiconductor device |
US5338960A (en) * | 1992-08-05 | 1994-08-16 | Harris Corporation | Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures |
US5793085A (en) * | 1993-02-26 | 1998-08-11 | Sgs-Thomson Microelectronics S.R.L. | Bipolar transistor compatible with CMOS processes |
US5659197A (en) * | 1994-09-23 | 1997-08-19 | Vlsi Technology, Inc. | Hot-carrier shield formation for bipolar transistor |
US5864160A (en) * | 1996-05-24 | 1999-01-26 | Advanced Micro Devices, Inc. | Transistor device with reduced hot carrier injection effects |
US5952701A (en) * | 1997-08-18 | 1999-09-14 | National Semiconductor Corporation | Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value |
Non-Patent Citations (2)
Title |
---|
Tasch et al. "Limitations of LDD Types of Structures in Deep-Submicrometer MOS Technology" IEEE Electron Device Letters, vol. 11, No. II, Nov. 1990, pp. 517-519. |
Tasch et al. Limitations of LDD Types of Structures in Deep Submicrometer MOS Technology IEEE Electron Device Letters, vol. 11, No. II, Nov. 1990, pp. 517 519. * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6559503B2 (en) * | 2000-11-02 | 2003-05-06 | Infineon Technologies Ag | Transistor with ESD protection |
US20050263817A1 (en) * | 2002-11-27 | 2005-12-01 | Martin Wendel | Transistor comprising fill areas in the source drain and/or drain region |
DE10255359B4 (en) * | 2002-11-27 | 2008-09-04 | Infineon Technologies Ag | Transistor with filling areas in the source and / or drain region |
Also Published As
Publication number | Publication date |
---|---|
KR19990062425A (en) | 1999-07-26 |
KR100263710B1 (en) | 2000-09-01 |
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