US6010940A - Methods for fabricating CVD TiN barrier layers for capacitor structures - Google Patents

Methods for fabricating CVD TiN barrier layers for capacitor structures Download PDF

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US6010940A
US6010940A US08/935,464 US93546497A US6010940A US 6010940 A US6010940 A US 6010940A US 93546497 A US93546497 A US 93546497A US 6010940 A US6010940 A US 6010940A
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capacitor
barrier layer
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Myoung-Bum Lee
Hyeon-deok Lee
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising transition metals

Definitions

  • the present invention relates to the field of integrated circuits and more particularly to methods of forming barrier layers for capacitor structures.
  • a barrier layer may be needed to reduce reactions between the polysilicon electrode and the tantalum pentoxide dielectric layer.
  • Titanium nitride (TiN) layers formed using physical vapor deposition (PVD) have been used to provide a barrier layer between polysilicon electrodes and tantalum pentoxide dielectric layers.
  • PVD TiN barrier layer may not provide a sufficiently uniform thickness when used with capacitors having complicated structures such as cylindrical structures, multiple fin structures, or stacked hemispherical grain (HSG) structures.
  • HSG stacked hemispherical grain
  • a barrier layer generally requires a uniform thickness across even and uneven portions of a dielectric layer.
  • a PVD TiN barrier layer may thus be unsuitable for use with more complicated capacitor structures.
  • TiN layers formed using chemical vapor deposition have been used to separate silicon substrates and aluminum layers. According to this method, however, the resistance of the TiN layer may be increased due to the chlorine (Cl) in the titanium tetrachloride (TiCl 4 ) used as the source gas. In particular, this chlorine may remain in the TiN layer after the deposition thereof thereby increasing the resistance of the TiN layer.
  • a method for removing the Chlorine (Cl) from the TiN layer has been discussed in U.S. Pat. No. 5,279,857, the disclosure of which is hereby incorporated herein in its entirety by reference.
  • a TiN layer is formed using a low pressure chemical vapor deposition (LPCVD) process, and the TiN layer is then annealed in an atmosphere of NH 3 gas. More particularly, the TiN layer is formed on a silicon substrate using TiCl 4 , and then the Chlorine in the TiN layer is reduced through a post annealing process in an atmosphere of NH 3 gas, thereby reducing the sheet resistance of the TiN layer.
  • LPCVD low pressure chemical vapor deposition
  • the inventor has found that when a TiN layer is formed on a dielectric layer using a chemical vapor deposition (CVD) method with TiCl 4 gas as a source, chlorine (Cl) may remain in the TiN layer thereby increasing the leakage current and increasing the equivalent oxide layer thickness.
  • the TiCl 4 source gas used in the chemical vapor deposition may react with the dielectric layer thereby forming an oxide layer at an interface between the dielectric layer and the TiN layer. This oxide layer may increase the equivalent oxide layer thickness.
  • chlorine (Cl) may remain in the TiN layer after the deposition thereof in the form of TiCl x . This TiCl x may react with the Ta 2 O 5 thereby forming TiO x at the interface between the dielectric layer and the TiN layer.
  • a method of fabricating a capacitor includes the steps of forming a lower capacitor electrode on an integrated circuit substrate, and forming a dielectric layer on the lower capacitor electrode opposite the integrated circuit substrate.
  • a titanium nitride barrier layer is chemical vapor deposited on the dielectric layer opposite the integrated circuit substrate to a thickness in the range of 50 ⁇ to 500 ⁇ using TiCl 4 as a source gas.
  • the titanium nitride barrier layer is then annealed, and an upper electrode is formed on the titanium nitride barrier layer opposite the integrated circuit substrate.
  • the dielectric layer can be a Ta 2 O 5 layer, and the barrier layer can have a thickness in the range of 100 ⁇ to 300 ⁇ .
  • the annealing step can be performed in atmosphere of NH 3 gas thereby reducing chlorine in the titanium nitride barrier layer. In particular, the chlorine may be removed in the form of hydrogen chloride gas.
  • the chemical vapor depositing step and the annealing step can be performed in a common reaction chamber thereby reducing the process time and handling requirements. In other words, the chemical vapor depositing step and the annealing step can be performed in-situ.
  • the chemical vapor depositing step can be performed using a low pressure chemical vapor deposition (LPCVD) system, a plasma enhanced chemical vapor deposition (PECVD) system, or an electron cyclotron resonance chemical vapor deposition (ECRCVD) system.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ERCVD electron cyclotron resonance chemical vapor deposition
  • the lower capacitor electrode can have a stack structure, a cylindrical structure, a multiple fin structure, or a hemispherical grain (HSG) structure.
  • improved capacitors can thus be provided for integrated circuit devices. Moreover, a desired capacitance can be provided in a highly integrated circuit device.
  • FIG. 1 is a graph illustrating leakage current densities as a function of a thickness of a TiN barrier layer for capacitors formed according to the present invention.
  • FIG. 2 is a graph illustrating equivalent oxide layer thicknesses of a capacitor as a function of a thickness of a TiN barrier layer for capacitors formed according to the present invention.
  • FIG. 3 is a plot illustrating a comparison of equivalent oxide layer thicknesses vs. thicknesses of a TiN barrier layer and annealing times for capacitors formed according to the present invention.
  • FIG. 4 is a graph obtained using thermal deposition spectroscopy (TDS) illustrating a comparison of the Chlorine content of a TiN barrier layer vs. thicknesses of the TiN barrier layer for different annealing times.
  • TDS thermal deposition spectroscopy
  • FIG. 5 is a graph illustrating thermodynamic reactivity of TiCl x remaining in a TiN layer with Ta 2 O 5 for capacitors formed according to the present invention.
  • FIG. 6 is a cross sectional view illustrating a capacitor formed according to a method of the present invention.
  • capacitor dielectric characteristics are influenced by the thickness of a TiN barrier layer formed by chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the TiCl 4 may react with oxygen in a dielectric layer such as a Ta 2 O 5 layer, thereby forming a TiO x layer at the interface between the Ta 2 O 5 layer and the TiN layer.
  • This TiO x layer may cause an increase in the equivalent oxide layer thickness reducing capacitance. It is thus preferable that the thickness of the TiO x layer is reduced.
  • Chlorine in the CVD TiN layer may generate TiCl x which may react with TaO thereby forming an oxide layer such as TiO x , and Chlorine remaining in the barrier layer may increase the leakage current density. It is thus preferred to reduce Cl in the CVD TiN layer.
  • a thickness of the TiO x layer increases as the deposition time of the TiN layer and the thickness of the TiN layer increase. It has also been found that the thickness of the TiO x layer can be reduced when the thickness of the TiN layer was in the range of 50 ⁇ to 500 ⁇ . It has also been found that when the thickness of the TiN layer is in the range of 50 ⁇ to 500 ⁇ , Chlorine in the TiN barrier layer can be more effectively removed.
  • the TiN barrier layer is formed on a capacitor dielectric layer to have a thickness in the range of 50 ⁇ to 500 ⁇ , and preferably to have a thickness in the range of 100 ⁇ to 300 ⁇ .
  • Barrier layers formed according to the present invention will now be described with reference to graphs illustrating experimental result as follows.
  • FIGS. 1 through 4 illustrate experimental results of samples fabricated according to the present invention wherein leakage current density, equivalent oxide layer thickness, and Chlorine content in the TiN barrier layer are plotted as a function of the thickness of the CVD TiN layer.
  • doped polysilicon was deposited to a thickness of approximately 8000 ⁇ to form lower capacitor electrodes, and layers of Ta 2 O 5 were deposited on the lower capacitor electrodes to a thickness of approximately 120 ⁇ to provide capacitor dielectric layers.
  • the leakage current densities and the equivalent oxide layer thicknesses were measured at a reference voltage of 1.5V.
  • the curve a indicates samples where the CVD TiN layers were formed and then annealed in an atmosphere of nitrogen gas (nitrogen annealing).
  • the curve b indicates samples where the CVD TiN layers were annealed in an atmosphere of NH 3 gas (NH 3 annealing).
  • the leakage current density is reduced as the TiN layer thickness increases. With TiN layer thicknesses greater than 300 ⁇ , however, there is relatively little change in the leakage current density. In addition, the leakage current densities for capacitors formed using the nitrogen anneal a was higher than that for capacitors formed using the NH 3 anneal b.
  • the equivalent oxide layer thickness increases as the TiN layer thickness increases. This relationship may be due to a reaction between the TiCl 4 and the Ta 2 O 5 dielectric layer thereby forming TiO x at the interface between the TiN barrier layer and the Ta 2 O 5 dielectric layer when forming the TiN barrier layer.
  • the equivalent oxide layer thickness was thicker for capacitors formed using the nitrogen anneal a than for capacitors formed using the NH 3 anneal b. This may be because the remaining chlorine content in the TiN layer when using a nitrogen anneal is higher than the remaining chlorine content when using an NH 3 anneal. Accordingly, less chlorine may be available as TiCl x to react with the Ta 2 O 5 dielectric layer to form TiO x at the interface between the barrier and dielectric layers.
  • the leakage current density for capacitors formed using the NH 3 anneal b was lower than that for capacitors formed using the nitrogen anneal a even though the equivalent oxide layer thickness for capacitors formed using the NH 3 anneal b was less than that for capacitors formed using the nitrogen anneal a.
  • the equivalent oxide layer thickness increases, the leakage current density decreases. This result seems to occur because chlorine is more effectively removed from the TiN barrier layer through an NH 3 anneal, thereby lessening the chlorine content remaining in the TiN layer.
  • FIG. 3 shows results obtained by measuring each equivalent oxide layer thickness after performing NH 3 annealing steps for 30 seconds and 60 seconds on samples in which the Ta 2 O 5 dielectric layers were 120 ⁇ thick and the TiN barrier layers were 100 ⁇ , 300 ⁇ or 500 ⁇ thick. For purposes of comparison, samples with the same thicknesses of layers were annealed using nitrogen for 30 seconds. Five samples of each TiN layer thickness were measured.
  • the equivalent oxide layer thickness increases as the thickness of the TiN barrier layer increases. It has been known that when the equivalent oxide layer thickness in the 100 ⁇ TiN layer was compared with that in the 500 ⁇ TiN layer, the equivalent oxide layer thickness in the 500 ⁇ TiN layer was much greater given the same annealing time conditions. As discussed above, this result may be because as the TiN layer was thicker, more TiO x may be formed at the interface between the TiN layer and the Ta 2 O 5 layer. For example, when the thickness of the TiN layer was 300 ⁇ , as annealing time is lengthened, the thickness of the equivalent oxide layer is reduced for longer anneal times. That is, the equivalent oxide layer thickness obtained after annealing for 60 seconds is less than that obtained after annealing for 30 seconds. It seems that this result occurs because chlorine was removed from the CVD TiN layer through annealing, thereby constraining the interface reaction.
  • FIG. 4 illustrates the chlorine content in TiN barrier layers as a function of NH 3 anneal time for various TiN layer thicknesses.
  • the chlorine content (Y-axis) in the TiN barrier layer designates relative evaluation. As shown in FIG. 4, the chlorine content increases as the TiN layer thickness increases when using the same anneal time. Furthermore, the chlorine content decreases as the anneal time increases for the same TiN barrier layer thickness. In the case where the thickness of the TiN barrier layer was 500 ⁇ and NH 3 anneal was performed for 30 seconds, the chlorine content was more than 5 times that of the case where the TiN barrier layer was 100 ⁇ .
  • the chlorine content was greater than that when the TiN layer was 300 ⁇ thick and the anneal was performed for 30 seconds.
  • the chlorine content after the annealing was performed for 30 seconds was similar to that when the TiN layer was 300 ⁇ thick and the anneal was not performed.
  • FIG. 5 is a graph illustrating the thermodynamic reactivity of Chlorine remaining as TiCl x in a CVD-TiN layer with a Ta 2 O 5 dielectric layer.
  • the x-axis indicates reaction temperature
  • the y-axis indicates Gibbs free energy
  • plots (1), (2), (3), and (4) indicate each Gibbs free energy curve with respect to the cases that Chlorine remaining in the TiN layer becomes 5TiCl, (5/2)TiCl, (3/10)TiCl, and 3TiCl, respectively.
  • the Gibbs free energy has a negative value, and that the larger the absolute value of the Gibbs free energy is, the greater the reactivity becomes.
  • the thermodynamic reactivity of Ta 2 O 5 with TiCl x is high. Also, the lower the temperature is, the higher the reactivity becomes.
  • the TiO x formed by the reaction of TiCl x with Ta 2 O 5 increases the equivalent oxide layer thickness, and the surplus Chlorine increases the leakage current density.
  • the equivalent oxide layer thickness increased, and more chlorine remained in the TiN layer as the TiN layer thickness increased. Accordingly, if the TiN layer thickness is maintained within a predetermined range such as 50 ⁇ to 500 ⁇ , and if the TiN layer is annealed using NH 3 , the chlorine content in the TiN layer can be reduced so that the equivalent oxide layer thickness of a capacitor dielectric layer can be reduced and the leakage current density can be reduced.
  • a minimum thickness of the TiN layer may be set to approximately 50 ⁇ , which is sufficient to allow the TiN layer to serve as a barrier layer, and to reduce reaction of the polysilicon layer with the Ta 2 O 5 dielectric layer.
  • a maximum thickness of the TiN layer may be set to approximately 500 ⁇ , which is a level sufficient to obtain the equivalent oxide layer thickness capable of securing an appropriate capacitance value, and to appropriately decrease the leakage current density by significantly reducing Cl in the layer.
  • An interlayer dielectric layer 12 is formed on a semiconductor substrate 10 where a sub-structure such as a transistor, is formed.
  • a memory cell access transistor for a dynamic random access memory (DRAM) device cell can be formed in the semiconductor substrate.
  • the interlayer dielectric layer 12 is then patterned to form a contact hole therein exposing part of the semiconductor substrate 10.
  • the contact hole can expose a source/drain region of a memory cell access transistor.
  • a layer of a conductive material such as doped polysilicon is deposited on the surface of the interlayer dielectric layer and in the contact hole, and this conductive layer is patterned to form a lower capacitor electrode 14.
  • a material such as Ta 2 O 5 having a relatively high dielectric constant is deposited on the lower capacitor electrode 14 and on the interlayer dielectric layer to a thickness of approximately 120 ⁇ thereby forming dielectric layer 16.
  • a TiN barrier layer 18 is formed using a chemical vapor deposition (CVD) with TiCl 4 and NH 3 as source gases.
  • this TiN barrier layer is preferably deposited to a thickness in the range of 50 ⁇ to 500 ⁇ , and most preferably in the range of 100 ⁇ to 300 ⁇ .
  • the structure including the TiN barrier layer is then in-situ annealed for a predetermined time, for example, 30 seconds to 60 seconds.
  • the anneal step and the step of depositing the TiN barrier layer are preferably performed in the same chamber.
  • the annealing step is preferably performed in atmosphere of NH 3 , so that chlorine in the TiN barrier layer reacts with hydrogen and is volatilized as hydrogen chloride (HCl).
  • a layer of a conductive material such as doped polysilicon is then deposited on the TiN barrier layer 18, and this conductive layer can be patterned to provide an upper capacitor electrode 20.
  • the lower capacitor electrode 14 can have a stack structure.
  • TiN barrier layers formed according to the present invention can also be used with lower capacitor electrodes having more complicated structures such as cylindrical structures, multiple fin structures, or stack structures with hemispherical grains (HSG).
  • HSG hemispherical grains
  • the dielectric layer can be formed from material such as tantalum oxide having a relatively high dielectric constant.
  • the lower electrode having a complicated structure can be employed thereby increasing capacitance.
  • the thickness of the TiN barrier layer is formed within a predetermined range, thereby reducing the equivalent oxide layer thickness of a capacitor dielectric layer. The chlorine content in the TiN barrier layer can also be reduced thereby reducing the leakage current density.

Abstract

A method of fabricating a capacitor for a integrated circuit device includes the steps of forming a lower capacitor electrode on an integrated circuit substrate, and forming a dielectric layer on the lower capacitor electrode opposite the integrated circuit substrate. A titanium nitride barrier layer is deposited by chemical vapor deposition on the dielectric layer opposite the integrated circuit substrate to a thickness in the range of 50 Å to 500 Å using TiCl4 as a source gas. The titanium nitride barrier layer is annealed, and an upper electrode is formed on the titanium nitride barrier layer opposite the integrated circuit substrate.

Description

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits and more particularly to methods of forming barrier layers for capacitor structures.
BACKGROUND OF THE INVENTION
As integrated circuit memory devices such as dynamic random access memory (DRAM) devices have become more highly integrated, the space available for memory cell capacitors has been reduced. Accordingly, there is a need to provide a capacitor on a smaller area while maintaining a predetermined capacitance. In response to this need, materials having relatively high dielectric constants have been used to provide capacitor dielectric layers thereby increasing capacitances. In particular, tantalum pentoxide (Ta2 O5) layers have been used, and tantalum pentoxide has good step coverage on complicated lower electrode structures.
When using a material having a high dielectric constant such as tantalum pentoxide to provide a capacitor dielectric layer together with a polysilicon capacitor upper electrode, however, a barrier layer may be needed to reduce reactions between the polysilicon electrode and the tantalum pentoxide dielectric layer. Titanium nitride (TiN) layers formed using physical vapor deposition (PVD) have been used to provide a barrier layer between polysilicon electrodes and tantalum pentoxide dielectric layers. A PVD TiN barrier layer, however, may not provide a sufficiently uniform thickness when used with capacitors having complicated structures such as cylindrical structures, multiple fin structures, or stacked hemispherical grain (HSG) structures. As will be understood by one having skill in the art, a barrier layer generally requires a uniform thickness across even and uneven portions of a dielectric layer. A PVD TiN barrier layer may thus be unsuitable for use with more complicated capacitor structures.
TiN layers formed using chemical vapor deposition have been used to separate silicon substrates and aluminum layers. According to this method, however, the resistance of the TiN layer may be increased due to the chlorine (Cl) in the titanium tetrachloride (TiCl4) used as the source gas. In particular, this chlorine may remain in the TiN layer after the deposition thereof thereby increasing the resistance of the TiN layer.
A method for removing the Chlorine (Cl) from the TiN layer has been discussed in U.S. Pat. No. 5,279,857, the disclosure of which is hereby incorporated herein in its entirety by reference. As discussed in this patent, a TiN layer is formed using a low pressure chemical vapor deposition (LPCVD) process, and the TiN layer is then annealed in an atmosphere of NH3 gas. More particularly, the TiN layer is formed on a silicon substrate using TiCl4, and then the Chlorine in the TiN layer is reduced through a post annealing process in an atmosphere of NH3 gas, thereby reducing the sheet resistance of the TiN layer.
SUMMARY OF THE INVENTION
It is therefor an object of the present invention to provide improved method for forming integrated circuit capacitors.
It is another object of the present invention to provide improved methods for forming barrier layers for integrated circuit capacitors.
These and other objects are provided according to the present invention by methods including the steps of chemical vapor depositing a titanium nitride barrier layer on a dielectric layer to a thickness in the range of 50 Å to 500 Å using TiCl4 as a source gas, and annealing the titanium nitride barrier layer. By using chemical vapor deposition to form the TiN barrier layer within the range of thicknesses discussed above, the reaction between the TiCl4 source gas and the dielectric layer can be reduced thereby reducing the thickness of any TiOx layer at an interface between the dielectric layer and the TiN layer and also reducing the equivalent oxide layer thickness. In addition, Chlorine in the TiN barrier layer can be more effectively removed thereby reducing leakage currents.
The inventor has found that when a TiN layer is formed on a dielectric layer using a chemical vapor deposition (CVD) method with TiCl4 gas as a source, chlorine (Cl) may remain in the TiN layer thereby increasing the leakage current and increasing the equivalent oxide layer thickness. The TiCl4 source gas used in the chemical vapor deposition may react with the dielectric layer thereby forming an oxide layer at an interface between the dielectric layer and the TiN layer. This oxide layer may increase the equivalent oxide layer thickness. In addition, after the CVD TiN layer is formed, chlorine (Cl) may remain in the TiN layer after the deposition thereof in the form of TiClx. This TiClx may react with the Ta2 O5 thereby forming TiOx at the interface between the dielectric layer and the TiN layer.
The methods of the present invention can thus be used to provide capacitors for integrated circuit devices. In particular, a method of fabricating a capacitor includes the steps of forming a lower capacitor electrode on an integrated circuit substrate, and forming a dielectric layer on the lower capacitor electrode opposite the integrated circuit substrate. A titanium nitride barrier layer is chemical vapor deposited on the dielectric layer opposite the integrated circuit substrate to a thickness in the range of 50 Å to 500 Å using TiCl4 as a source gas. The titanium nitride barrier layer is then annealed, and an upper electrode is formed on the titanium nitride barrier layer opposite the integrated circuit substrate.
The dielectric layer can be a Ta2 O5 layer, and the barrier layer can have a thickness in the range of 100 Å to 300 Å. In addition, the annealing step can be performed in atmosphere of NH3 gas thereby reducing chlorine in the titanium nitride barrier layer. In particular, the chlorine may be removed in the form of hydrogen chloride gas. Moreover, the chemical vapor depositing step and the annealing step can be performed in a common reaction chamber thereby reducing the process time and handling requirements. In other words, the chemical vapor depositing step and the annealing step can be performed in-situ.
The chemical vapor depositing step can be performed using a low pressure chemical vapor deposition (LPCVD) system, a plasma enhanced chemical vapor deposition (PECVD) system, or an electron cyclotron resonance chemical vapor deposition (ECRCVD) system. In addition, the lower capacitor electrode can have a stack structure, a cylindrical structure, a multiple fin structure, or a hemispherical grain (HSG) structure.
By using the methods of the present invention, improved capacitors can thus be provided for integrated circuit devices. Moreover, a desired capacitance can be provided in a highly integrated circuit device.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a graph illustrating leakage current densities as a function of a thickness of a TiN barrier layer for capacitors formed according to the present invention.
FIG. 2 is a graph illustrating equivalent oxide layer thicknesses of a capacitor as a function of a thickness of a TiN barrier layer for capacitors formed according to the present invention.
FIG. 3 is a plot illustrating a comparison of equivalent oxide layer thicknesses vs. thicknesses of a TiN barrier layer and annealing times for capacitors formed according to the present invention.
FIG. 4 is a graph obtained using thermal deposition spectroscopy (TDS) illustrating a comparison of the Chlorine content of a TiN barrier layer vs. thicknesses of the TiN barrier layer for different annealing times.
FIG. 5 is a graph illustrating thermodynamic reactivity of TiClx remaining in a TiN layer with Ta2 O5 for capacitors formed according to the present invention.
FIG. 6 is a cross sectional view illustrating a capacitor formed according to a method of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.
The inventor has found that capacitor dielectric characteristics, such as leakage currents and equivalent oxide layer thicknesses, are influenced by the thickness of a TiN barrier layer formed by chemical vapor deposition (CVD). In particular, when TiCl4 is used as a source gas when forming a TiN layer by chemical vapor deposition, the TiCl4 may react with oxygen in a dielectric layer such as a Ta2 O5 layer, thereby forming a TiOx layer at the interface between the Ta2 O5 layer and the TiN layer. This TiOx layer may cause an increase in the equivalent oxide layer thickness reducing capacitance. It is thus preferable that the thickness of the TiOx layer is reduced. In addition, Chlorine in the CVD TiN layer may generate TiClx which may react with TaO thereby forming an oxide layer such as TiOx, and Chlorine remaining in the barrier layer may increase the leakage current density. It is thus preferred to reduce Cl in the CVD TiN layer.
It has been found by the inventor that a thickness of the TiOx layer increases as the deposition time of the TiN layer and the thickness of the TiN layer increase. It has also been found that the thickness of the TiOx layer can be reduced when the thickness of the TiN layer was in the range of 50 Å to 500 Å. It has also been found that when the thickness of the TiN layer is in the range of 50 Å to 500 Å, Chlorine in the TiN barrier layer can be more effectively removed.
According to an embodiment of the present invention, the TiN barrier layer is formed on a capacitor dielectric layer to have a thickness in the range of 50 Å to 500 Å, and preferably to have a thickness in the range of 100 Å to 300 Å. Barrier layers formed according to the present invention will now be described with reference to graphs illustrating experimental result as follows. In particular, FIGS. 1 through 4 illustrate experimental results of samples fabricated according to the present invention wherein leakage current density, equivalent oxide layer thickness, and Chlorine content in the TiN barrier layer are plotted as a function of the thickness of the CVD TiN layer.
For FIGS. 1 and 2, doped polysilicon was deposited to a thickness of approximately 8000 Å to form lower capacitor electrodes, and layers of Ta2 O5 were deposited on the lower capacitor electrodes to a thickness of approximately 120 Å to provide capacitor dielectric layers. TiN layers having respective thicknesses of 100 Å, 300 Å, and 500 Å, were then chemical vapor deposited on the capacitor dielectric layers using TiCl4 and NH3 on each of the Ta2 O5 dielectric layers. The leakage current densities and the equivalent oxide layer thicknesses were measured at a reference voltage of 1.5V. The curve a indicates samples where the CVD TiN layers were formed and then annealed in an atmosphere of nitrogen gas (nitrogen annealing). The curve b indicates samples where the CVD TiN layers were annealed in an atmosphere of NH3 gas (NH3 annealing).
As shown in FIG. 1, the leakage current density is reduced as the TiN layer thickness increases. With TiN layer thicknesses greater than 300 Å, however, there is relatively little change in the leakage current density. In addition, the leakage current densities for capacitors formed using the nitrogen anneal a was higher than that for capacitors formed using the NH3 anneal b.
As shown in FIG. 2, the equivalent oxide layer thickness increases as the TiN layer thickness increases. This relationship may be due to a reaction between the TiCl4 and the Ta2 O5 dielectric layer thereby forming TiOx at the interface between the TiN barrier layer and the Ta2 O5 dielectric layer when forming the TiN barrier layer. In addition, the equivalent oxide layer thickness was thicker for capacitors formed using the nitrogen anneal a than for capacitors formed using the NH3 anneal b. This may be because the remaining chlorine content in the TiN layer when using a nitrogen anneal is higher than the remaining chlorine content when using an NH3 anneal. Accordingly, less chlorine may be available as TiClx to react with the Ta2 O5 dielectric layer to form TiOx at the interface between the barrier and dielectric layers.
As a result, in the case that the TiN barrier layer is 500 Å thick, for example, the leakage current density for capacitors formed using the NH3 anneal b was lower than that for capacitors formed using the nitrogen anneal a even though the equivalent oxide layer thickness for capacitors formed using the NH3 anneal b was less than that for capacitors formed using the nitrogen anneal a. This result is contrary to the conventional wisdom that as the equivalent oxide layer thickness increases, the leakage current density decreases. This result seems to occur because chlorine is more effectively removed from the TiN barrier layer through an NH3 anneal, thereby lessening the chlorine content remaining in the TiN layer.
FIG. 3 shows results obtained by measuring each equivalent oxide layer thickness after performing NH3 annealing steps for 30 seconds and 60 seconds on samples in which the Ta2 O5 dielectric layers were 120 Å thick and the TiN barrier layers were 100 Å, 300 Å or 500 Å thick. For purposes of comparison, samples with the same thicknesses of layers were annealed using nitrogen for 30 seconds. Five samples of each TiN layer thickness were measured.
As shown in FIG. 3, the equivalent oxide layer thickness increases as the thickness of the TiN barrier layer increases. It has been known that when the equivalent oxide layer thickness in the 100 Å TiN layer was compared with that in the 500 Å TiN layer, the equivalent oxide layer thickness in the 500 Å TiN layer was much greater given the same annealing time conditions. As discussed above, this result may be because as the TiN layer was thicker, more TiOx may be formed at the interface between the TiN layer and the Ta2 O5 layer. For example, when the thickness of the TiN layer was 300 Å, as annealing time is lengthened, the thickness of the equivalent oxide layer is reduced for longer anneal times. That is, the equivalent oxide layer thickness obtained after annealing for 60 seconds is less than that obtained after annealing for 30 seconds. It seems that this result occurs because chlorine was removed from the CVD TiN layer through annealing, thereby constraining the interface reaction.
FIG. 4 illustrates the chlorine content in TiN barrier layers as a function of NH3 anneal time for various TiN layer thicknesses. The chlorine content (Y-axis) in the TiN barrier layer designates relative evaluation. As shown in FIG. 4, the chlorine content increases as the TiN layer thickness increases when using the same anneal time. Furthermore, the chlorine content decreases as the anneal time increases for the same TiN barrier layer thickness. In the case where the thickness of the TiN barrier layer was 500 Å and NH3 anneal was performed for 30 seconds, the chlorine content was more than 5 times that of the case where the TiN barrier layer was 100 Å.
When the TiN layer was 500 Å thick and the anneal was performed for 60 seconds, the chlorine content was greater than that when the TiN layer was 300 Å thick and the anneal was performed for 30 seconds. When the TiN layer was 500 Å thick, the chlorine content after the annealing was performed for 30 seconds was similar to that when the TiN layer was 300 Å thick and the anneal was not performed.
FIG. 5 is a graph illustrating the thermodynamic reactivity of Chlorine remaining as TiClx in a CVD-TiN layer with a Ta2 O5 dielectric layer. Here, the x-axis indicates reaction temperature, the y-axis indicates Gibbs free energy, and plots (1), (2), (3), and (4) indicate each Gibbs free energy curve with respect to the cases that Chlorine remaining in the TiN layer becomes 5TiCl, (5/2)TiCl, (3/10)TiCl, and 3TiCl, respectively.
In general, it is understood that the Gibbs free energy has a negative value, and that the larger the absolute value of the Gibbs free energy is, the greater the reactivity becomes. As can be seen from FIG. 5, the thermodynamic reactivity of Ta2 O5 with TiClx is high. Also, the lower the temperature is, the higher the reactivity becomes. The respective reaction will be described as follows;
(1) Ta2 O5 +5 TiCl→TiO+2 Ta+(5/2) Cl2
(2) Ta2 O5 +(5/2) TiCl→(5/2) TiO2 +2 Ta+(5/4) Cl2
(3) Ta2 O5 +(3/10) TiCl→(5/3) Ti2 O3 +2 Ta+(5/3) Cl2
(4) Ta2 O5 +3 TiCl→Ti3 O5 +2 Ta+(3/2) Cl2
As described above, the TiOx formed by the reaction of TiClx with Ta2 O5 increases the equivalent oxide layer thickness, and the surplus Chlorine increases the leakage current density.
According to the experimental results illustrated in FIGS. 1 through 5, as the TiN layer became thicker, the equivalent oxide layer thickness increased, and more chlorine remained in the TiN layer as the TiN layer thickness increased. Accordingly, if the TiN layer thickness is maintained within a predetermined range such as 50 Å to 500 Å, and if the TiN layer is annealed using NH3, the chlorine content in the TiN layer can be reduced so that the equivalent oxide layer thickness of a capacitor dielectric layer can be reduced and the leakage current density can be reduced.
Here, a minimum thickness of the TiN layer may be set to approximately 50 Å, which is sufficient to allow the TiN layer to serve as a barrier layer, and to reduce reaction of the polysilicon layer with the Ta2 O5 dielectric layer. In addition, a maximum thickness of the TiN layer may be set to approximately 500 Å, which is a level sufficient to obtain the equivalent oxide layer thickness capable of securing an appropriate capacitance value, and to appropriately decrease the leakage current density by significantly reducing Cl in the layer.
Referring to FIG. 6, a capacitor fabricated according to an embodiment of the present invention will be described. An interlayer dielectric layer 12 is formed on a semiconductor substrate 10 where a sub-structure such as a transistor, is formed. In particular, a memory cell access transistor for a dynamic random access memory (DRAM) device cell can be formed in the semiconductor substrate. The interlayer dielectric layer 12 is then patterned to form a contact hole therein exposing part of the semiconductor substrate 10. For example, the contact hole can expose a source/drain region of a memory cell access transistor.
A layer of a conductive material such as doped polysilicon is deposited on the surface of the interlayer dielectric layer and in the contact hole, and this conductive layer is patterned to form a lower capacitor electrode 14. A material such as Ta2 O5 having a relatively high dielectric constant is deposited on the lower capacitor electrode 14 and on the interlayer dielectric layer to a thickness of approximately 120 Å thereby forming dielectric layer 16.
A TiN barrier layer 18 is formed using a chemical vapor deposition (CVD) with TiCl4 and NH3 as source gases. In particular, this TiN barrier layer is preferably deposited to a thickness in the range of 50 Å to 500 Å, and most preferably in the range of 100 Å to 300 Å.
The structure including the TiN barrier layer is then in-situ annealed for a predetermined time, for example, 30 seconds to 60 seconds. The anneal step and the step of depositing the TiN barrier layer are preferably performed in the same chamber. The annealing step is preferably performed in atmosphere of NH3, so that chlorine in the TiN barrier layer reacts with hydrogen and is volatilized as hydrogen chloride (HCl). A layer of a conductive material such as doped polysilicon is then deposited on the TiN barrier layer 18, and this conductive layer can be patterned to provide an upper capacitor electrode 20.
As shown in FIG. 6, the lower capacitor electrode 14 can have a stack structure. TiN barrier layers formed according to the present invention, however, can also be used with lower capacitor electrodes having more complicated structures such as cylindrical structures, multiple fin structures, or stack structures with hemispherical grains (HSG).
According to the present invention, since the barrier layer can be formed through a CVD process, the dielectric layer can be formed from material such as tantalum oxide having a relatively high dielectric constant. At the same time, the lower electrode having a complicated structure can be employed thereby increasing capacitance. Also, the thickness of the TiN barrier layer is formed within a predetermined range, thereby reducing the equivalent oxide layer thickness of a capacitor dielectric layer. The chlorine content in the TiN barrier layer can also be reduced thereby reducing the leakage current density.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims (5)

That which is claimed is:
1. A method of fabricating a capacitor for an integrated circuit device, said method comprising the steps of:
forming a lower capacitor electrode on an integrated circuit substrate;
forming a Ta2 O5 capacitor dielectric layer on said lower capacitor electrode opposite said integrated circuit substrate;
chemical vapor depositing a titanium nitride barrier layer on said Ta2 O5 capacitor dielectric layer opposite said lower capacitor electrode to a thickness in the range of 50 Å to 500 Å using TiCl4 as a source gas to reduce formation of TiOx at an interface between said Ta2 O5 capacitor dielectric layer and said titanium nitride barrier layer as a result of reaction of said TiCl4 with said Ta2 O5 capacitor dielectric layer, thereby reducing an equivalent oxide thickness of a resulting capacitor;
annealing said chemical vapor deposited titanium nitride barrier layer in an atmosphere of NH3 gas to reduce a leakage current density of the resulting capacitor; and
forming an upper capacitor electrode on said annealed chemical vapor deposited titanium nitride barrier layer opposite said integrated circuit substrate.
2. A method according to claim 1 wherein said barrier layer has a thickness in the range of 100 Å to 300 Å.
3. A method according to claim 1 wherein said lower capacitor electrode has a structure selected from the group consisting of a stack structure, a cylindrical structure, a multiple fin structure, and a hemispherical grain (HSG) structure.
4. A method according to claim 1 wherein said upper capacitor electrode comprises a polysilicon layer.
5. A method of fabricating a capacitor for an integrated circuit device, said method comprising the steps of:
forming a lower capacitor electrode having a hemispherical grain (HSG) structure on an integrated circuit substrate;
forming a Ta2 O5 capacitor dielectric layer on said lower capacitor electrode opposite said integrated circuit substrate;
chemical vapor depositing a titanium nitride barrier layer on said Ta2 O5 capacitor dielectric layer opposite said lower capacitor electrode to a thickness in the range of 50 Å to 500 Å using TiCl4 as a source gas so as to reduce forming of TiOx at an interface between said Ta2 O5 capacitor dielectric layer and said titanium nitride barrier layer as a result of reaction of said TiCl4 with said Ta2 O5 capacitor dielectric layer, thereby reducing an equivalent oxide thickness of a resulting capacitor;
annealing said chemical vapor deposited titanium nitride barrier layer in an atmosphere of NH3 gas to reduce a leakage current density of the resulting capacitor; and
forming an upper capacitor electrode on said annealed chemical vapor deposited titanium nitride barrier layer opposite said integrated circuit substrate.
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