US5990863A - Image display system - Google Patents
Image display system Download PDFInfo
- Publication number
- US5990863A US5990863A US08/823,903 US82390397A US5990863A US 5990863 A US5990863 A US 5990863A US 82390397 A US82390397 A US 82390397A US 5990863 A US5990863 A US 5990863A
- Authority
- US
- United States
- Prior art keywords
- video signals
- data
- field
- buffer
- interlacing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
- H04N7/012—Conversion between an interlaced and a progressive signal
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0229—De-interlacing
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0606—Manual adjustment
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0626—Adjustment of display parameters for control of overall brightness
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/57—Control of contrast or brightness
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/641—Multi-purpose receivers, e.g. for auxiliary information
Definitions
- the present invention relates to an image display system for displaying interlaced images (of television and laser disc signals) on non-interlace display apparatuses, such as those used in personal computers (PC).
- PC personal computers
- video signals from television or laser discs are sometimes inputted to a PC and displayed on its screen, and these input signals constitute what are called interlaced images in which even-number fields and odd-number fields are alternated every 1/60 second. These signals comprising even-number and odd-number fields are together referred to as frames.
- An example of such display apparatus according to the prior art is disclosed in the U.S. Pat. No. 5,068,648.
- interlacing signals from the input source are once stored in a memory known as a frame buffer, end when they are read out of the frame buffer, they are converted into non-interlacing signals to display non-interlaced images on the PC screen.
- FIG. 6 illustrates conventional methods of interlace-to-non-interlace conversion: (a) shows a single buffer system, (b), a double buffer plus frame display system, and (c), another double buffer plus frame display system.
- the same buffer is used as read buffer for display indication and as write buffer for the input source.
- Double Buffer System 1 the read buffer for display indication and the write buffer for the input source arm separate, and the fields are displayed at a rate of 30 frames per second (fps).
- Double Buffer System 2 the read buffer for display indication and the write buffer for the input source are separate, and each even- or odd-number field is displayed at a rate of 60 fps.
- display indication each field is extended vertically, and interpolation lines are inserted into the spaces between fields.
- reading from the frame buffer may over-take writing from the image input source to the frame buffer and, if it does, an image under updating is displayed.
- each even-number or odd-number field of the input interlaced image is displayed as a single frame, even fast-moving images are immune from motion artifacts due to differences in motion corresponding to time differences between fields, but the height of the frame is doubled when displayed and interpolating lines are inserted between the original lines, resulting in poor resolution in the vertical direction and consequent deterioration in picture quality.
- the displayed image especially where a striped pattern is involved, may turn out completely different from the original image.
- the present invention worked out in view of the above-described problems involved in the prior art, is intended to provide an image display system subject to no conspicuous motion artifact ensuing from differences in motion corresponding to time differences between fields.
- an image display system for displaying interlacing video signals in the form of non-interlacing video signals comprising:
- a frame buffer for temporarily storing input interlacing video signals
- a difference calculator for calculating differences between fields from said interlacing video signals
- a brightness controller for controlling, on the basis of the differences between fields calculated by said difference calculator, the brightness of video signals stored in said frame buffer.
- At image display system may further have:
- a data writer for reading input interlacing video signals into said frame buffer and delivering them to said difference calculator
- a data reader for converting interlacing video signals stored in said frame buffer into non-interlacing video signals, reading them and delivering them to said difference calculator;
- timing controller for controlling the timing of writing video signals into said frame buffer by said data writer and that of reading video signals out of said frame buffer by said data reader,
- said difference calculator calculates differences between fields from interlacing video signals delivered from said data writer and non-interlacing video signals read out of said frame buffer.
- the difference calculator comprises a selector for judging in said data reader whether video date read out of said frame buffer are data in a plotted field or data in an after image field;
- an after image field buffer for delivering video data to said brightness controller when said selector judges them to be data in an after image field
- an inter-field difference calculator for calculating differences between video signals delivered from said data writer and video signals delivered to said plotted field buffer.
- FIG. 1 is a block diagram of an image display system which is a preferred embodiment of the present invention
- FIG. 2 is a diagram illustrating the usual timing of video outputs
- FIG. 3 is a diagram illustrating the timing of difference calculation in the image display system shown in FIG. 1;
- FIG. 4 is a diagram for describing an example of updating of the frame buffer in the image display system shown in FIG. 1;
- FIG. 5 is a block diagram for describing inter-field difference calculation and brightness control in the image display system shown in FIG. 1;
- FIG. 6 is a diagram illustrating a conventional method of interlace-to-non-interlace conversion.
- FIG. 1 is a block diagram of an image display system which is the preferred embodiment of the present invention.
- This embodiment includes, as illustrated in FIG. 1, an analog-to-digital (A/D) converter 1 for converting input interlacing video signals into digital signals; a frame buffer 5 for temporarily storing the digital signals resulting from the conversion of interlacing video signals by the A/D converter 1; a difference calculator 6 for calculating inter-field differences from the digital signals resulting from the conversion of video signals by the A/D converter 1; a data writer 2 for writing into the frame buffer 5 the digital signals resulting from the conversion of video signals by the A/D converter 1 and delivering them to the difference calculator 6; a data reader 4 for converting the interlacing video signals into non-interlacing video signals by altering the frequency, reading them out, and delivering them to the difference calculator 6; a timing controller 3 for controlling the timing of writing video signals into the frame buffer 5 by the data writer 2 and that of reading video signals out of the frame buffer 5 by the data reader 41 a brightness controller 7 for controlling, on the basis of the inter-field differences calculated by the difference calculator 6, the brightness of video signals read out of the
- input interlacing video signals are first stored into the frame buffer 5, and converted into non-interlacing video signals by altering their frequency when they are read out.
- Inter-field differences are calculated from the input video signals by the difference calculator 6 and, on the basis of the calculation results, the brightness controller 7 controls the brightness of video signals, which are then outputted.
- FIG. 2 is a diagram illustrating the usual timing of video outputs, wherein "odd” represents an odd-number field, "even”, an even-number field, and the numeral following "odd” or "even”, a position in the time sequence.
- the output image is divided into a plotted field and an after image field, which are currently being plotted and remaining as an after image, respectively.
- FIG. 3 is a diagram illustrating the timing of difference calculation in the image display system shown in FIG. 1.
- the input is the timing of the entry of video signals into the frame buffer 5, and the output is that of the reading of video signals from the frame buffer 5.
- the field currently displayed in a plotting state is compared with the incoming image to figure out the difference.
- the calculation is completed at the end of the input field, and then controlled so as to be reflected in the field of an after image state.
- FIG. 4 is a diagram for describing an example of updating of the frame buffer in the image display system shown in FIG. 1.
- this embodiment is provided with a buffer for updating fields in addition to buffers for displaying odd-number and ever-number fields.
- FIG. 5 is a block diagram for describing inter-field difference calculation and brightness control in the image display system shown in FIG. 1.
- the difference calculator in this embodiment includes of a buffer 15 for controlling the frequencies of input images and output images; an interfield difference calculator 16 for calculating the difference between an image inputted to the frame buffer 5 and an image outputted from the frame buffer 5; a selector 19 for judging whether video data read by the data reader 4 out of the frame buffer 5 are data in a plotting field or data in an after image field; a plotting field buffer 20 for delivering, when the selector 19 judges given data to be data in a plotting field, the video data to the inter-field difference calculator 161 an after image field buffer 21 for delivering, when the selector 19 judges given data to be data in an after image field, the video data to the brightness controller 7; and a brightness control value memory 17 for storing the value calculated by the inter-field difference calculator 16.
- the data writer 2 When video data are entered into the data writer 2 via the A/D converter 1, the data writer 2 writes the latest video data, which are the same as the video data written into the frame buffer 5, into the buffer 15.
- the frequency difference between the input image and the output image is absorbed to carry out necessary frequency control for calculating difference.
- the data read by the data reader 4 out of the frame buffer 5 are entered into the selector 19 to be judged whether they are data in a plotting field or data in an after image field.
- the data are judged by the selector 19 to be data in a plotting field, they are delivered to the plotting field buffer 20 and, after undergoing frequency adjustment with the input data, further delivered to the inter-field difference calculator 16.
- the data delivered to the inter-field difference calculator 16 under-go calculation of their difference from the data entered from the data writer 2 via the buffer 15, and the image control value for use when the data currently in a plotting field have shifted to an after image field in calculated, and stored in the brightness control value memory 17 as value to be displayed next.
- the data are judged by the selector 19 to be data in an after image field, they are delivered to the after image field buffer 21 and, after undergoing frequency adjustment with the data in the plotting field, further delivered to the brightness controller 7.
- the data delivered to the brightness controller 7 undergo calculation by the inter-field difference calculator 16 and brightness control on the basis of the value stored in the brightness control value memory 17.
- a selector provided in the brightness controller 7 synthesizes data in the after image field, whose brightness has been controlled, with data in the plotting field, which have been delivered to the plotting field buffer 20, and the resultant synthesized data are delivered to the D/A converter 8.
- a difference calculator for calculating, when interlacing video signals are entered, interfield differences according to the input interlacing video signals and non-interlacing video signals, into which the interlacing signals are converted when they are read out of a frame buffer, and a brightness controller for controlling the brightness of video signals in the after image field on the basis of the differences calculated by the difference calculator. Accordingly, even though images are updated, images both in the plotting field and in, the after image field can be displayed without allowing any image under updating to be displayed.
- This arrangement makes it possible, even where interlacing video signals are to be displayed in the form of non-interlacing video signals, to prevent motion artifacts, which result from lags in motion corresponding to time differences between fields, from becoming conspicuous in fast-moving images and to display still pictures and slow-moving images with high vertical resolution.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Graphics (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
- Television Systems (AREA)
Abstract
Description
Claims (3)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8067902A JPH09258707A (en) | 1996-03-25 | 1996-03-25 | Image display system |
JP8-067902 | 1996-03-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
US5990863A true US5990863A (en) | 1999-11-23 |
Family
ID=13358300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/823,903 Expired - Lifetime US5990863A (en) | 1996-03-25 | 1997-03-25 | Image display system |
Country Status (2)
Country | Link |
---|---|
US (1) | US5990863A (en) |
JP (1) | JPH09258707A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6535300B2 (en) * | 1997-06-26 | 2003-03-18 | Brother Kogyo Kabushiki Kaisha | Picture signal processing apparatus and method |
US6674478B2 (en) * | 1998-08-04 | 2004-01-06 | Sony Corporation | Image processing apparatus, method and providing medium |
US20070103598A1 (en) * | 2003-10-01 | 2007-05-10 | Katsuji Uro | Video signal processing apparatus |
US20100097521A1 (en) * | 2008-10-22 | 2010-04-22 | Fujitsu Limited | Video-signal processing apparatus, video-signal processing method, video-signal processing computer program, and video-signal control circuit |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4698674A (en) * | 1986-03-06 | 1987-10-06 | Vsp, Inc. | Interlace/non-interlace data converter |
US5068648A (en) * | 1988-01-29 | 1991-11-26 | Nec Corporation | Display controller having a function of controlling various display memories |
US5473382A (en) * | 1992-11-04 | 1995-12-05 | Hitachi, Ltd. | Video signal converting apparatus for converting an interlace video signal into a non-interlace video signal for reduction |
US5790096A (en) * | 1996-09-03 | 1998-08-04 | Allus Technology Corporation | Automated flat panel display control system for accomodating broad range of video types and formats |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2937339B2 (en) * | 1989-02-16 | 1999-08-23 | 株式会社東芝 | Motion adaptive processor |
JP2579014B2 (en) * | 1989-12-28 | 1997-02-05 | 富士通株式会社 | Interlace / non-interlace converter |
-
1996
- 1996-03-25 JP JP8067902A patent/JPH09258707A/en active Pending
-
1997
- 1997-03-25 US US08/823,903 patent/US5990863A/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4698674A (en) * | 1986-03-06 | 1987-10-06 | Vsp, Inc. | Interlace/non-interlace data converter |
US5068648A (en) * | 1988-01-29 | 1991-11-26 | Nec Corporation | Display controller having a function of controlling various display memories |
US5473382A (en) * | 1992-11-04 | 1995-12-05 | Hitachi, Ltd. | Video signal converting apparatus for converting an interlace video signal into a non-interlace video signal for reduction |
US5790096A (en) * | 1996-09-03 | 1998-08-04 | Allus Technology Corporation | Automated flat panel display control system for accomodating broad range of video types and formats |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6535300B2 (en) * | 1997-06-26 | 2003-03-18 | Brother Kogyo Kabushiki Kaisha | Picture signal processing apparatus and method |
US6674478B2 (en) * | 1998-08-04 | 2004-01-06 | Sony Corporation | Image processing apparatus, method and providing medium |
US20070103598A1 (en) * | 2003-10-01 | 2007-05-10 | Katsuji Uro | Video signal processing apparatus |
US20100097521A1 (en) * | 2008-10-22 | 2010-04-22 | Fujitsu Limited | Video-signal processing apparatus, video-signal processing method, video-signal processing computer program, and video-signal control circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH09258707A (en) | 1997-10-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5781241A (en) | Apparatus and method to convert computer graphics signals to television video signals with vertical and horizontal scaling requiring no frame buffers | |
US7280103B2 (en) | Display method, display apparatus and data write circuit utilized therefor | |
JP2656737B2 (en) | Data processing device for processing video information | |
US5469223A (en) | Shared line buffer architecture for a video processing circuit | |
US5633687A (en) | Method and system for providing an interlaced image on an display | |
EP0744731B1 (en) | Method and apparatus for synchronizing video and graphics data in a multimedia display system including a shared frame buffer | |
US5327240A (en) | Methods, systems and apparatus for providing improved definition video | |
US20020140685A1 (en) | Display control apparatus and method | |
JPH08508138A (en) | Video signal processing with motion compensation | |
KR19990067399A (en) | Adaptive picture delay | |
US5473382A (en) | Video signal converting apparatus for converting an interlace video signal into a non-interlace video signal for reduction | |
RU2113770C1 (en) | Method for generation of image data | |
US6359654B1 (en) | Methods and systems for displaying interlaced video on non-interlaced monitors | |
US5764240A (en) | Method and apparatus for correction of video tearing associated with a video and graphics shared frame buffer, as displayed on a graphics monitor | |
US6040868A (en) | Device and method of converting scanning pattern of display device | |
US6229571B1 (en) | Scan converter with interpolating function | |
US6747656B2 (en) | Image processing apparatus and method of the same, and display apparatus using the image processing apparatus | |
US5990863A (en) | Image display system | |
US5831684A (en) | Subpicture image signal vertical compression circuit | |
US7289170B2 (en) | Method and apparatus for compensating for interlaced-scan type video signal | |
US6437835B1 (en) | System and method for transfer of an interlaced video signal over a data bus for use by a non-interlace video signal device | |
JP3727631B2 (en) | Matrix display control device | |
US7106384B1 (en) | Method and device for simultaneously representing at least a first and a second sequence of pictures in an overall picture | |
JP3183231B2 (en) | Bus transfer method for video data | |
JP2635055B2 (en) | Still image transmission device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NEC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAKAMOTO, SUSUMU;REEL/FRAME:008472/0841 Effective date: 19970321 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: AU OPTRONICS CORPORATION, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:022928/0298 Effective date: 20090702 |
|
AS | Assignment |
Owner name: AU OPTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AU OPTRONICS CORP.;REEL/FRAME:025884/0016 Effective date: 20110302 Owner name: AU OPTRONICS CORPORATION AMERICA, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AU OPTRONICS CORP.;REEL/FRAME:025884/0016 Effective date: 20110302 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: AU OPTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AU OPTRONICS CORPORATION AMERICA;AU OPTRONICS CORP.;SIGNING DATES FROM 20120828 TO 20120904;REEL/FRAME:028906/0622 |