US5414662A - Dynamic random access memory using imperfect isolating transistors - Google Patents
Dynamic random access memory using imperfect isolating transistors Download PDFInfo
- Publication number
- US5414662A US5414662A US08/147,038 US14703893A US5414662A US 5414662 A US5414662 A US 5414662A US 14703893 A US14703893 A US 14703893A US 5414662 A US5414662 A US 5414662A
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- Prior art keywords
- sense
- bit line
- logic
- voltage
- inputs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
Definitions
- This invention relates to semiconductor dynamic random access memories (DRAMs) and in particular to apparatus and methods for controlling the sensing of bit lines.
- DRAMs semiconductor dynamic random access memories
- a DRAM is generally formed of an array of bit storage capacitors which are accessed via word lines and bit lines, the word lines being located in rows and the bit lines being located in columns.
- the capacitors are coupled via access transistors to the bit lines upon being enabled by the word lines; each capacitor is thus associated with the intersection of a bit line and word line.
- bit lines are usually provided as a folded bit line (pairs of complementary bit lines), with a sense amplifier connected to both bit lines of a folded bit line.
- a sense amplifier connected to both bit lines of a folded bit line.
- the charge stored on a capacitor is dumped on one of the lines of the folded bit line, and the sense amplifier senses the resulting differential in potential between the two lines of a folded bit line, applying full logic voltage levels to the bit lines which both restore the charge on the storage capacitors and apply full logic levels to data buses to which the bit lines are coupled.
- Bit lines typically have a capacitance of around 0.2-0.5 pF.
- current being passed through the sense amplifier to provide full logic voltage levels on the bit lines is consumed in charging the capacitance of the bit lines.
- the bit line voltage differential must exceed a certain noise margin before the levels on the bit lines can be read to the databuses.
- the voltage differential on the lines of the bit lines must be above that certain level, which requires a substantial capacitor charging time, which in turn results in a slowed sensing interval.
- a technique for attempting to deal with bit line capacitance is to insert an isolation device to isolate the sense nodes associated with the sense amplifier from the bit lines during the initial sensing period.
- a memory capacitor associated with one of the lines of the bit line is enabled to dump its charge on one bit line, following which both bit lines are completely isolated from the sense amplifier. Since the small amount of capacitance associated with the sense node retains some charge differential, subsequent enabling of the sense amplifier causes it to sense this differential, and to apply the full logic level to the sense nodes for application to the databus. Since the sense nodes are now completely isolated from the bit lines, the bit lines need not be charged up by the power supply associated with the sense amplifier, and the time for charging the bit line capacitances thus is substantially eliminated.
- the conductive tracks which carry the sense amplifier clock signals must supply considerable current in order to provide, for all sense amplifiers on the chip, full logic levels. That current must not only charge the bit lines and sense nodes, but also the databuses.
- the conductive tracks across the semiconductor integrated circuit contains resistance, and the heavy clock current passing down the tracks creates a voltage difference. This creates a significant differential in the speed of operation of sense amplifiers close to the sense amplifier clock drivers from those at the far ends of the tracks. Access of data from the memory must be slowed to accommodate the slowest sense amplifier.
- the isolation device is a field effect transistor (FET) which has its source drain circuit in series between a sense node and an associated bit line.
- FET field effect transistor
- the gate of each FET is held at a voltage which maintains it imperfectly open, and changes to a level which allows each FET to conduct when the sense amplifier operates (e.g. its gate-source voltage is similar to the logic level supplied by the sense amplifier).
- the imperfect isolation referred to herein means that the source-drain of the FET is in a high resistance state, but allows some charge leakage through it.
- the memory capacitor dumps its charge on the associated bit line
- the charge leaks through the imperfect isolation device to the associated sense node of the sense amplifier.
- the voltage on the gate of each isolating field effect transistor is changed to the logic level which is to be applied to the sense amplifier. Due to the leakage through the imperfect isolating device, charge from the memory capacitor leaks to the sense node.
- the sense amplifier is enabled. Due to the charge differential between its sense nodes, the sense amplifier applies full logic voltage level to the sense nodes, which is applied to the databuses. However due to the voltage drop across the isolating FET, there is significantly less current consumed in charging the bit line capacitance. As a result the sense nodes reach full logic levels considerably faster than in the prior art.
- the gate source bias of the isolating FET is increased to allow bit lines to be charged to full logic levels (overcoming the threshold voltage drop in the FET). This allows bit line charging current to be distributed over time.
- a dynamic random access memory is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense nodes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.
- DRAM dynamic random access memory
- a dynamic random access memory is comprised of a plurality of bit lines and associated sense amplifiers, the bit lines being arrayed across an integrated circuit chip and the sense amplifiers being disposed in a row, a pair of low resistance power supply conductors extending in parallel with the row for carrying logic high level and logic low level voltages, sense amplifier enabling signal conductors extending across the chip accessible to the sense amplifiers, apparatus for coupling sense inputs of the sense amplifiers to the power supply conductors, and apparatus coupling the sense amplifier enabling signal conductors to the apparatus for coupling sense inputs, for enabling passage of current resulting from the logic high level and low level voltages to the sense amplifiers.
- DRAM dynamic random access memory
- a dynamic random access memory is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, the sense amplifier having respective sense enable and restore enable inputs for providing full high and full low logic levels respectively to the sense nodes, power supply apparatus for providing full high and full low logic level voltages, a pair of field effect transistors, one having its source-drain circuit connected between the restore enable input and the high logic level power supply voltage and the other having its source-drain circuit connected between the sense enable input and the power supply low-logic level power supply voltage, and apparatus for providing restore and sense signals to gates of the one and other field effect transistors respectively, whereby restore and sense current is supplied to the sense amplifier from the power supply apparatus rather than from the apparatus for providing restore and sense signals.
- DRAM dynamic random access memory
- a method of sensing in a folded bit line type of dynamic random access memory (DRAM) having a bit storage capacitor for coupling to the bit line and a sensing amplifier having sense nodes is comprised of the steps of imperfectly isolating the sense nodes of the sensing amplifier from the bit line using an imperfectly isolating apparatus, coupling the capacitor to the bit line thereby dumping its charge thereon, leaking the charge through the imperfect isolating apparatus to one of the sense nodes thereby causing a voltage differential across the sense nodes, sensing the differential by the sense amplifier, and applying full high and low logic levels respectively to the sense nodes, and, inhibiting isolation of the sense nodes from the bit line, whereby full logic levels are applied to the complementary bit lines.
- DRAM dynamic random access memory
- the enabling inputs to the sense amplifiers are connected through local pull down field effect transistors to local power supply tracks which have little resistance from one end to the other of the integrated circuit memory.
- the gates of these pull down transistors are connected to the sense amplifier clock conductive tracks since very little current is required by the gates of those transistors, and very little voltage drop thus occurs between the near and far ends of the integrated circuit. Accordingly enabling of the sense amplifiers is substantially speeded at locations remote from the near end sense amplifiers, and there is substantially reduced differential in enabling speed between the near and far end of the sense amplifiers.
- groups of sense amplifiers may be coupled to the same pull down transistors.
- FIG. 1 is a schematic diagram of a portion of a bit line circuit and sense amplifier in accordance with the prior art
- FIG. 2 is a schematic diagram of a portion of a bit line circuit and sense amplifier in accordance with the present invention.
- FIG. 3 is a waveform diagram used to describe the function of the present invention.
- Bit storage capacitors 1A and 1B are coupled through field effect transistors (FETs) 2A and 2B to complementary bit lines BL and/BL of a folded bit line.
- FETs field effect transistors
- the gates of transistors 2A and 2B are connected to word lines WL n and WL n+1 in a well known manner.
- a sense amplifier 3 is connected to the bit lines also in a well known manner.
- the bit lines are coupled to databuses DB and /DB via FETs 4A and 4B.
- the sense amplifier 3 is formed of a pair of N-channel transistors having their series connected source-drain circuits connected across the bit lines of the folded bit line, their junction being connected to an active low logic level source / ⁇ s , and a pair of P-channel FETs having their series connected source-drain circuits connected across bit lines BL and /BL, their junction being connected to an active high level source ⁇ R .
- the gates of the N and P-channel transistors connected to a first bit line are connected together and to the other bit line, and the gates of the transistors connected to the other transistor are connected together and to the first bit line.
- a transistor e.g. 2B is enabled from a word line, and the charge, representing a bit, stored on a capacitor e.g. 1B is dumped to the associated bit line /BL.
- the logic levels / ⁇ s and ⁇ R are applied to the sense amplifier 3
- the voltage differential causes the circuit to latch, applying the full logic levels of / ⁇ s and ⁇ R to the bit lines. This restores the charge on the capacitor 1B to full logic level.
- the transistors 4A and 4B by the signal / ⁇ yi , the resulting full logic level on the bit lines is applied to the databuses DB and /DB.
- each bit line Associated with each bit line is an inherent capacitance 5A and 5B, which results from the length and breadth of the bit line track on the semiconductor and the substrate. Those capacitances 5A and 5B must be charged by the current from the power supply supplying the full logic levels / ⁇ s and ⁇ R . This takes a considerable period of time and current requirement.
- isolators 6A and 6B have been used to isolate the bit line from the sensing nodes SA and SB associated with the sense amplifier.
- the isolators are devices which completely isolate the bit lines from the sense nodes.
- the isolator since the isolator must be turned on and off, additional steps in the memory access sequence must be performed. Further, the isolator must be inhibited in order to restore the logic level to the memory capacitor and indeed, if an incorrect bit were read, the restored bit value would also be incorrect. Clearly both speed and reliability of the memory were sacrificed.
- FIG. 2 illustrates an embodiment of the present invention.
- An imperfect isolation device 8A and 8B, driven from a source ⁇ In is connected in series between each bit line and each sense node.
- the imperfect isolation devices are N-channel enhancement mode FETs 8A and 8B.
- P-channel enhancement mode FETs are connected in series between each bit line and each sense node.
- the gates of the transistors 9A and 9B are connected together to a logic source ⁇ Ip .
- operation of the device is as follows. At the beginning of an active cycle the voltage ⁇ IN is brought from a boosted level, e.g. V pp to a lower level that still allows cell charge to flow to the sense amplifier as noted, e.g. V dd . Then, as described earlier, either transistor 2A or 2B is enabled, causing the charge on either bit storage capacitor 1A or 1B to be dumped on an associated bit line. Charge on the bit line leaks through the high resistance source-drain circuit transistor 8A or 8B (assuming transistors 9A and 9B are not present) to the sense node SA or SB, charging the small capacitance associated therewith.
- the sense amplifier 3 is enabled by applying high logic level ⁇ s and low logic level / ⁇ R , as described earlier.
- the sense amplifier is caused to apply the full logic levels ⁇ s and / ⁇ R to the sense nodes SA and SB, latching due to the differential thereacross.
- bit line capacitances 5A and 5B will only be charged up to a reduced voltage less than full logic level applied to the sense nodes. Since capacitances 5A and 5B are charged a reduced amount, the sensing interval is considerably reduced from the prior art; the sensing is faster because the sense node voltage differential develops faster for the same sense current budget.
- Data can be read out over the data bus by enabling column access transistors 4A and 4B, as soon as a sufficient potential exists across the sense nodes. Hence memory access time is improved by the isolation devices. While the restore charge on capacitors 1A and 1B is less than full logic level, they can be fully restored after column access.
- the ⁇ IN level is brought back up to the boosted level V pp to allow full restore of the bit lines. This causes a second peak in sensing current. Compared to prior art sensing current peaks are lower and are distributed over time.
- P-channel transistors 9A and 9B could be used in place of transistors 8A and 8B, or in series therewith as shown in the figure. If P-channel transistors are used, their gates should initially be at a ⁇ IP level V bb , and are raised to a level V ss during the initial part of sensing when a high impedance isolation device is required.
- resistive voltage drops in the conductive tracks in the semiconductor memory from the sense amplifier driver circuits to the far end of the array cause quick sensing at the near end of the array (close to the sense amplifier driver circuits) and slow (retarded) sensing at the far end of the array.
- memory access must be delayed to accommodate the sensing of the slowest column.
- transistors 12A and 12B are connected through the source-drain circuits of FETs 12A and 12B to voltage sources V dd and ground (V ss ) respectively.
- the gates of transistors 12A and 12B are driven from the / ⁇ R and ⁇ s logic sources respectively.
- ground and V dd power tracks on an integrated circuit memory normally are of low resistance. Therefore the provision of those sources to the sense amplifiers is through short and low resistance conductors.
- the result of the last-described embodiment is increased reliability, since leaky bit lines which have been deprogrammed will not affect sense line current in other bit lines, if local sense clock drivers are shared only among bit lines with the same redundancy address. No additional power supplies are required other than those normally on the chip.
- the result of the above embodiments is increase in sensing speed and more uniformity of sensing speed across a large DRAM.
- N-channel bit line isolation devices could be used in conjunction with local sensing amplifier enabling pull downs as described, to control peak V dd current and V ss current respectively.
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- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
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Abstract
Description
Claims (17)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/147,038 US5414662A (en) | 1990-04-06 | 1993-11-04 | Dynamic random access memory using imperfect isolating transistors |
US08/377,622 US5574681A (en) | 1990-04-06 | 1995-01-25 | Method for DRAM sensing current control |
US08/853,507 USRE37641E1 (en) | 1990-04-06 | 1997-05-08 | Dynamic random access memory using imperfect isolating transistors |
US10/032,431 USRE40552E1 (en) | 1990-04-06 | 2001-12-21 | Dynamic random access memory using imperfect isolating transistors |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB909007789A GB9007789D0 (en) | 1990-04-06 | 1990-04-06 | Method for dram sensing current control |
GB9007789 | 1990-04-06 | ||
US68074791A | 1991-04-05 | 1991-04-05 | |
GB9107164 | 1991-04-05 | ||
GB9107164A GB2242768A (en) | 1990-04-06 | 1991-04-05 | DRAM sensing control; connecting bitlines to sense amplifier |
US08/147,038 US5414662A (en) | 1990-04-06 | 1993-11-04 | Dynamic random access memory using imperfect isolating transistors |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US68074791A Continuation | 1990-04-06 | 1991-04-05 |
Related Child Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/377,622 Continuation US5574681A (en) | 1990-04-06 | 1995-01-25 | Method for DRAM sensing current control |
US08/853,507 Reissue USRE37641E1 (en) | 1990-04-06 | 1997-05-08 | Dynamic random access memory using imperfect isolating transistors |
US10/032,431 Reissue USRE40552E1 (en) | 1990-04-06 | 2001-12-21 | Dynamic random access memory using imperfect isolating transistors |
Publications (1)
Publication Number | Publication Date |
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US5414662A true US5414662A (en) | 1995-05-09 |
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Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/147,038 Ceased US5414662A (en) | 1990-04-06 | 1993-11-04 | Dynamic random access memory using imperfect isolating transistors |
US08/377,622 Expired - Lifetime US5574681A (en) | 1990-04-06 | 1995-01-25 | Method for DRAM sensing current control |
US08/853,507 Expired - Lifetime USRE37641E1 (en) | 1990-04-06 | 1997-05-08 | Dynamic random access memory using imperfect isolating transistors |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
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US08/377,622 Expired - Lifetime US5574681A (en) | 1990-04-06 | 1995-01-25 | Method for DRAM sensing current control |
US08/853,507 Expired - Lifetime USRE37641E1 (en) | 1990-04-06 | 1997-05-08 | Dynamic random access memory using imperfect isolating transistors |
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GB (2) | GB9007789D0 (en) |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5574681A (en) * | 1990-04-06 | 1996-11-12 | Mosaid Technologies Incorporated | Method for DRAM sensing current control |
US5610573A (en) * | 1995-09-13 | 1997-03-11 | Lsi Logic Corporation | Method and apparatus for detecting assertion of multiple signals |
US5636170A (en) * | 1995-11-13 | 1997-06-03 | Micron Technology, Inc. | Low voltage dynamic memory |
US5673219A (en) * | 1996-03-21 | 1997-09-30 | Texas Instruments Incorporated | Apparatus and method for reducing leakage current in a dynamic random access memory |
US5694143A (en) * | 1994-06-02 | 1997-12-02 | Accelerix Limited | Single chip frame buffer and graphics accelerator |
US5748554A (en) * | 1996-12-20 | 1998-05-05 | Rambus, Inc. | Memory and method for sensing sub-groups of memory elements |
US5936898A (en) * | 1998-04-02 | 1999-08-10 | Vanguard International Semiconductor Corporation | Bit-line voltage limiting isolation circuit |
US6041010A (en) * | 1994-06-20 | 2000-03-21 | Neomagic Corporation | Graphics controller integrated circuit without memory interface pins and associated power dissipation |
US6542107B1 (en) | 2002-01-11 | 2003-04-01 | International Business Machines Corporation | Flash analog-to-digital converter using folded differential logic encoder having capacitors which distribute charge |
US20050083721A1 (en) * | 2001-09-07 | 2005-04-21 | Hampel Craig E. | Granularity memory column access |
US20050137710A1 (en) * | 1995-09-04 | 2005-06-23 | Amiram Steinberg | One piece snap fit acetabular cup |
US20060039227A1 (en) * | 2004-08-17 | 2006-02-23 | Lawrence Lai | Memory device having staggered memory operations |
US20060117155A1 (en) * | 2004-11-29 | 2006-06-01 | Ware Frederick A | Micro-threaded memory |
US7280428B2 (en) | 2004-09-30 | 2007-10-09 | Rambus Inc. | Multi-column addressing mode memory system including an integrated circuit memory device |
US20070260841A1 (en) * | 2006-05-02 | 2007-11-08 | Hampel Craig E | Memory module with reduced access granularity |
US20080056039A1 (en) * | 2006-08-04 | 2008-03-06 | Kim Myeong-O | Sense amplifier, semiconductor memory device including the same, and data sensing method |
US7500075B1 (en) | 2001-04-17 | 2009-03-03 | Rambus Inc. | Mechanism for enabling full data bus utilization without increasing data granularity |
JP2013016247A (en) * | 2011-06-10 | 2013-01-24 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device |
US9268719B2 (en) | 2011-08-05 | 2016-02-23 | Rambus Inc. | Memory signal buffers and modules supporting variable access granularity |
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DE19503782A1 (en) * | 1995-02-04 | 1996-08-08 | Philips Patentverwaltung | Delay circuit |
JP3220027B2 (en) * | 1996-11-01 | 2001-10-22 | 日本電気株式会社 | Semiconductor storage device |
KR100221629B1 (en) * | 1996-12-28 | 1999-09-15 | 구본준 | Data access device of dram |
US5764581A (en) * | 1997-03-04 | 1998-06-09 | Advanced Micro Devices Inc. | Dynamic ram with two-transistor cell |
US5901078A (en) | 1997-06-19 | 1999-05-04 | Micron Technology, Inc. | Variable voltage isolation gate and method |
JPH11232868A (en) * | 1998-02-10 | 1999-08-27 | Nippon Foundry Inc | Semiconductor storage integrated circuit |
US6300810B1 (en) | 1999-02-05 | 2001-10-09 | United Microelectronics, Corp. | Voltage down converter with switched hysteresis |
US6285242B1 (en) * | 1999-02-05 | 2001-09-04 | United Microelectronics Corporation | Reference voltage shifter |
US6195302B1 (en) | 1999-02-05 | 2001-02-27 | United Memories, Inc. | Dual slope sense clock generator |
JP2015118724A (en) * | 2013-11-13 | 2015-06-25 | 株式会社半導体エネルギー研究所 | Semiconductor device and method for driving the semiconductor device |
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GB9007789D0 (en) * | 1990-04-06 | 1990-06-06 | Foss Richard C | Method for dram sensing current control |
-
1990
- 1990-04-06 GB GB909007789A patent/GB9007789D0/en active Pending
-
1991
- 1991-04-05 GB GB9107164A patent/GB2242768A/en not_active Withdrawn
-
1993
- 1993-11-04 US US08/147,038 patent/US5414662A/en not_active Ceased
-
1995
- 1995-01-25 US US08/377,622 patent/US5574681A/en not_active Expired - Lifetime
-
1997
- 1997-05-08 US US08/853,507 patent/USRE37641E1/en not_active Expired - Lifetime
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Also Published As
Publication number | Publication date |
---|---|
USRE37641E1 (en) | 2002-04-09 |
US5574681A (en) | 1996-11-12 |
GB9007789D0 (en) | 1990-06-06 |
GB2242768A (en) | 1991-10-09 |
GB9107164D0 (en) | 1991-05-22 |
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