US3900719A

US3900719A - Hybrid arithmetic device

Info

Publication number: US3900719A
Application number: US355061A
Authority: US
Inventors: Satoshi Yamauchi
Original assignee: Ricoh Co Ltd
Current assignee: Ricoh Co Ltd
Priority date: 1972-05-01
Filing date: 1973-04-27
Publication date: 1975-08-19
Anticipated expiration: 1992-08-19
Also published as: JPS495236A; FR2183477A5; GB1437981A; JPS5225217B2; DE2322156A1

Abstract

A hybrid arithmetic device is disclosed in which a load is connected to a constant current or voltage source, and the resistances of the load and a resistor which determines the constant current or voltage of the constant current or voltage source are varied in response to coded signals representing decimal digits. The result of multiplication or division of two decimal operands may be detected as a voltage across or current flowing through the load resistor.

Description

United States Patent 11 1 Yamauchi Aug. 19, 1975 [54] HYBRID ARITHMETIC DEVICE 3.400257 9/l968 Smith 235/5052 {75] Inventor: Satoshi Yamauchi. Tokyo. Japan 73 Assigneez Ricoh Co" Ltd" Tokyo Japan 3.634.659 1/1972 Lucas et a1. 235/1505 X [22] F'led: 1973 Primary E ranu'nerMalcolm A. Morrison [21] A N 3553M Assistant I:.'.\aminer.lerry Smith Attorney, Agent. 0:" Firm-.|ohn F. Ohlandt [30] Foreign Apphcatlon Prlorlty Data ABSTRACT May 1, 1972 Japan 1. 47-43497 A hybrid arithmetic device is disclosed in which a load [52] s Cl. 235/5052; 235/1505; 235/194 is connected to a constant current or voltage source, 5 1 C| G06- I/OO; 006g 7/16 and the resistances of the load and a resistor which de- 58 1 Field of Search .4 235/1505, 150.52, 50.53. lermmes the constant current or voltage of the 235/|g4 9 9 333H6Q |6| stant current or voltage source are varied in response to coded signals representing decimal digits. The re- 1 56] References cu sult of multiplication or division of two decimal oper- UNITED STATES PATENTS ands may be detected as a voltage across or current flowing through the load resistor. 3.293.424 12/1966 Flsher 235/194 1309.508 3/!967 Win 23S/l5(l.52 5 Claims, ll Drawing Figures PATENTEUAUB'I 9197s 3, 900 7 1 9 sum 1 0r 3 FIG. 2

PATENT [[1 AUG-1 91975 3. 900,7 1 9 sum 3 n; 3

HYBRID ARITI-I'METIC DEVICE BACKGROUND OF THE INVENTION AND SUMMARY The present invention relates to a hybrid arithmetic device of the type in which multiplication or division may be electrically effected in a digital-to-analog conversion process.

Analog and digital multipliers and dividers are widely used in computers and other data processing units. In the analog multipliers and dividers, two analog inputs representing the operands such as a multiplicand and multiplier. or dividend and divisor are converted into signals representing the logarithms of the two operands so that the product or quotient may be obtained by the addition or subtraction of the logarithms. The output signal representing the sum of or difference between the logarithms is converted into a signal representing the antilogarithm thereof. In order to improve the accuracy in arithmetic operation. the stability of the logarithmic multipliers and dividers must be improved. As a result their circuits become very complex in construction. In case of the digital multipliers and dividers, the control of the registers, adders and subtractors is extremely complicated and the speed is relatively low.

One of the objects of the present invention is to provide a hybrid arithematic device comprising in combination analog and digital arithmetic and functional circuits.

Another object of the present invention is to provide a high-speed hybrid arithmetic device simple in construction and capable of carrying out arithmetic operations with a higher degree of accuracy and at a considerably higher speed than digital arithmetic devices.

According to the present invention a constant voltage circuit or source is connected to a first resistor to which in turn is connected in Series a second resistor. The constant voltage source and the first resistor constitute a constant current source for controlling a constant current flowing through the second resistor. To the second resistor is connected a third resistor to which in turn is connected in series a load resistor. The constant current source and the second resistor constitute a constant voltage circuit for controlling a constant voltage across the third resistor. The constant voltage source and the third resistor constitute a constant current source for controlling a constant current flowing through the load resistor. The relation between the voltage E, across the first resistor and the output voltage E across the load resistor is given by R2 n L RI R3 1 where R,, R R and R resistances of the first, second, third and load resistors, respectively. When the resistances R and R of the second and third resistors as well as the voltage E, across the first resistor are made constant while the resistances R and R, are varied in response to a dividend and a divisor, respectively, the quotient is derived as the output voltage E across the load resistor. When the voltage E, across the first resistor as well as the resistances R, and R of the first and third resistors are made constant whereas the resistances of the second and load resistors are varied to correspond a multiplicand and a multiplier, respectively. the product is derived as the voltage E across the load resistor. According to the present invention the resistances of the resistors which determine the constant voltages and currents of the constant current and voltage sources are varied in response to digital signals representing operands such as a multiplicand, multiplier, dividend and divisor. For this purpose digital-toanalog converters are used.

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the preferred embodiments thereof taken in conjunction with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING FIGS. I, 2, 3, and 4 are circuit diagrams used for the explanation of the underlying principle of the present invention;

FIGS. 5-A, -B. -C and -D are circuit diagrams of the digital-to-analog converters used in the present invention;

FIG. 6 is a circuit diagram of a hybrid arithmetic device in accordance with the present invention;

FIG. 7 is a circuit diagram used for the explanation of one application of a hybrid arithmetic device in accordance with the present invention; and

FIG. 8 is a circuit diagram of another hybrid arithmetic device in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Principle of the Invention, FIGS. 1 -5 Referring to FIG. I, a first constant voltage circuit or source comprising a resistor R a Zener diode ZD and a transistor Tr, is provided for a resistor R,, and a first constant current circuit or source comprising the first constant voltage circuit and the resistor R, is provided for a resistor R In like manner, a second constant voltage circuit or source comprising the resistors R R, and R the Zener diode ZD, a diode D and the transistors Tr, and Tr is provided for a resistor R and a second constant current circuit comprising the second constant voltage circuit and the resistor R is provided for a resistor R The voltage E across the zener diode ZD and the voltage drop E across the base and emitter of the transistor Tr, are constant so that the current I, flowing through the resistor R, is given by where E, 15 E The voltage across the resistor R is given by (2) In like manner the current flowing through the resistor R the transistor Tr and the resistor R is given by 12 z El a/R3 Substituting Eq. (2) into Eq. (4). we have From Eq. (5! it is seen that when the values ofthe resistors R and R; are fixed whereas the magnitudes of the resistors R and R are varied to correspond to the dividend X and the divisor Y. the output voltage E is proportion to the quotient X/Y may be obtained. When the magnitudes of the resistors R and R are fixed whereas the magnitudes of the resistors R and R are varied to correspond to the multiplicand X and the multiplier Y. respectively. the output voltage E is in proportion to the product X'Y. The voltage E, which is the voltage across the Zener diode ZD is constant. In general any combination of the resistors R R R and R may be used. and the circuit shown in FIG. 1 may be used as a square-root generator or squarer when the magnitudes of the resistors R w R are suitably selected.

The circuit shown in FIG. I is the most fundamental circuit of the present invention, and when a more accurate output is required, a circuit shown in FIG. 2 is used which is substantially similar to that shown in FIG. 1. Eq. (5 l holds for the voltage E across the Zener diode ZD and the voltage E across the output resistor R in the circuit shown in FIG. 2. Two differential amplifiers A, and A whose gain is very high are inserted in the circuit shown in FIG. 2 in order to feed back the outputs thereof to their negative terminals through Dar- Iington circuits Tr and Tr and Tr and Tr There fore the stability and accuracy of the constant current circuits may be further improved over the circuit shown in FIG. I. When a third differential amplifier A with a gain of unity is connected to the output resistor R the output voltage E may be detected through the amplifier A without causing the change in current flowing through the resistor R FIGS. 3 shows an operational amplifier of the inverting configuration, and when the gain of the differential amplifier A is almost infinity, the input current thereof is almost zero so that the relation between the current l flowing through the resistor R and the current I flowing through the resistor R is given by This means that the circuit shown in FIG. 3 functions as a constant current circuit or source for the load re sistor R... Since the gain of the amplifier A is almost infinity, the input voltage error Es of the amplifier A is almost zero and the output voltage E becomes the voltage across the load resistor R Therefore the relation between the input voltage E and the output voltage E is given by From Eq. (6) it is seen that when the magnitudes of the resistor R. and R, are so selected as to correspond to the dividend and divisor, the output voltage [1], represents the quotient. That is, the circuit shown in FIG. 3 functions as a divider.

In the circuit shown in FIG. 4, the circuits of the type shown in FIG. 3 are connected in cascade. and Eq. (5)

holds for the input and output voltages E and E Therefore the circuit shown in FIG. 4 functions as a multiplier or divider depending upon the combination of the resistors R R R and R In order to construct a hybrid arithematic device from the circuits of the types described hereinbefore. the magnitudes of the resistors must be varied so as to represent the multiplicand, multiplier. dividend and divisor which are fed in the form of digital signals. For this purpose digital-to-analog converters of the types shown in FIGS. S-A to 5-D are used. In these circuits weighted resistors are connected in series or parallel as is well known in the art, and a contact or contacts across a resistor or resistors are closed or opened depending upon a given digital signal.

In the digitaI-to-analog converter shown in FIG. S-A, the resistors R R represent weights equal to successive powers of 2. That is, they represent weights r. 2r, 4r and Sr, respectively. The switches S S S and S shunt the resistors R R respectively. Assume that the decimal digit 6" which may be represented by ()1 H)" in the pure binary code be converted into the analog signal. Then the switches S and 5 are opened so that the combined resistance Rs becomes Rx 2r 4r or which is the resistance representing the decimal digit In the digItaLto-analog converter shown in FIG. S-B weighted resistors R R R and R representing the weights r. r/Z. r/4 and r/X are connected in parallel together with the switches 5., S When the switch S, and 5;, is closed in response to a given digital signal, the combined resistance Rp is given by Ill Rp M r l r The circuit shown in FIG. S-B is adapted to carry out the multiplications and divisions based upon Eq. (5) which may be rewritten in the form of I, a. z 1

illil i Hybrid Arithematic Device. FIG. 6

FIG. 6 illustrates a hydrid arithmetic device in accordance with the present invention comprising the circuit shown in FIG. 3 and the digital-to-analog converter shown in FIG. S-A. The resistors R and R are shown as comprising a weighted resistor network of the type shown in FIG. S-A. As described hereinbefore a dividend is represented by the magnitude of the resistor R, whereas a divisor is represented by the magnitude of the resistor R to carry out the division based upon Eq.

(6). For example in order to obtain the quotient of 3/6, the switches S and S are opened in response to the binary coded signal 001 l representing the decimal digit 3 whereas the switches 8, and 5,, are opened in response to the binary signal ()1 l0" representing the decimal digit 6. Therefore R 3n, and R, 6r,. From Eq (6) the output voltage E becomes Since r,,, r, and E, are all constants, the output voltage E is proportional to 3/6".

Application, FIG. 7

Next one example of an application ofa hybrid arithmetic device in accordance with the present invention will be described in connection with a teaching machine of the type which may automatically analyze the responses or answers from students for a given question and record the analyzed data. Each student selects one of a plurality of previously given answers for a given question, and the number of students who selected each of a plurality of answers is recorded. In this case it is advantageous if the ratio of the number of students who selected each of a plurality of answers to the total number of students is also displayed and recorded. This may be accomplished by the circuit shown in FIG. 7.

Referring to FIG. 7 illustrating the circuit which is substantially similar in construction to that shown in FIG. 2, same reference numerals are used to designate similar components. A constant current source I0 may comprises the Zener diode ZD and the differential amplifier A, as shown in FIG. 2 or may be any conventional constant current source. The internal resistance of the constant current source I0 corresponds to the resistor R, shown in FIG. 2. A first arithmetic device comprising the constant current source 10, and the resistors R R and R,, carries out the division of (the number of students who selected a first answer/ the total number of students). The output of the differential amplifier A in the first hybrid arithmetic device is applied through a signal line 1 to the input ofa second arithmetic device comprising the resistor R the con stant current source and the resistors R and R In order to carry out the division based upon Eq.(7), the total number of students, that is a divisor is represented by R whereas the numbers of students who selected the specific answers that is, dividends, are represented by the resistors R R and so on, respectively. As a result the voltage across or current flowing through each of the resistors R,,., R and so on represents the number of students who selected a specific answer/the total number of puiples. In order to improve the accuracy, the output of the first arithmetic circuit may be derived through the operational amplifier A or instead of the resistor R an ammeter is inserted so that the teacher may directly read the ratio. In the circuit shown in FIG. 7 the digital-to-analog converter of the type shown in FIG. S-B is used.

Hybrid Arithmetic Device, FIG. 8

The hybrid arithmetic device shown in FIG. 8 gives the result of a division or multiplication in the form of a digital output, and is based upon the circuit shown in FIG. 3. That is, the circuit comprising the differential amplifier A, and the resistors R, and R,, which are shown as comprising a weighted resistor network is substantially similar in construction to the divider shown in FIG. 3. The weighted resistor networds R, and

R are similar to the circuit shown in FIG. 5-C including the switching transistors Tr, and Tr The on-off operation of the transistor Tr, is controlled in response to a register 11 whereas the on-olf operation of the switching transistor Tr, is controlled in response to the output of a register 12. In addition to the above components, the hybrid arithmetic device shown in FIG. 8 comprises a register 13, a voltage comparator l4 and a generalpurpose analog-to-digital converter comprising the flipflop IS, the weighted resistor network R and the differential amplifier A The registers I] and 13 also function as a counter, and the flip-flop 15 is set in response to the clear input and reset in response to the output of the comparator 14.

Next the mode of division will be described. The flipflop 15 is set in response to the clear input before the arithematic device is actuated. The digital signals rep resenting the digits A and B are stored in the

registers

11 and 12, respectively and the analog voltage representing the quotient A/B is derived from the differential amplifier A,, and is applied to one input terminal of the comparator 14. Since the flip-flop 15 is set, the clock signals are transmitted through a gate G to the register I3 which functions as a counter in this case. In response to the output of the register I3, the transistors Trare turned on and off so that the analog voltage representing the Content in the register 13 is derived from the differential amplifier A and is applied to the other input terminal of the comparator 14. When the content in the register 13 is shifted so that the output of the differential amplifier A coincides with that of the amplifier A,, the coincidence signal is derived from the comparator I4 and applied to the flipflop 15 so that the latter is reset. As a result, the gate G is closed so that the clock signals are interrupted to be applied to the register 13. In this case, the content in the register 13 represents the quotient A/B.

Next the mode of multiplication will be described. A multiplicand is set into the register 12 whereas a multiplier, into the register I3. The register 11, which now functions as a counter, steps in response to the clock signals. When the output voltage of the amplifier A, co incides with that of the amplifier A the clock pulses are interrupted to be applied to the register II. (The circuit for this purpose is now shown). The content in the register 11 represents the product B-C.

What is claimed is:

I. A hybrid arithmetic, device comprising:

a first stage including a first resistor, a Zener diode connected to said first resistor, a first transistor am plifier having an output and an input, second and third resistors connected to the output of said first transistor amplifier, a first operational amplifier having a plurality of inputs and an output, the output thereof being connected to the input of said first transistor amplifier, one of said inputs of said first operational amplifier being connected to the point of interconnection between said Zener diode and said first resistor, the other input of said first operational amplifier being connected to a feedback path from the output of said first transistor amplifier;

a second stage including a second transistor amplifier having an input and an output, fourth and fifth resistors connected to the output of said second transistor amplifier, a second operational amplifier having a plurality of inputs and an output, the output of said second operational amplifier being connected to the input of said second transistor amplifier, one of the inputs of said second operational amplifier being connected to the output of said first transistor amplifier and the other input thereof being connected to a feedback path from the output of said second transistor amplifier;

means for setting the values of at least a selected pair of said resistors to selected digital values representing the values of arithmetic operands so as to derive across the fifth resistor an output voltage whose value is a measure of the result of a selected arithmetic operation on said operands.

2. A hybrid arithmetic device as defined in claim I, in which the second and the fifth, output resistor are set to the values of a multiplicand and a multiplier, respectively, and the value of the output voltage is proportional to the product of said multiplicand and multiplier.

3. A hybrid arithmetic device as defined in claim 1, in which the third and fifth resistor are set respectively to the values of a divisor and a dividend, respectively, and the value of the output voltage is proportional to the quotient of said dividend and divisor.

4. A hybrid arithmetic device as defined in claim 1, in which the setting means comprise digital-to-analog converter means for converting the value of a selected digital quantity into an analog resistance value.

5. A hybrid arithmetic device as defined in claim I, in which a plurality of additional stages, substantially identical to said second stage, are connected in parallel to the output of said second transistor amplifier, a resistor in each of said additional stages being representative of a particular dividend in relationship to a common divisor represented by said second resistor, another resistor in each of said additional stages being representative of a particular quotient resulting from the dividing operation.

Claims

1. A hybrid arithmetic, device comprising: a first stage including a first resistor, a Zener diode connected to said first resistor, a first transistor amplifier having an output and an input, second and third resistors connected to the output of said first transistor amplifier, a first operational amplifier having a plurality of inputs and an output, the output thereof being connected to the input of said first transistor amplifier, one of said inputs of said first operational amplifier being connected to the point of interconnection between said Zener diode and said first resistor, the other input of said first operational amplifier being connected to a feedback path from the output of said first transistor amplifier; a second stage including a second transistor amplifier having an input and an output, fourth and fifth resistors connected to the output of said second transistor amplifier, a second operational amplifier having a plurality of inputs and an output, the output of said second operational amplifier being connected to the input of said second transistor amplifier, one of the inputs of said second operational amplifier being connected to the output of said first transistor amplifier and the other input thereof being connected to a feedback path from the output of said second transistor amplifier; means for setting the values of at least a selected pair of said resistors to selected digital values representing the values of arithmetic operands so as to derive across the fifth resistor an output voltage whose value is a measure of the result of a selected arithmetic operation on said operands.

2. A hybrid arithmetic device as defined in claim 1, in which the second and the fifth, output resistor are set to the values of a multiplicand and a multiplier, respectively, and the value of the output voltage is proportional to the product of said multiplicand and multiplier.

5. A hybrid arithmetic device as defined in claim 1, in which a plurality of additional staGes, substantially identical to said second stage, are connected in parallel to the output of said second transistor amplifier, a resistor in each of said additional stages being representative of a particular dividend in relationship to a common divisor represented by said second resistor, another resistor in each of said additional stages being representative of a particular quotient resulting from the dividing operation.