US3885323A

US3885323A - Signal conversion system

Info

Publication number: US3885323A
Application number: US337225A
Authority: US
Inventors: Frederick C Kaase; Wilson C Selden
Original assignee: Singer Co
Current assignee: CAE Link Corp
Priority date: 1973-03-01
Filing date: 1973-03-01
Publication date: 1975-05-27
Anticipated expiration: 1992-05-27

Abstract

A signal conversion system which employs a random access memory for storing signals, and further including means for generating a first address for storing the signals and a second address for retrieving the stored signals is disclosed in this specification. The first set of addresses is generated in accordance with a first mathematical function, and the second set of addresses is generated in accordance with a second mathematical function. The input signal is periodically sampled, and an analog-to-digital converter is provided for converting the input signal from an analog form to a digital form for storage in the memory in accordance with the first set of addresses. A digital-to-analog converter is provided for converting the digital signals retrieved from the memory in accordance with the second set of addresses into an analog form. Control signals are generated for generating the first and second sets of addresses and for synchronizing the operation of the individual constituent circuits.

Description

United States Patent Kaase et al.

[ 1 SIGNAL CONVERSION SYSTEM [75] inventors: Frederick C. Kaase, Sunnyvale;

Wilson C. Selden, San Jose, both of Calif.

[73] Assignee: The Singer Company, New York,

[22] Filed: Mar. 1, 1973 [21] Appl. No.: 337,225

[52] US. Cl. 35/l0.4 [5 1] Int. Cl. G09b 9/00 [58] Field of Search 35/l0.4

[56] References Cited UNITED STATES PATENTS 3,764,719 10/1973 Dell 35/104 3,80l,720 4/l974 Rymer 35/104 Primary Examiner-T. H. Tubbesing Attorney, Agent, or Firm-Paul M. Hentzel; William Grobman May 27, 1975 [57] ABSTRACT A signal conversion system which employs a random access memory for storing signals, and further including means for generating a first address for storing the signals and a second address for retrieving the stored signals is disclosed in this specification. The first set of addresses is generated in accordance with a first mathematical function, and the second set of addresses is generated in accordance with a second mathematical function. The input signal is periodically sampled. and an analog-to-digital converter is provided for converting the input signal from an analog form to a digital form for storage in the memory in accordance with the first set of addresses. A digitalto-analog converter is provided for converting the digital signals retrieved from the memory in accordance with the second set of addresses into an analog form. Control signals are generated for generating the first and second sets of addresses and for synchronizing the operation of the individual constituent circuits.

26 Claims, 23 Drawing Figures SIMULATION COMPUTER SYSTEM J RADAR IMAGE F" GENERATOR TIME BASE CONVERTER IIO CARRIER FREQUENCY CONVERTER RADAR DISPLAY SHEU [BEEF i4 TIME Rg SWEEP GATE 505i FSS SWEEP GATE I RADAR MAIN BANG GENERATOR I06 OUTPUT CONVERTOR I08 OUTPUT Pi -i211?kiAYZYiSYS $885,323

SHEET G35F 1T,

r r r 63/ H8 ANALOG- 605 ANALOG- DATA 633 637 0% TO To i) RAM AN A LOG DIGITAL CONVERSION DRIVER CONVERTER 607 CIRCUIT ADDRESS 608 s09 '08 c| oc| 6/! AND TIMING T c:Rcu|T a29 V 6/5 625 Fig-6 3 -R MEMORY 6/9? GENERATOR ADDRESS 62, 5L CIRCUIT CONTROL 623? CIRCUIT 705 36 MHZ CLOCK OSCILLATOR GENERATOR GATING NETWORK SHEET C DF 14 S-BIT COUNTER 222 nsec m, 'ggrmmims 3.885.323

SHEET [29 0F 14 PATENTED W2 71975 SHEET lZUF 13 D A a 6 C 629A K MULTI- PLEXER Cl RCUIT MULTI- PLEXER CIRCUIT C 29 PATENTED HAYZYIGYS 3,885,323

RESISTOR NETWORK AND AMPLIFI CIRCUIT F lg. 23

1 SIGNAL CONVERSION SYSTEM BACKGROUND OF THE INVENTION l. Field of the Invention This invention relates to simulators for training personnel in the operation of aircraft radar equipment, and more particularly to an improved apparatus for realistically simulating images displayed by radar equipment employed in aircraft flight simulators.

2. Description of the Prior Art In the past, aircraft flight simulators have employed auxiliary devices for generating synthetic representations of the environment which would typically surround such simulated aircraft in flight; and for generating signals to operate instruments and indicators which are typically employed in such simulated aircraft. One such auxiliary device is an aircraft radar simulator.

Aircraft radar equipment normally includes a transmitter of very high frequency electromagnetic energy pulsed at a predetermined rate and a receiver which responds to the portion of the transmitted energy reflected from an object of the terrain. The output of the radar receiver is coupled to a cathode ray tube (CRT) which is employed as the radar display means. The electron beam ofthe CRT scans radial lines from an in itial point representing the position of the aircraft itself, and light blips or spots representing objects or targets will appear on the CRT at radial distances from the initial point corresponding to the range or distance that the actual objects or terrain features bear with respect to the aircraft. A plurality of the radial lines are rapidly scanned in a sequence, and the light blips or spots are combined by the radar equipment in order that a maplike display be provided on the CRT with various terrain features and other objects appearing as light spots in sealed relation with the aircrafts location. The range or distance is representative of the slant range from the aircraft to the terrain features and other objects.

The simulation of actual aircarft radar equipment is often accomplished by employing at least one flying spot scanner (PS8) or other light source to synchronously scan a pair of photographic transparencies wherein various shades of gray on the first of the transparencies in encoded to represent radar reflectance information, and a second of the transparencies is encoded to represent elevation information. The modulated light passing through the transparencies is thereafter converted into video signals and operated upon to provide input signals for the radar display means. An example of this type of simulator is disclosed in US. Pat. Nos: 3,031,774; 3,067,526; 3,l00,328; 3,1 13,989; and 3,29l ,884.

Another type of radar simulator presently being used employs a single F55 and a transparency containing both elevation and reflectance information colorcoded onto the transparency. The modulated light passing through the transparency is collected and decoded into a plurality of discrete signals, and these signals are operated upon to provide a combined video signal for the simulated radar CRT.

These radar simulators generate radar video signals by radially scanning the transparencies with the FSS from a point indicative of aircraft ground position to objects on the terrain. The radar video signal thus generated is linear with respect to a ground range time base. Since the actual aircraft radar video is linear with respect to a slant range time base, the synthetically gcnerated video signal from the radar simulator must be converted to a video signal linear with respect to slant range time base.

One such device presently available on the market for converting radar video from a linear ground range time base to a linear slant range time base is a dual electron beam scanconverting vacuum tube, or a storage tube. This scan'eonverting tube employs two opposing electron guns disposed coaxially with an electron charge-storage screen located between the two electron guns. The electron beam from a first of these two electron guns is directed toward one side of the chargestorage screen, and the electron beam from the second electron gun is directed toward the second side of the charge-storage screen. A separate deflection means is provided for each electron beam. In general operation, the first electron beam is deflected in a predetermined pattern, and the beam is further modulated to cause disruptions in the electron charges on the chargestorage screen. A pattern of the disrupted charges is thereby made on the charge-storage screen. The second electron beam may be deflected in the same or a different pattern to detect, with a secondary collector electrode, the pattern of disrupted charges made by the first electron beam. This type of scan-converting tube, or storage tube, is described in greater detail in Television" by V. K. Zworykin and G. A. Morton, Second Edition, on pages 377 and 378.

As used in radar simulators, the first electron beam of the scan-converting tube is deflected by a non linear signal representative of the simulated aircraft's slant range, which signal is derived from the linear ground range time base of the radar simulator in combination with the aircraft altitude above the terrain. The first electron beam is modulated by the synthetic video from the radar simulator. The pattern of disrupted charges produced on the charge-storage screen, as a result of the deflection and modulation, is representative of a spatial distribution of the slant range video signal. The second electron beam scans the charge-storage screen and the resulting analog signal produced at the secondary collector electrode is representative of video linear with respect to the slant range time base. However, it is pointed out that the second electron beam is delayed in time from the scanning operaton of the first electron beam for an amount of time sufficient to pre clude simultaneous production of charge-storage by the first electron beam and the scanning of the chargestorage from the same element on the screen by the second electron beam.

The prior art scan-converting tube is not reliable over any reasonable period of time in that it requires fre quent and precise realignment as a result of serious short-term drift, and in that the tube must be replaced periodically as a result of a relatively short life cxpec tancy.

SUMMARY OF THE INVENTION According to the present invention, a storage means is disposed for randomly storing discrete manifestations of the video information from an FSS of a radar simulator. Video information is entered into the memory at an address whose numerical value is proportional to the instantaneous difference between the radar slant range distance and the radar ground range distance. The video information is retrieved sequentially from the storage means. Electronic circuits are provided for generating an address for retrieving video information from the memory; and for controlling the timing of all circuitry.

A general object of this invention is the provision of a novel apparatus for converting radar simulator video signals into a realistic representation of the simulated operaton of aircraft radar equipment.

Another object is the provision of a new and improved solid-state electronic circuit for converting radar simulator video signals which are generated linearly with respect to a ground range time base into radar video signals which are linear with respect to a slant range time base.

Another object is the provision of an improved means for converting radar simulator video signals from one time base to another time base, which means employs a high-speed random access memory.

A further object is the provision of a radar simulator video time base converter which, in comparison to those previously known, is simpler in construction, lower in cost, and more reliable in operation.

A primary advantage of the present invention over similar devices of the prior art is that solid-state electronic circuitry is employed, which circuitry improves the reliability of operation.

These and other objects and advantages of the present invention will become clear to one normally skilled in the art from perusal of the appended specification when taken in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a simulator system in which the apparatus of the present invention may be used;

FIG. 2 is a diagram of the geometric relationship between ground range R,,, slant range R and altitude )2;

FIG. 3 is a diagram illustrating the distance-to-time relationship of R,, R,, and h prior to a time base conversion by the present apparatus;

FIG. 4 is a diagram illustrating the distance-to-time relationship of R,,, R and h following a time base conversion by the present apparatus;

FIG. 5 is a timing diagram of the signals supplied to the present apparatus and the video signal provided at the output following a time base conversion;

FIG. 6 is a block diagram of one form of the apparatus of the present invention;

FIG. 7 is a block diagram of the clock and timing circurt:

FIG. 8 is a logic-block diagram of the clock generator of FIG. 7;

FIG. 9 is a timing diagram for the circuit of FIG. 8;

FIG. 10 is a logic diagram of the gating network of FIG. 7;

FIG. 11 is a timing diagram for the circuitry shown in FIG. 10;

FIG. 12 is a schematic-block diagram of the analogto-digital driver circuit;

FIG. 13 is a logic-block diagram of the analog-todigital converter;

FIG. 14 is a schematic-logic diagram of the analog comparator circuit of FIG. 13',

FIG. 15 is a logic diagram of the encoder of FIG. 13;

FIG. 16 is a schematic-block diagram of the R, R generator;

FIG. 17 is a logic diagram of the conditioning logic and count limiter circuit of FIG. 16;

FIG. 18 is a block diagram of the memory address control circuit;

FIG. 19 is a logic-block diagram of the read/write multiplexer of FIG. 18;

FIG. 20 is a logic diagram of the control logic for the read address counter, multiplexer, and random access memory of FIG. 18;

FIG. 21 is a logic diagram ofthe write address control logic of FIG. 18;

FIG. 22 is a logic diagram of the read enable logic of FIG. 18; and

FIG. 23 is a logic-block diagram of the digital-toanalog converter circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings in detail, and to FIG. 1 in particular, the reference character 101 designates a simulation computer which may, for example, comprise a conventional digital computer programmed for simulating aircraft. Data is supplied from computer 101 to a radar simulator 102 via a line 104. This output data is indicative of such things as simulated aircraft position, altitute, etc. Radar simulator 102 comprises a radar image generator 106 which receives the information from the computer 101 and has its output connected to an input of a time base converter 108 whose output is connected to the input of a carrier frequency converter 110 which feeds a portion of a radar receiver 112 and a radar display 114 connected to the output of the receiver 112. Simulation computer 101 also supplied data to a system timing circuit 116. The timing circuit generates a plurality of waveforms for controlling the radar simulator 102. More particularly. timing signals from circuit 116 are supplied as inputs to radar image generator 106, time base converter 108, and the radar display 114.

The radar image generator 106 generates synthetic radar video by scanning one or more transparencies containing information representative of terrain elevation and reflectance information. The scanning is usu ally performed by a beam of light, such as generated by a flying spot scanner. moving in a prescribed pattern, and then the light, which is modulated by its passage through the transparencies is converted into electrical signals. The output of radar image generator 106 is supplied to the input of the time base converter 108 via line 118. The time base converter 108. which constitutes the apparatus of the present invention, converts the video signals, generated lineariy with respect to ground range, to video signals which are linear with respect to slant range. The frequency converter 110 modulates a carrier frequency (for example, 30 MHz) with the video converted by converter 108. Only a portion of receiver 112 is used, and the carrier modulated with the radar video from converter 110 is connected direetly to the intermediate frequency (I.F.) portion of receiver 112. The output of receiver 112 activates radar display 114 to display the synthetic video generated by scanning the transparency(s). The operation of the FSS within the radar image generator 106 is synchronized with the sweep circuitry of the radar display 114 by the timing signals supplied from circuit 116. Also, as will be shown in greater detail hereinbelow, the operation of the time base converter 108 is operated in synchronization with the same timing signals supplied from circuit 116.

In FIG. 2 the relationship is shown between the ground range and the slant range of the radar beam from the aircraft 201 to an object 202 on the ground. A triangle is formed by the slant range R,, the ground range R and the altitude of the aircraft 201. The altitude of the aircraft 201 is computed from the actual altitude of the aircraft 201 above sea level less the elevation of the object 202. The ground range is the horizontal distance from the point of intersection of a vertical from the aircraft with the ground and the object 202. These values are computed by the computer 101 in accordance with information originally stored therein or supplied from the transparencies mentioned above.

The angle formed by sides R and R is designated hereafter as angle 6. A line 204 drawn perpendicular to slant range side R and intersecting the right angle formed between sides It and R forms an angle 6' between line 204 an side h. In accordance with the laws of geometry, angle is equal to the angle 6.

Hypotenuse R is divided by the point of intersection with the line 204 into portions .1: and y. The portion x is equal to the distance between the aircraft 201 and this point of intersecton, and the portion y is equal to the distance between object 202 and the intersection of line 204 with hypotenuse R... It may be readily seen from the diagram of FIG. 2 that R, is equal to the sum ofx and y. In accordance with the laws of trigonometry, the portion x is equal to hSin 6; and the portion y is equal to R Cos 6. This relationship is expressed mathematically as follows:

R, hSin 9' R,,Cos 6 The value for angle 6 ranges from a maximum of 90 when the radar is sweeping beneath the aircraft, to a minimum angle when the radar is sweeping ahead of the aircraft. At the beginning of the radar sweep, angle 0 is equal to 90, and R is thereby equal to 11 since Sin 90 equals l and Cos 90 is equal to zero. As time progresses angle 8 becomes very small, and R is approximately equal to R since the Sine ofa small angle is very small and the Cos of the same angle approaches 1. This relationship may be more fully understood from the diagram of FIG. 3 illustrating both the relationship of R and R, in a plot of distance versus time.

With reference to FIG. 3, curve 301 represents the linear relationship of R, for distance versus time, and curve 303 represents the relationshp of R (as a func tion of R, and h) versus time. The vertical axis represents distance and the horizontal axis represents time. In particular, time t represents the beginning of R sweep time, and also corresponds to the beginning of a single sweep by the FSS within the radar image generator 106. As stated hereinabove, the FSS scans from a point on the transparency corresponding to the aircraft ground position to points on the transparency which would be ahead of and in the direction of the radar line of sight. The scanning operaton of the FSS is linear; and, therefore, the plot of R,, for distance versus time is linear as represented by curve 301.

Curve 303 is a mathematical plot of equation [l] given hereinabove. Curve 303 intersects the vertical (or distance) axis at a value equal to it, since the value for R, is equal to h when angle 6 is coal to 90.

As time t increases, angle 0 decreases, and the value for R, approaches the value for R This is represented in FIG. 3 by curve 303 approaching curve 301 asymptotically as time 1 increases. That is, the value for R, approaches the value for R,, as angle 0 approaches 0. With reference to the prior art scan-converting device described hereinabove, curve 303 is representative of the shape of the deflecting signal employed in the scanconverting tube for deflecting the first electron beam.

The apparatus of the present invention performs the time base conversion by delaying discrete samples of the video signal from generator 106 for an amount of time proportional to the instantaneous difference between the values for R, and R,,. In particular, the amount of this time delay for any given time t (measured on the horizontal time axis) is equal to the vertical difference between curve 303 and curve 301 multiplied by a constant proportionately K, wherein K is equal to l microsecond per 500 feet.

FIG. 4 illustrates the distance versus time relationship of R, and R following a time base conversion by the apparatus of the present invention. The vertical axis represents distance and the horizontal axis represents time. Curve 401 illustrates ground range R,,, and curve 403 represents slant range R,. Note that curve 403 is linear and represents the desired time base for displaying the radar simulator video on the CRT. Curve 401 represents the nonlinear variation of ground range fol lowing the conversion to a linear slant range. The point at which curve 401 intersects the horizontal (or time") axis represents a time delay (t,,) proportional to altitude h. It is pointed out that the horizontal incremental difference between

curves

403 and 401 represent the amount of time delay to be applied to each discrete sample of video from image generator 106. As will be shown in greater detail hereinbelow, the amount of time delay is effected by the use of a random access memory which stores data randomly at address locations proportional to the instantaneous horizontal difference between

curves

403 and 401, and retrieves data from the RAM sequentially at an address location represented by curve 403.

Referring now to FIG. 5, the timing signals from circuit 116, and the video signals from both the image generator 106 and the time base converter 108 are illustrated with the timing relationship therebetween. Waveform 501 illustrates the linear R, SWEEP signal indicative of the linear sweeping relationship of terrain objects and features from a transparency by the FSS. Waveform 503 illustrates the R SWEEP GATE signal, which signal is at a high level during the time that waveform 501 is linearly increasing in magnitude. Waveforms 501 and 503 both begin positive transitions at time t, wherein i represents the time at which a given simulated radar sweep begins.

Waveform 505 is the FSS SWEEP GATE signal, which signal is indicative of the operation of the FSS for the sweeping of a single line on the transparency. Waveform 505 begins a positive transition at time I wherein time t represents the beginning of operation of the FSS for a given simulated radar sweep. The time interval between time 1 and time I, is provided to allow sufficient time for the FSS to turn on and stabilize operation prior to the given simulated radar sweep beginning at time t Waveform 507 represents the RADAR MAIN BANG signal, which signal is representative of the beginning of the simulated operation of the radar equipment during the given radar sweep. The positive transition oi'the RADAR MAIN BANG signal is approximately microseconds in time duration, and occurs approximately 60 microseconds after time I The 60 microsecond time delay is nominal, and prevents the two electron beams of the dual beam storage tube from simulta neously operating on the same point of the storage screen.

Waveform 509 represents slant range R, as a function of R, and h during a given radar sweep. The shape of this waveform between times I and is identical to that of curve 303, and is employed in the prior art scan conversion tube as the first electron beam deflection signal. As will be shown in greater detail hcreinbelow, this waveform is employed in the apparatus of the pres ent invention in conjunction with waveform 501 to generate instantaneous differences between slant range R, and ground range R,,. The instantaneous differences between these two waveforms is used for providing a memory address for entering information into the memory.

Waveform 511 represents the radar video signal gen erated in generator 106 for a single sweep by the FSS, which signal is linear with respect to the ground range time base. Waveform 513 represents the video signal 8 provided at the output of the digital time base converter 108, which signal has been converted to a video signal linear with respect to slant range time base. The video signal shown by waveform 513 between times and I is the video signal shown by waveform 511 between times t, and r which has been converted to a lin ear slant range time base. Time I, is analogous to the nadir point of the given radar scan as generated by the radar simulator. Time is analogous to the nadir point of the given radar sweep of the video signal to be displayed on the simulator CRT. It is also pointed out that the time delay between times I, and is is the same as the time delay between times and That is, the delay of the RADAR MAIN BANG signal affects a similar delay in the resultant video signal supplied from the time base converter 108. It is also pointed out that the time delay between times and i is the same amount of time delay as represented by the horizontal distance between

curves

403 and 401 along the time axis of the diagram of FIG. 4.

The time base converter 108 is shown in greater detail in HO 6. An input line 118 to an analog-to-digital driver 601 is connected to the output of the radar image generator 106 as shown in FIG. 1. The output from the A/D driver 601 is applied to the input of an analog-todigital converter 603, throughout a line 605 is connected to the input of a read-only memory (RAM) 606 through a line 607. Another input to the converter 603 comes from the output 613 of a timing and synchronization circuit 608. The output of the RAM 606 is applied to the input of a digital-to-analog conversion circuit 631. In addition to the input from the A/D converter 603, the RAM 606 also receives an input from the output 629 of a memory address control circuit 625, whose input is supplied by a difference generating circuit 615 at output 627. The timing and synchronizing circuit 608 supplies signals to time and synchronize the RAM 606. the D/A converter 631, the difference generating circuit 615 and the memory address control circuit 625 also, all through a line 613. The difference generating circuit 615 receives interface input signals on

lines

617, 619, 621, and 623 from image generator 108. Line 617 has the ground range (R,,) sweep signals (waveform 501 l applied to it; the negative slant range (*R.) sweep signal (waveform 509) is applied to line 619; and two image controlling signals are applied to the

lines

621 and 623 for determining the operating range of the simulated radar. The

lines

621 and 623 are also connected as inputs to the memory address control circuit 625.

The signal applied to the line 621 selects the mile range (for example] of the radar set to be displayed, and the signal on the line 623 selects the 200 mile range. When neither of the

lines

621 and 623 carries a signal, the system selects the 40 mile range.

Binary numbers retrieved from RAM 606, which numbers are a binary manifestation of the video signal linear with respect to slant range time base, are supplied to the input of a digital-to-analog conversion cir cuit 631 via lines 633. Circuit 631 is controlled by one of the timing signals on lines 613. The output of circuit 631 is an analog signal representative of video which has been converted to a linear slant range time base, and is supplied to the frequency converter (FIG. 1) via line 637. The signal supplied at the output of converter 110 is a high frequency carrier signal which has been modulated by the video signal supplied on line 637. The output signal from converter 110 is supplied to the l.F. strip of the radar receiver 112.

In operation, the video signal which is linear with respect to ground range time base, and is supplied at the output of radar image generator 106 is supplied to the input of driver 60] via line 118. A plurality of analog signal comparator circuits are employed within driver 601 to separate the video signal on line 118 into four discrete bands of analog signals. These four bands of analog signals are supplied to converter 603 via lines 605. Converter 603 converts the four bands of analog signals supplied thereto into a binary number having a value proportional to the magnitude of the input analog signals. Additionally, converter 603 has provisions for scaling the binary numbers into weighted values in accordance with fine, medium, and coarse transitions of the input video signal on line 118.

Control and synchronization of the operation of the circuitry of the time base converter 108 is supplied by the circuit 608. A plurality of clock timing signals are generated by the circuit 608 to control individual steps of the time base conversion during a given sweep of the F88. The timing signals supplied on lines 609 (R SWEEP GATE) and 611 (PS5 SWEEP GATE) are employed in circuit 608 to generate additional control signals to effect the synchronization of operation of time base converter 108 to the remaining circuitry of the radar simulator. These signals will be explained in greater detail hereinbelow.

Generator 615 generates the instantaneous algebraic sum of the varying values of the R SWEEP signal and the R SWEEP signal supplied on

lines

617 and 619. A binary number is provided at the output of circuit 615 which is indicative of this instantaneous sum between R and R The binary number representative of the instantaneous sum between R, and R,, is supplied to circuit 625 via lines 627.

It is the function of circuit 625 to supply an address to RAM 606 via lines 629 during a first time interval for entering data into the memory via lines 607, and for retrieving data from the RAM 606 on lines 633 during a second time interval. The binary numbers retrieved from the RAM 606 are supplied to conversion circuit 631 via lines 633.

Conversion circuit 631 converts the binary numbers retrieved from the RAM into an analog signal representative of the video signal which is linear with respect to slant range time base. This signal is supplied on line 637 to frequency converter 110.

In summary, the operation of the time base converter 108 is to sample the video signals supplied on line 118 periodically; store this smaple of the video signal into the RAM 606 at an address proportional to the instantaneous difference between R and R to sequentially retrieve the stored information from the RAM 606; and, convert the information retrieved from the RAM 606 back into an analog signal representative of a video signal linear with respect to slant range time base.

Referring now to FIG. 7, the clock and timing circuit 608 is illustrated in block diagram form. A 36 Megahertz oscillator 701 supplies an oscillatory voltage to a clock generator 703 via a line 705. Oscillator 701 may comprise, for example, a conventional free-running multivibrator. Clock generator 703 uses the clock pulses supplied on line 705 to produce eight subclock signals which will be referred to hereinafter as 01 through 08. Subclock signals 01 through 08 are employed for timing other circuitry of this invention, as will be explained in greater detail hercinbelow.

The 05 and the O8 subclock signals are supplied as inputs to a gating network 707. The R, SWEEP GATE signal generated in timing circuit 116, and represented by waveform 503, is supplied as an input to gating network 707 via line 609. Also, the FSS SWEEP GATE signal supplied from timing circuit 116, and represented by waveform 505, is supplied as an input to gating network 707 via line 611. The signals provided at the output of gating network 707 are defined as follows: an inversion of the 05 signal on line 713; a BUFF- ERED R SWEEP GATE signal on line 715; a CLOCKED R, SWEEP GATE signal on line 716; a (R, R,,) GENERATOR REGISTER ENABLE signal on line 717; a MASTER ZERO signal on line 719; a BUFFERED FSS SWEEP GATE signal on line 721; a MASTER CLEAR signal on line 723; and, an ALTI- TUDE h DATA TRANSFER signal on line 725. The generation and detailed explanation of these signals will be described in greater detail hereinbelow Also, the operation of the clock and timing circuit 608 will be explained in greater detail following a description of the circuitry comprising generator 703 and network 707.

Referring now to FIG. 8, clock generator 703 is illustrated in greater detail. The 36 Megahertz oscillatory signal from oscillator 701 is supplied to the toggle input of a binary counter stage 801. The oscillatory signal at the output of counter stage 801 is an 18 Megahertz oscillatory signal, which is supplied to the count input of a 3-bit counter 803. Counter 803 may comprise any conventional binary counter however, it is preferred that counter 803 be a closed-ring counter. That is, when the contents of the counter 803 reaches the counter capacity, it resets to a count of zero. The signals at the output of counter 803 represent the binary value of the contents of the counter. The signal supplied on an output line 805 represents a binary count of 2"; the signal supplied on an output line 807 represents a binary count of 2; and, the signal supplied on an output line 809 is representative of a binary count of 2 Line 805 is connected to an inverting input ol an AND gate 811; an inverting input of an AND gate 813; an inverting input of an AND gate 815; a direct input of AND gate 817; an inverting input of an AND gate 819; a direct input of an AND gate 821; an inverting input of an AND gate 823; and, a direct input of an AND gate 825. Line 807 is connected to an inverting input of the AND gate 811; a direct input of the AND gate 813; an inverting input of the AND gate 815; an inverting input of the AND gate 817; a direct input of the AND gate 819; a direct input of the AND gate 821; a direct input of the AND gate 823; and, a direct input of the AND gate 825. The line 809 is connected to an inverting input of the AND gate 811; an inverting input of the AND gate 813; a direct input of the AND gate 815; a direct input of the AND gate 817; an inverting input of the AND gate 819; an inverting input of the AND gate 821; a direct input of the AND gate 823; and, a direct input of the AND gate 825. The output of the AND gate 811 is connected to an input of inverter 827, and the output of inverter 827 constitutes the 01 signal. The output of the AND gate 813 is connected to an input of an inverter 829, and the output of inverter 829 constitutes the 02 signal. The output of the AND gate 815 is connected to an input of inverter 831, and the output of inverter 831 constitutes the 03 signal. The output of the AND gate 817 is connected to an input of inverter 833, and the output of inverter 833 constitutes the 04 signal. The output of the AND gate 819 is connected to an input of inverter 835, and the output of inverter 835 constitutes the 05 signal. The output of the AND gate 821 is connected to an input of inverter 837, and the output of inverter 837 constitutes the 06 signal. The output of the AND gate 823 is connected to an input of inverter 839, and the output of inverter 839 constitutes the 07 signal. The output of the AND gate 825 is connected to an input of inverter 841, and the output of inverter 841 constitutes the 08 signal.

In operation, the 36 Megahertz oscillatory signal supplied at the input to binary counter stage 801 is effectively divided by two since only positive transitions of the signal supplied to the input of the stage will cause a change in state at the 1 output of the counter stage. The 18 Megahertz signal supplied to the count input of counter 803 increments the counter from a count of 000 to a count of l l I, wherein the counter 803 is again reset to a count of 000. This operation continues in this manner independently without interruption from external circuitry. When the contents of counter 803 are 000, the AND gate 811 is enabled and a high-level signal is supplied to the input of inverter 827. The signal at the output of inverter 827 is at a low level when the signal from the output of the AND gate 811 is at a high level. Similarly, when the contents of counter 803 are 111, the AND gate 825 is enabled and the output of the inverter 841 goes to a low level. Each of the AND gates 813 through 823 are enabled in response to unique binary values within the counter 803. The relationship of the 01 through 08 subclock signals, and the oscillatory voltage supplied on line 705 may be more fully under stood from the description of the timing diagram hereinbelow.

With reference to FIG. 9, waveform 901 represents the 36 Megahertz oscillatory signal supplied on line 705 from oscillator 701. Waveform 903 represents the 18 Megahertz signal provided at the output of counter

Claims

1. A method for converting a first signal which varies in accordance with a First mathematical function into a second signal which varies in accordance with a second mathematical function, said method comprising the steps of: a. sampling said first signal; b. generating a first address in accordance with the instantaneous difference between said first and second mathematical function; c. utilizing said first address for storing manifestations of said first signal samples in a storage means during a first time interval; d. generating a second address proportional to said second mathematical function; and e. utilizing said second address for retrieving said stored manifestations from said storage means during a second time interval, wherein said retrieved manifestations correspond to said second signal in accordance with said second mathematical function.

2. The method as defined in claim 1, wherein the step of generating said first address further comprises the steps of: a. deriving a first number representative of the instantaneous difference between said first mathematical function and said second mathematical function; b. generating a second number uniformly increasing in value; and c. combining said first number with said second number to produce said first address.

3. The method as defined in claim 2, wherein the step of generating said second address further comprises the step of generating a third number uniformly increasing in value to produce said second address.

4. The method as defined in claim 2, wherein said deriving step includes the steps of: a. algebraically summing a first signal proportional to said first mathematical function with a second signal proportional to said second mathematical function to generate a third signal varying in amplitude; b. comparing the amplitude of said third signal with a reference potential to produce first and second composite signals each of which represents a polarity of the difference between said third signal and said reference potential; c. incrementing a digital counter in response to said first composite signal representative of one polarity of said difference; d. decrementing said digital counter in response to said second composite signal representative of the other polarity of said difference; e. converting said first number derived by incrementing said digital counter into an analog form; and f. modifying the amplitude of said third signal with the amplitude of said analog form of said first number to maintain proportionality between the amplitude of said third signal and the value of said first member.

5. The method as defined in claim 1, wherein the step of sampling said first signal in accordance with said first mathematical function includes the steps of: a. producing from each of said samples a plurality of individual amplitudes which together represent the value of the sample; b. converting all of said amplitudes into a digital number which represents said value with each of said amplitudes being converted at its own digital resolution; and c. encoding said digital number into manifestations of said sampled signal.

6. A system for converting a first signal which varies in accordance with a first mathematical function into a second signal which varies in accordance with a second mathematical function, said system comprising: a. means for sampling the first signal in accordance with said first mathematical function; b. means having a data input coupled to the output of said sampling means for storing manifestations of the sampled signal; c. means having an output coupled to an address input of said storage means to generate a first address for storing said manifestations in said storage means; d. means having an output coupled to the address input of said storage means to generate a second address for retrieving said stored manifestations from said storage means; e. means for utilizing said first address for storing said manifestations in said storage means during a First time interval and for utilizing said second address for retrieving said manifestations from said storage means during a second time interval, wherein said retrieved manifestations are representative of the first signal in accordance with said second mathematical function; and f. means for controlling said sampling means, said storage means, and said first and said second address generating means for coordinated synchronous operation.

7. The system as defined in claim 6, wherein said first address generating means comprises: a. means for deriving values representative of instantaneous differences between said first mathematical function and said second mathematical function; b. a first counting means disposed for providing a uniformly increasing output value; c. an adding means having a first set of adding inputs coupled to the output of said counting means and having a second set of adding inputs coupled to the output of said deriving means; and d. means coupling the output of said adding means to the address input of said storage means.

8. The system as defined in claim 7 wherein said second address generating means comprises: a. a second counting means disposed for providing a uniformly increasing output value; and b. means for coupling the output of said second counting means to an address input of said storage means.

9. The system as defined in claim 8 wherein said means for sampling the signal comprises: a. means for producing a plurality of component signals which together represent the value of said signal samples; b. means for converting said component signals individually into digital components with each component signal being converted at its own resolution; and c. means for encoding said digital components into a single digital word which represents the value of said signal sample.

10. The system as defined in claim 7, wherein said deriving means includes: a. means for algebraically subtracting a first signal proportional to said first mathematical function from a second signal proportional to said second mathematical function to produce a third signal which varies in amplitude; b. means for comparing the amplitude of said third signal with a reference potential to produce composite signals each of which represent a first and second polarity; c. a digital counter coupled to said comparing means and adapted to increment in response to said first polarity representative of one of said composite signals, and adapted to decrement in response to said second polarity of another one of said composite signals, wherein the contents of said counter is said value representative of the instantaneous differences between said first mathematical function and said second mathematical function; d. means for converting the output of said digital counter into an analog signal which varies in amplitude in accordance with the output of said counter; e. means for comparing the analog output of said counter with said third signal to generate an error signal proportional to the difference therebetween; and f. means for adjusting the contents of said counter to reduce said error signal to zero.

11. The system as defined in claim 6 wherein said second address generating means comprises: a. a second counting means disposed for providing a uniformly increasing output value; and b. means for coupling the output of said second counting means to an address input of said means.

12. The system as defined in claim 6 wherein said means for sampling the signal comprises: a. means for producing a plurality of component signals which together represent the value of said signal samples; b. means for converting said component signals individually into digital components with each component signal being converted at its own resolution; and c. means for encoding said digital components into a single digital word which represents the value of said signal sample.

13. The systeM as defined in claim 6 wherein said storage means comprises a random access memory.

14. The system as defined in claim 6 wherein said means for controlling comprises: a. a source of clock pulses; b. means for generating sub-clock pulses which exist for equally spaced time intervals between said clock pulses; c. means for applying at least one of said sub-clock pulses to said sampling means; d. means utilizing said clock pulses for generating control signals; and e. means for applying said control signals to said storage means and said first and second address generating means.

15. Apparatus for converting a signal represented in accordance with a first mathematical function into the same signal represented in accordance with a second mathematical function, said apparatus comprising: a. means for periodically sampling a varying input signal; b. an information storage means having a plurality of addressable storage locations; c. means for generating in a first sequence which represents a third mathematical function a first set of addresses of said locations; d. means for writing representations of the values of the samples of said input signal into the storage means locations of said first set of addresses; e. means for generating a second set of addresses for said locations in a linear sequence; f. means for reading said stored representations of said samples from said storage means in accordance with said second sequence of addresses; and g. means for constructing a smooth output signal from the samples read from said storage means.

16. The apparatus defined in claim 15 wherein said means for generating the first set of addresses comprises: a. a first counter; b. means for stepping said first counter for each sample of said input signal; c. means for generating a third mathematical function signal which follows the difference between said first and second mathematical functions; and d. means for combining the contents of said first counter with said third function signal to produce said first set of addresses.

17. The apparatus defined in claim 16 wherein said means for stepping said first counter comprises: a. means for synchronizing the operation of said apparatus, said synchronizing means including b. means for generating timing signals; c. means for applying timing signals from said generating means to said sampling means to control the time of sampling said input signal; and d. means for applying timing signals from said generating means to said first counter to cause said first counter to step.

18. The apparatus defined in claim 16 wherein said means for generating said second set of addresses comprises a second counter, and means for stepping said second counter each time said input is sampled to produce said second set of addresses.

19. The apparatus defined in claim 18 further including: a. means for synchronizing the operation of said apparatus, said synchronizing means including b. means for generating timing signals; c. means for applying timing signals from said generating means to said sampling means to control the time of sampling said input signal; and d. means for applying timing signals from said generating means individually to said first and second counters to cause them to step in synchronism with said sampling and with each other.

20. The apparatus defined in claim 18, wherein said means for stepping said second counter comprises: a. means for synchronizing the operation of said apparatus, said synchronizing means including b. means for generating timing signals; c. means for applying timing signals from said generating means to said sampling means to control the time of sampling said input signal; and d. means for applying timing signals from said generating means to said second counter to cause said second counter to step.

21. The apparatus defined in claim 15 wherein said means for sampling includes means for converting said samples of said input signal from a varying amplitude form into an equivalent digital form.

22. The apparatus defined in claim 21 wherein said means for converting said samples of said input signal includes means for producing several signals having amplitudes representative of the amplitudes of said samples with respect to fixed values, and means for generating digital values of said several signals with the resolution varying from signal to signal.

23. The apparatus defined in claim 15 wherein said means for constructing an output signal includes means for converting the information read from said storage means in digital form into an equivalent signal in varying amplitude form.

24. The apparatus defined in claim 15 wherein said means for generating said second set of addresses comprises a second counter, and means for stepping said second counter each time said input signal is sampled to produce said second set of addresses.

25. The apparatus defined in claim 15 wherein said information storage means comprises a random access memory.

26. A system for converting a first video signal which varies in accordance with radar ground range into a second video signal which varies in accordance with radar slant range, said system comprising: a. an analog-to-digital converter for periodically sampling said first video signal, and for converting said first video signal into digital numbers; b. a random access memory having a data input coupled to the output of said converter and disposed for storing said digital numbers; c. means for generating a first digital number representative of the instantaneous differences between a first signal proportional to radar ground range and a second signal proportional to radar slant range; d. first means for producing a second number uniformly increasing in value; e. means for combining said first number with said second number; f. means coupling the output of said combining means to the address input of said memory during a first time interval, wherein said combined first and second numbers are utilized for addressing the memory for storing said digital numbers in said memory; g. second means for producing a third number uniformly increasing in value; h. means coupling the output of said second producing means to the address input of said memory during a second time interval, wherein said third number is utilized for addressing said memory for retrieving said digital numbers from said memory; and i. a digital-to-analog converter for converting the digital numbers retrieved from said memory into an analog form, wherein said analog form is said second video signal which varies in accordance with said second mathematical function.