US3873929A - Clock synchronization system - Google Patents

Clock synchronization system Download PDF

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US3873929A
US3873929A US077356A US7735670A US3873929A US 3873929 A US3873929 A US 3873929A US 077356 A US077356 A US 077356A US 7735670 A US7735670 A US 7735670A US 3873929 A US3873929 A US 3873929A
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fed
integrator
zero crossing
output
clock
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US077356A
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Robert R Willmore
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US Air Force
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US Air Force
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04K—SECRET COMMUNICATION; JAMMING OF COMMUNICATION
    • H04K3/00—Jamming of communication; Counter-measures
    • H04K3/40—Jamming having variable characteristics
    • H04K3/45—Jamming having variable characteristics characterized by including monitoring of the target or target signal, e.g. in reactive jammers or follower jammers for example by means of an alternation of jamming phases and monitoring phases, called "look-through mode"
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/12—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a scanning signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04K—SECRET COMMUNICATION; JAMMING OF COMMUNICATION
    • H04K3/00—Jamming of communication; Counter-measures
    • H04K3/80—Jamming or countermeasure characterized by its function
    • H04K3/82—Jamming or countermeasure characterized by its function related to preventing surveillance, interception or detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • This invention relates to detection systems, and more particularly to an apparatus for determining the frequency of a clock oscillator driving a shift register generator.
  • noise-like signals with predictable correlation functions has produced a new family of highly secure communication systems. These systems generally obtain their noise-like, pseudo-random modulating signal from a linear shift register generator being driven by a clock oscillator. A hostile eavesdropping receiver must first determine the clock frequency from the received code sequence before signal identification can be made or a suitable jamming signal prepared.
  • the invention takes advantage of the fact that the code signal generated by the shift register generator can only change state (zero crossing) when a clock pulse occurs. Thus, by detecting the zero crossing of the input code it is possible to generate the synchroniz ing signal for an oscillator located near the clock frequency.
  • the clock synchronization units used in the past have several limitations which limited the usefulness in ferret and jamming applications.
  • One limitation is the limited frequency locking range caused in part by the fixed output pulsewidth from the zero crossing detector. For very large frequency ranges, the fixed output pulsewidth reduces the amount of phase error that can be used without losing lock.
  • Another limitation for some applications is the variation in the steady state phase error across the frequency band. Since lock break occurs only at to l80, the amount of phase jitter that causes a lock break varies across the band and is a maximum only at the center of the locking range.
  • phase sensitive zero crossing detector simplifies the loop by eliminating the need for an extra phase detector or a second zero crossing detector. It also increases the usable region of phase error which is important when the desired frequency locking range is large.
  • the sweep control difference integrator in addition to increasing the frequency locking range maintains a nearly constant steady state phase error regard less of the center frequency.
  • the amount of input phase jitter that can be tolerated without the loop losing lock is increased by the phase sensitive zero crossing detector because of the increased usable phase error.
  • the sweep integrator can also increase the allowable phase jitter by maintaining a constant steady state phase error in the center of the usable phase region (90).
  • FIG. 5b shows associated waveforms used for explanation of FIG. 5a.
  • FIGS. 6a and 6b are circuit diagrams of that shown in FIG. 2.
  • a prior art clock synchronization unit as shown in the block diagram of FIG. 1 takes advantage of the fact that code signals generated by a shift register generator only change state when a clock pulse occurs.
  • the signal is fed to zero crossing detector 15 and its output fed to phase detector 17 together with the output of zero crossing detector 15, the output of phase detector 17 being fed to in tegrator 19.
  • a standard phase loop incorporating a low pass filter is not used because of the pulse dropouts and the related very low frequencies contained in the spectrum of a pseudo-random sequence. Box car 21 holds the last-known charges between pulses thus eliminating the effect of pulse dropouts making the unit nearly independent of the received number of zero crossing per second.
  • Phase sensitive zero crossing detector 23 is capable of producing pulses at each zero'crossing with a width that can vary from 0 to I"; the output of detector 23 is fed to box car 29.
  • Sweep control difference integrator 25 fed by sweep control 27 and box car circuit 29 expands the frequency locking range and reduces the steady state phase variations with frequency.
  • Voltage control integrator 31 is also used to optimize the simple RC integrators time constant with changes in the loops center frequency.
  • the output of the difference integrator 25 and box car 29 is summed in summing circuit 33 through loop filter 34 and fed to multivibrator 35.
  • FIGS. 3a and 3b An expanded block diagram of the phase sensitive zero crossing detector and some associated typical waveforms are shown in FIGS. 3a and 3b.
  • the circuit incorporates NAND gates 36-38, inverter 39, and flipflop 40.
  • the typical waveforms illustrate the output pulses that would be observed if the loops voltage controlled multivibrator clock 35 was synchronized with the clock source used to generate the received code sequence.
  • the output pulsewidth wouldbe decreased by an amount proportional to the phase difference. Should the two clock sources be located at different frequencies then the output pulsewidth varies in accordance with the difference between the two clock frequencies. Since the zero crossing detector employs a square-wave clock source rather than a fixed pulsewidth source, only one zero crossing detector is requiredin the loop.
  • the phase sensitive zero crossing detector of FIG. 3a serves two functions. First, it generates an output pulse at each zero crossing of the input code sequence. Secondly, itserves as a phase detector in that the pulsewidth of the generated zero crossing pulses is proportional to the phase difference between the system clock source and that used to generate the code sequence.
  • the waveforms shown in FIG. 3b are for the case when the system clock has achieved perfect synchronization with the frequency of the shift register generator; clock source.
  • the zero-crossings (waveforr Z) of the input code sequence (waveform A) are show to have a pulsewidth equal to that of clock sou c (waveforms B and E).
  • Waveforms B and E With respect to the code sequence the pulsewidth th 7 zero crossings (waveform Z) will decrease. If the phase drifting is continuous then a frequency difference exists between the two clock sources. A frequency difference will cause the zero crossing pulsewidths to decrease and then increase at a rate proportional to the difference between the two source frequencies.
  • Waveform A represents the input code sequence.
  • Waveform B is the system clock source which would be identical.
  • FIGS. 4a and 4b An expanded block diagram showing the voltage controlled integrator box car filter and associated waveforms are shown in FIGS. 4a and 4b.
  • Two saturated NAND gates 41 and 42 are used to provide the proper amount of pulse delay to insure discharge of the box car before the arrival of the succeeding integrated pulse.
  • FIGS. 5a and 512 The expanded block diagram of the sweep control circuitry and the associated waveforms are shown in FIGS. 5a and 512.
  • the voltage being sent to the integrator changes from 13+ to a selected voltage, e,. If a signal e, is not present the integrator remains negatively saturated. If a signal is present, the output from the boxcar e before synchronization, will exceed the threshold voltage e, and the integrator will begin to integrate toward positive saturation.
  • the loops voltage controlled multi ⁇ 'i brator will lock itself to the clock used to generate the received code.
  • the steady state phase error will adjust itself to the value required to make e equal to e,. At this point the loop is completely locked and the integrator stops integrating and holds the voltage required to maintain the voltage controlled multivibrator at the proper center frequency.
  • the loop in the locked mode, can follow clock variations as wide and as fast as the loop's bandwidth regardless of the clocks center frequency.
  • the difference integrator providesthe loop with a drift frequency tracking range limited only by the voltage controlled multivibrator and power supply voltage.
  • FIGS. 6a and 6b are circuit diagrams.
  • Transistors designated as 51 can be type 2N250l and those designated as 53 can be type 2N9l8.
  • Diodes designated as 55 can be type lN9l4 and those designated as 57 can be type What is claimed is:
  • An apparatus for synchronizing a pseudorandom code comprising:
  • An apparatus for synchronizing a pseudorandom code according to claim 1 wherein the output of said multivibrator is a square wave clock signal.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A synchronizing apparatus having a phase sensitive zero crossing detector fed to a voltage controlled integrator and a box car circuit that is also fed by the voltage controlled integrator. The output of a sweep controlled difference integrator fed by the box car circuit is summed with the box car circuit output and fed the voltage controlled integrator and a voltage controlled multivibrator, the output thereof being fed to the zero crossing detector.

Description

United States Patent OUTPUT Willmore Mar. 25, 1975 -[54] CLOCK SYNCHRONIZATION SYSTEM 3,567,959 3/1971 Kaneko et al.... 328/63 [75] Inventor: Robert R- il more, e e 3,602,834 8/1971 McAuliffe v 307/269 Primary Examiner-Malcolm F. Hubler [73] Assignee: The United States of America as Attorney, Agent, or FirmHarry A. Herbert, Jr.;
represented by the Secretary of the Julian L. Siegel Air Force, Washington, DC. 22 Filed: Oct. 1, 1970 L h Q T h sync ronizmg apparatus avmg a p ase sensitive [21] Appl' 77356 zero crossing detector fed to a voltage controlled integrator and a box car circuit that is also fed by the volt- [52] US. Cl. 328/63, 307/269 g controlled integratcr- The pu of a Sweep [51] Int. Cl. H03k 1/16, H03k 5/13 trolled iff r n ntegrator f d by the box car circuit [58] Field of Search 328/63, 72; 307/269 is summed wi h h ox car circuit output and fed the voltage controlled integrator and a voltage controlled |5 References Cit d multivibrator, the output thereof being fed to the zero UNITED STATES PATENTS 055mg detector- 3.544,907 12/1970 Bleickardt 328/72 2 Claims, 10 Drawing Figures f 2 4 0 609-5 Jiffy i754 x :WEEP ZZ-Wa was: azmm TA/Fir zira zrax l J'WEJP roan/9w 4 dd? I]! 72 3 /5' 2%?3 if; a e
CLOCK SYNCHRONIZATION SYSTEM BACKGROUND OF THE INVENTION This invention relates to detection systems, and more particularly to an apparatus for determining the frequency of a clock oscillator driving a shift register generator.
The use of noise-like signals with predictable correlation functions has produced a new family of highly secure communication systems. These systems generally obtain their noise-like, pseudo-random modulating signal from a linear shift register generator being driven by a clock oscillator. A hostile eavesdropping receiver must first determine the clock frequency from the received code sequence before signal identification can be made or a suitable jamming signal prepared.
The invention takes advantage of the fact that the code signal generated by the shift register generator can only change state (zero crossing) when a clock pulse occurs. Thus, by detecting the zero crossing of the input code it is possible to generate the synchroniz ing signal for an oscillator located near the clock frequency.
The clock synchronization units used in the past have several limitations which limited the usefulness in ferret and jamming applications. One limitation is the limited frequency locking range caused in part by the fixed output pulsewidth from the zero crossing detector. For very large frequency ranges, the fixed output pulsewidth reduces the amount of phase error that can be used without losing lock. Another limitation for some applications is the variation in the steady state phase error across the frequency band. Since lock break occurs only at to l80, the amount of phase jitter that causes a lock break varies across the band and is a maximum only at the center of the locking range.
SUMMARY OF THE INVENTION The invention incorporates a phase sensitive zero crossing detector capable of producing a pulse at each zero crossing with a width that can vary from 0 to 180 and a sweep control difference integrator that expands the,frequency locking range and reduces the steady state phase variation with frequency.
The use of the phase sensitive zero crossing detector simplifies the loop by eliminating the need for an extra phase detector or a second zero crossing detector. It also increases the usable region of phase error which is important when the desired frequency locking range is large. The sweep control difference integrator in addition to increasing the frequency locking range maintains a nearly constant steady state phase error regard less of the center frequency.
The amount of input phase jitter that can be tolerated without the loop losing lock is increased by the phase sensitive zero crossing detector because of the increased usable phase error. The sweep integrator can also increase the allowable phase jitter by maintaining a constant steady state phase error in the center of the usable phase region (90).
It is therefore an object of the invention to provide an improved clock synchronization system.
It is another object to provide a clock synchronization system having an extended frequency locking range.
It is still another object to provide a clock synchronization system that eliminates the variation in steady state phase error.
It is still another object to provide a clock synchronization system that uses a phase sensitive zero crossing detector having a square wave clock source rather than a fixed pulsewidth source thereby requiring only one zero crossing detectorin the loop.
These and other advantages, features and objects of the invention will become more apparent from the following description taken in connection with the illustrative embodiment in the accompanying drawings.
DESCRIPTION OF THE DRAWINGS control circuit shown in FIG. 2;
FIG. 5b shows associated waveforms used for explanation of FIG. 5a; and
FIGS. 6a and 6b are circuit diagrams of that shown in FIG. 2.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A prior art clock synchronization unit as shown in the block diagram of FIG. 1 takes advantage of the fact that code signals generated by a shift register generator only change state when a clock pulse occurs. Thus, by detecting the zero crossing of the input code with detector 11 it is possible to generate a synchronizing signal for oscillator or square wave generator 13 located near the clock frequency. The signal is fed to zero crossing detector 15 and its output fed to phase detector 17 together with the output of zero crossing detector 15, the output of phase detector 17 being fed to in tegrator 19. A standard phase loop incorporating a low pass filter is not used because of the pulse dropouts and the related very low frequencies contained in the spectrum of a pseudo-random sequence. Box car 21 holds the last-known charges between pulses thus eliminating the effect of pulse dropouts making the unit nearly independent of the received number of zero crossing per second.
The block diagram of the improved clock synchronization unit as shown in FIG. 2 incorporates two major improvements. Phase sensitive zero crossing detector 23 is capable of producing pulses at each zero'crossing with a width that can vary from 0 to I"; the output of detector 23 is fed to box car 29. Sweep control difference integrator 25 fed by sweep control 27 and box car circuit 29 expands the frequency locking range and reduces the steady state phase variations with frequency. Voltage control integrator 31 is also used to optimize the simple RC integrators time constant with changes in the loops center frequency. The output of the difference integrator 25 and box car 29 is summed in summing circuit 33 through loop filter 34 and fed to multivibrator 35.
An expanded block diagram of the phase sensitive zero crossing detector and some associated typical waveforms are shown in FIGS. 3a and 3b. The circuit incorporates NAND gates 36-38, inverter 39, and flipflop 40. The typical waveforms illustrate the output pulses that would be observed if the loops voltage controlled multivibrator clock 35 was synchronized with the clock source used to generate the received code sequence. When the two clock sources are synchronized in frequency but out of phase, the output pulsewidth wouldbe decreased by an amount proportional to the phase difference. Should the two clock sources be located at different frequencies then the output pulsewidth varies in accordance with the difference between the two clock frequencies. Since the zero crossing detector employs a square-wave clock source rather than a fixed pulsewidth source, only one zero crossing detector is requiredin the loop.
The phase sensitive zero crossing detector of FIG. 3a serves two functions. First, it generates an output pulse at each zero crossing of the input code sequence. Secondly, itserves as a phase detector in that the pulsewidth of the generated zero crossing pulses is proportional to the phase difference between the system clock source and that used to generate the code sequence. The waveforms shown in FIG. 3b are for the case when the system clock has achieved perfect synchronization with the frequency of the shift register generator; clock source. As a result the zero-crossings (waveforr Z) of the input code sequence (waveform A) are show to have a pulsewidth equal to that of clock sou c (waveforms B and E). Should the system clock source (waveforms B and E) begin drifting in time or p ay: with respect to the code sequence the pulsewidth th 7 zero crossings (waveform Z) will decrease. If the phase drifting is continuous then a frequency difference exists between the two clock sources. A frequency difference will cause the zero crossing pulsewidths to decrease and then increase at a rate proportional to the difference between the two source frequencies. Waveform A represents the input code sequence. Waveform B is the system clock source which would be identical.
An expanded block diagram showing the voltage controlled integrator box car filter and associated waveforms are shown in FIGS. 4a and 4b. Two saturated NAND gates 41 and 42 are used to provide the proper amount of pulse delay to insure discharge of the box car before the arrival of the succeeding integrated pulse.
The expanded block diagram of the sweep control circuitry and the associated waveforms are shown in FIGS. 5a and 512. When a command is sent to the sweep control inputs, the voltage being sent to the integrator changes from 13+ to a selected voltage, e,. If a signal e, is not present the integrator remains negatively saturated. If a signal is present, the output from the boxcar e before synchronization, will exceed the threshold voltage e, and the integrator will begin to integrate toward positive saturation. When the difference between the clock frequencies falls within the loops bandwidth (locking range), the loops voltage controlled multi\'i brator will lock itself to the clock used to generate the received code. The steady state phase error will adjust itself to the value required to make e equal to e,. At this point the loop is completely locked and the integrator stops integrating and holds the voltage required to maintain the voltage controlled multivibrator at the proper center frequency.
The loop, in the locked mode, can follow clock variations as wide and as fast as the loop's bandwidth regardless of the clocks center frequency. The difference integrator providesthe loop with a drift frequency tracking range limited only by the voltage controlled multivibrator and power supply voltage.
FIGS. 6a and 6b are circuit diagrams. Transistors designated as 51 can be type 2N250l and those designated as 53 can be type 2N9l8. Diodes designated as 55 can be type lN9l4 and those designated as 57 can be type What is claimed is:
1. An apparatus for synchronizing a pseudorandom code comprising:
. a. phase sensitive zero crossing detection means fed by the code;
b. a voltage control integrator fed by the zero crossing detecting means;
c. a box car circuit fed by the integrator and zero crossing detecting means;
(1. a sweep control means;
e. a difference integrator fed by the sweep control means and the box car circuit;
f. a summing circuit fed by the difference integrator and the box car circuit an output of the summing circuit being fed to the voltagecontrol integrator;
and
g. a voltage control multivibrator fed by the summing circuit with the output of the multivibrator fed to the zero crossing detector.
2. An apparatus for synchronizing a pseudorandom code according to claim 1 wherein the output of said multivibrator is a square wave clock signal.

Claims (2)

1. An apparatus for synchronizing a pseudo-random code comprising: a. phase sensitive zero crossing detection means fed by the code; b. a voltage control integrator fed by the zero crossing detecting means; c. a box car circuit fed by the integrator and zero crossing detecting means; d. a sweep control means; e. a difference integrator fed by the sweep control means and the box car circuit; f. a summing circuit fed by the difference integrator and the box car circuit an output of the summing circuit being fed to the voltage control integrator; and g. a voltage control multivibrator fed by the summing circuit with the output of the multivibrator fed to the zero crossing detector.
2. An apparatus for synchronizing a pseudorandom code according to claim 1 wherein the output of said multivibrator is a square wave clock signal.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025743A (en) * 1996-06-04 2000-02-15 Pioneer Electronic Corporation PLL circuit having forcible pull-in function

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3544907A (en) * 1966-06-08 1970-12-01 Hasler Ag Apparatus for generating synchronised timing pulses in a receiver of binary data signals
US3567959A (en) * 1966-10-20 1971-03-02 Nippon Electric Co Phase-locked pulse generator with frequency maintaining function
US3602834A (en) * 1970-06-18 1971-08-31 Ibm Timing recovery circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3544907A (en) * 1966-06-08 1970-12-01 Hasler Ag Apparatus for generating synchronised timing pulses in a receiver of binary data signals
US3567959A (en) * 1966-10-20 1971-03-02 Nippon Electric Co Phase-locked pulse generator with frequency maintaining function
US3602834A (en) * 1970-06-18 1971-08-31 Ibm Timing recovery circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025743A (en) * 1996-06-04 2000-02-15 Pioneer Electronic Corporation PLL circuit having forcible pull-in function

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