US3859543A - Sequencing timers - Google Patents

Abstract

A sequencing timer for providing independently adjustable time intervals of same or different durations starting at the same time or at the end of the preceding interval as applicable. Clock frequency, produced in a clock oscillator, is used to synchronise the incremental charging of one or more capacitors each being part of an adjustable RC timer. Using a relay with multiple, mutually isolated, contacts operated at given clock frequency both high insulation of the timing capacitor and its incremental charging are achieved. As result, stable short or long time intervals are obtained on relatively wide ambient temperature range. Independent intervals can range from seconds to hours.

Description

United States Patent 1191 1111 3,859,543 Milovancevic Jan. 7, 1975 SEQUENCING TIMERS 3,660,691 5/1972 Glawleschkoffet al. 307/293 [76] Inventor: Slavko Milovaneevic, PO. Box 402, OTHER PUBLICATIONS Torrance Cahf- 90508 FET Keeps Long Staircase Steps Flat by Bray in 22 Filed; Man 2 73 Electronics, March 18, 1968, page 94. [21] Appl' 323,774 Primary ExaminerStanley D. Miller, Jr.

[52] US. Cl. 307/293, 307/252 F, 328/130, [57] ABSTRACT 328/131 317/141 S A sequencing timer for providing independently ad- Cl "H03k 17/28,}103k17/301 justable time intervals of same or different durations A" H0314 17/72 starting at the same time or at the end of the preced- Field of Search 307/227, 228, 293, 252 F; ing interval as applicable. Clock frequency, produced 8/ 317/14l S in a clock oscillator, is used to synchronise the incremental charging of one or more capacitors each being [56] References Cited part of an adjustable RC timer. Using a relay with UNITED STATES PATENTS multiple, mutually isolated, contacts operated at given 3 019,393 1/1962 Rockafellow 328/130 eleek frequency both high insulation of the timing 3:15s,757 11/1964 Rywak 307/227 Paeiter and its incremental eharging are achieved- AS 3,162,772 12/1964 307/293 result, stable short or long time intervals are obtained 3,378,698 4/1968 307/2 on relatively wide ambient temperature range. Inde- 3,5 5 5/1968 328/12 pendent intervals can range from seconds to hours. 3,456,554 7/1969 Goodwin 307/227 3,555,305 1/1971 Luczkowski 307/228 8 Claims, 9 Drawing Figures 3,538,924 /1971 Linde ll 307/293 Patented Jan. 7, 1975 2 Sheets-Sheet 1 Ad ust. Adjust. Aofilst- ,4 jusz, Clock im imer Timer Frag, 1 1 7;

v Z 2 Tn Fig.

Adju t 140721515 Clock Freq. lmer 1 Fig. 3 '9' 4 4 4 H J. /0 r- """"1 E 45 ll $20 +37 36+)? H as 45 26 i l I I 23 n I I 4 Av- -24 max 39'\- 1 J46 "*1 I ll T32? I i 1 SEQUENCING TIMER BACKGROUND OF TH EiINX/ENTION' I I I This invention relates to timing devices in general, "i particularly to sequenced'timing performed el'ectroni cally and specifically to sequenced timing with independentlyadjustable delays in wide limits. And as a j '1 special case'when timer has one single sequence it is TABIsEI l. The subject sequencing timers have long time delays for example on the order of at least 1 hour;

2. They are also sequencing, that is,'adapted to'gen erate a plurality of successive time-indicating signals;

3. It is also adapted for stable operation in the face I of relatively widely varying ambient temperatures, such as approx. -30 to 70 C;

called simply timer in this case increment timer. 1 See the following Table I containing some distinctive features and advantages.

4. It is also adapted to be implemented with off-theshelf components such as resistors, capacitors, semiconductors, relays, etc., that are widely available at retailer, rather than being specially fabricated or exhibiting excess values;

5. It is relatively small and compact as opposed to electro-mechanical devices for same purpose;

6. It is relatively non-mechanical, having no motor, I

cams, springs, etc. as in the prior art, can besealed, needs no maintenance;

FIG. 8 isan -FIG. 7.

l FIG. 2 is a representation of timing intervals per FIG.

FIGLB is a block diagr am of a sequence timer with {successivetiniing intervals or series mode of operation.

FIG. 4 is a representation of time intervals per FIG. 3.

FIG.5 is an example of a preferred embodiment per FIG. 1.

FIG. 6 is an example of a preferred embodiment per FIGQ3.

FIG. 7 is a generalized block diagram of the sequencing timer. 1 I

example of a preferred embodiment per FIG. 9'is'timing'diagram of the timer per FIG. 8.

l DESCRIPTION OF OPERATION Referring to FIG. 1, an adjustable clock frequency "source designated 1 produces periodic adjustable freto a reasonably high number like 10 or as necessary.

7. It operates with a relatively low power consumption, e.g. on the order of 0.1 watt or less as opposed to several watts for electro-mechanical devices;

8. It is economical since it cost less than cam timers; etc. 1 Mechanical and electro-mechanical devices are well known in the art for example cam timersspring oper- -When n takes value I, timer of FIG. l becomec an in- 'crementftimer, when n 2 'or more a true sequence timer results. All adjustable timers, in this case, are I being pulsed by adjustable clock frequency source at ated timers, etc. Electronic timers, even with a single interval, do not exceed 5 or 10 minutes except in special cases. As example, see the description of an electronic sequencer in Motorola's Semiconductor Power Circuits Handbook, page 6-27, FIG. 6-23, l First Edition, November 1968.

Therefore, one objective of the invention is to pro-- vide long time intervals (in order of an hour and longer) for' a wide ambient temperature range and using regular semiconductor and other electronic components such as those available from retailers shelves; Itis also an objective of this invention to provide long time intervals by use of not more than 1 micro farad capacitors, and not more than 10 Megoh ms resistors as variable timing means. 7

Mechanical and electromechanical systems of sequencing long time delays, though reliable and acc'urate, are bulky, require relatively high amount of power for operation, require maintenance and are subject to,

corrosion in some instances.

' spe ctive ltimehintervals T ;T

the same time, from the very beginning, thus starting their respectiveitiming intervals at the same time which is then called parallel mode of operation. FIG. 2

represents graphically respective time intervals T ,T ...T,, each being indicated by the length of an appropriate arrow,. and-vividly suggests the name parallel mode of operation."

Referring nowto FIG. 3 we find again an adjustable clock frequency source designated 5 in this case, and adjustable timersdesignat'ed' 6,7 and 8 with their re- T,,'. In this arrangement timer 6 is being pulsed first. At the end of its timing interval T' ";it fires and initiates operation of timer 1 7, which';simila'rly initiates operation of the succeding timer etc. This process continues on and on until (n 1) st timer initiates the operation of the last adjustable timer in thechain -timer n which tires at the end of its timing interval T thus completing the sequence. Sys- It is, therefore, a further objectiveof this invention to if provide reliable, relatively accurate, small in size de-- vice which would not require much electric power for operation, any maintenance and be corrosion resistive.

It is also an objective of this invention to provide an economical long delay timer.

BRIEF DESCRIPTION or DRAWINGS FIG. 1 is a block diagram of a sequence timer with common starting time or parallel mode of operation.

embodiment of FIG. 1 without square 3 for sake of tem can be now'reset'manually or automatically by depriving'all of themofe'lecti'ic power for a short period of time. Thistype 1of operation readily suggests the name series Inode'of operation" which is even more pronounced in FIG-.' 4 where the length of arrow represents the length of the respective timing interval, while its position on'time axis represents its sequencing position timewise. r r I Referring to FIG. 5 is represents an example of the space savings. In addition note a d-c power source designated 9-and power switch designated 10. Square 1 represents adjustable clock frequency source based on a relatively new voltage sensing and triggerring device called Programmable Unijunction Transistor (PUT). For detailed information on PUTs please see General Electrics Application Note 6020- and also: Semiconductor Data Handbook, FirstEdition, 197 1, pages 702 707fSince PUT operates in same way as well known Unijunction Transistor (UJT) and information on its operation is readily available it will not be given here for the sake of brevity.

Before we proceed let us note the similarity-between FIGS. 5 and 8. This is obvious since FIG. 8 is special caseof FIG. 5 when n l, .i.e., number of sequences is 1. Accordingly, circuit elements in FIG. 8 are designated with same numbers and double primed for sake of distinction. An additional difference between these figures is the lack of contacts 27 in FIG. 8 since they are not needed. Consequently, FIG. 9 is applicable to both figures and explanation of operation of one figure will suffice. Since blocks designated 55,56 and 57 in FIG. 8 are identical to block 1 of FIG. 5 (except for contacts 27) and FIG. 8 is a special case of FIG. 5 it is also a special case of FIG. 1. Comparing FIG. 7 to FIGS. 1 and 3 one will notice difference in rearrangement of squares.- Block designated Capacitor Storage Means inFIG. 7 is same as Adjustable Timer blocks in FIGS. 1 and 3. Thus FIG. 7 is a more generalized diagram of an increment type sequence timer. Consider now FIG. 8 in connection with FIG. 7. FIG. 7 is a functional blockdiagram consisting of 3 basic elements: clock meams', isolation means and storage capacitor means. Clock means consists of adjustable clock means and a pulse stretcher designated respectively 55 and 56. Pulse stretcher 56 is used to enable isolation switch means 57 to respondproperly and operate timing elements 58 as adjustable clock means 55 dictates. Output from timing elements 58 is fed to sensing and trigger means 59. Corresponding squares in FIG. 8 are designated with same numbers as blocks in FIG. 7 allowing us to see that adjustable clock means SS'is an adjustable in frequency, temperature compensated PUT oscillator, pulse stretcher 56 stores charge from capacitor 13' in its capacitor 18" discharging it slowly through resistor 23 and transistor 24 causing relay contacts 26" to remain closed for much longer, period than the duration of pulse from 55 is and enabling operation of relay 25" by extremely short pulses. Block 57 is, then, a relay with set of contacts in this case. Timing elements are resistors 28", 29" and. capacitor 30" all located in block 58. Finally, block 59 consists of a temperature compensated. PUT circuit as used in sensing and-trigger applications like in timers, oscillators and has its counterpart in'block 55. Refer now to FIGS. 8 and 9. Adjustable clock means 55 delivers a pulse once per interval T (designated 60 in FIG. 9-). At the nearly same time contacts26" are closed allowing capacitor 30' to be charged for a small increment as indicated in 61 (FIG. 9) at the end offirst period T (in-terval T named above). This' isrepeated again and again until voltage across capacitor 30" is high enough to trigger PUT 32" allowing discharge of capacitor 30"through PUT 32-' and resistor 31"aftera time delay T, as indicated in 62 .(FIG. 9) when an output pulse will appear on terminal 33". p

Back to FIG. 5, the interconnection of elements in block 1 is as follows: Negative terminal of the d-c power source designated 9 is connected to a common lead designated 52, while positive terminal is connected to one side of power switch 10, whose other end is connected to the supply lead designated 53. Timing elements consisting of a series connection of a timing I 4 capacitor designated 13, a fixed resistor designated 12 and a variable resistor designated 11 are connected respectively between said common and said supply lead 53. Interconnection of capacitor 13 and resistor 12 is connected to anode electrode of a PUT designated 15 and having its cathode electrode connected to said common lead through a resistor designated 14. A resistor designated 17 is connected between common lead and the gaterelectrodev of PUT 15, their interconnection being connected to the cathode electrode of temperature effects compensating diode designated 20, while its'anode electrode is connected to the interconnection of reference voltage resistors designated 19 and 21 and connected, respectively, with remaining ends to common and the. supply leads. When voltage across capacitor 13 reaches potential slightly higher than reference potential across resistor 17, PUT l5 abruptly decreases resistance between its anode and cathode electrodes allowing capacitor 13 to discharge as fast as elements connected to cathode permit. Discharge current forms a positive goingpulse across resistor 14 approximately triangular in shape and of a typical duration 5 l0 microseconds. Said dischargecurrent is fed through diode designated 16 since its anode is connected to PUTs cathodeand resistor 14. Diode 16 has its cathode connected to resistor designated 23, while capacitor designated 18 is connected to said interconnection and with remaining plate to common terminal (lead) 52. Capacitor 18 stores the received charge from capacitor 13. Said resistor 23 has its remaining end connected to the base electrode of an NPN type transistor designated 24 having its emitter electrode connected to common terminal (lead) 52 and its collecter electrode to interconnection of a relay coil designated 25 and anode of a kick-back voltage protective diode designated 22 whose cathode and the remaining end of relay coil 25 are connected to lead 53. Charged capacitor 18 supplies the base current for transistor 24 for some 5 msec. Diode 16 becomes reverse biased'as soon as voltage across it reaches reference potential less a junction voltagedrop (about 0.6 to 0.8 Volt), thus, prevents capacitor 18 discharge through resistor 14. Transistor 24 is driven into saturation causing relay contacts 26 and 27 to change positions from those in the drawing to opposite ones and remain there for few msecs. Oscillator pulse of some 5 microseconds duration has been stretched to msecs.

Period of oscillation must be, therefore, longer than duration of .the stretched pulse (5 msec in this case) in order to permit relay contacts to. stay also open and allow incremental charging of capacitor 30 in block 2 and capacitor 40in 4. I

Note now that value of capacitor 13 need not be larger than 1 microfarad sinceperiod of oscillation up to 1 sec. can-be covered with a resistor being adjustable semiconductors (l6 and 24). Temperature effects on PUT 15 arecompensated by diode 20. This way adjustable clock frequency oscillator will be stable in wide temperature limits, since PUTs have low leakage between'gateand anode electrodes.

. i Let iifs'iconsider n w of the timeopen and capacitor 30:can be charged in wquency period, then it is, clear that the timedelay of the block 2 will be hundreds of times longer'and even thouple o'nlyg'contacts' 26'p'er'rnane'ntly'clQsedLblock' Z is then identieal toioscill'ator-in' block 1 and itsoperation needs no long explanations. -l ts ,tirnedelay with same values-asirf-lfloek 1 would becertainly. identical (up to 1 sec. .asanticipated). However; contacts 26 are most small incrementsonly as'clo'ck frequency from block 1 dictates. Assuming perfect isolation of capacitorf30, while contacts are fop'en, and thatportion of time contacts are closedisonly a fraction' of the clock fresands of times l'onger than clock frequency'period re-- sulting in delays of over 1 hour, Regarding temperature influence same holds for, block ,2; as for oscillator in block 1, and in additioh, during thetime contacts 26 are open insulation resistance is extremelyhigh and leakage current negligible bylall standards even. at highest operative temperatures. The only, leakage current to which timing capacitor is exposed is throughthe A. S. Fitz Gerald Pat. No. 2,l l0,0l5-(Cl,l77353)-,

D. F. Moore- Pat. No. 2,915,632 (Cl.250-27) C. W. Harrison Pat. No. 2,924,708 (Cl.'250-27.)

B. B. Nichols Pat. No. 3,105,158 Cl.30 788'. 5) j J. Rywak Pat. No. 3,158,757 (Cl.307.88'.5) 1 H. B. Kadah Pat. No. 3,378,698 (Cl.'307'225 A. F. Goodwin Pat. No.

3,456,554 (cres -13s) x Additional improvements on circuits given'in this-ap -iplication are: useof constant currentsource instead of resistors for timing purposes, use of additional sets of contacts to isolate storage capacitorfrom PUTTs while awaiting incoming charging period, use of a single" ref- 1 erence voltage source for all adjustable ,timers -a r,e .-j sulting in better circuit economy, pulsing of anodes or'i gates to decreasepeakpoint current etc. Referring now to FlG. 6 one will note that the clock frequency oscillator in block 5 is identical to that of j block 1 inFIG. 5. Blocks 6 and 8, however, differ partially as compared to blocks2 and 4 in FIG, 5, which: is necessary to assure serial operationQThis is achieved. by triggering f.e. Silicon Controlled Rectifier (SCR) designated 49 in block 6, FlG.6. Cathode electrode is connected to common lead 52', gate to cathode of PUT 1 32 and anode to a resistor designated 48 having other end connected to the supply lead 53'. To the interconnection anode resistor 48 a base current limitingresis tor is connected, being designated 50, and having remaining end connected to the base electrode of aPNP transistor designated 51, emitter being connected'to. supply lead 53', while collector to a leaddesignated 54 which will supply the successive timer'withthe d-c power needed for its operation. As PUT 32' tires at the end of its timing interval, T SCR 49 will be triggerred i I lock 2g which-5is'circuitwise. 7 identical to all remaining blocks. Assuming,iforfexam- 11 said PUTj'cathode electrode is con into conduction brijiiging ,th'e potential across its anode ;,-to about lIVoltabo ecommon'lead 53. The rest of the supply {voltage will W base-'e'mittfijdnctibn of transistor 51 causing it to enter e;irnpressed across-resistor 50 and saturation arid supply nearly full voltage from source 9 to the'adjustable. timer th'at followsblock 6. This process continues untillast sequence is performed by ad- 'justablejtimer, here designated, 8. v

lt is tobe noted that besides-usual delay adjustment foreaehsequenc'e a common adjustment by changing clock frequency is an advantage. Also the possibility to do adjustments of time delays by changing reference voltage andpulse stretching are options not to be disregarded. And possibilities do not end here as those skilled in the, art know yet the basis remains the same.

I claim:

,l. A sequencing timer having a plurality of sequences all starting at the same time and produces a pulse at the end of each sequence, consists of:

a d-c power source,'having a positive and a negative terminal, said negative terminal is connected to a common lead, said positive terminal is connected to the first terminal of a power switch, while the second terminal .of said power switch is connected to a supply lead, a clock frequencysource includes a timing resistor "connected between said supply lead and a first ter minal of a current limiting resistor whose second terminal is connectedto the first plate of. a storage capacitor having the secon nected to said common lead,

interconnection of said'current limiting resistor and '35.

1,;jsaid storage capacitor is connected to the anode A: "tor (PUT) whose cathode electrode is connected 'through'apulse forming resistor to said common lea d, I I gate electrode of said PUT is connected through abiasiing resistor tosaid common lead, said interconfne'ction of gate electrodeand, biasing resistor is connected also to the cathode electrode of l a compensating diode havinganode electrode con- .45

.nected to interconnection offtwo PUT reference voltage resistors connected betw and'said supply lead, v Y

nected to a pulse stretching circuit which includes ,anode' electro de ,of a blockingdiode whosecathode electrode is connected to the first plate of a capaci- Ltor, having the second plateconnected tosaid v common lead, a base resistor connected b etweenthe said; diode-capacitor interconnection. and a base. electrode-of; I t [an 4 n-p-fn transisto v I across said relaycoil having cathode electrode con i nectedto' thep 'coil operating multiple sets ofmutually isolated contacts, each set of contacts 'isutilized to pulseat least one sequencing circuit which includes a normally open contact connectedthrough a timi d plate con- I electrode of a'Programmable Unijunction Transis- 5 een said common 1'. having emitterfelectrode con r nected toisaid'common lead and the collector elec-.

Q trode connected through a relay coil to said supply lead, a transient" protection diode is connected ositive -end of said'coil, said relay a common contact being connected through a current limiting resistor to the interconnection of the firstplate of a storage capacitor, having second plate" connected to said common lead, and an anode electrode of a PUT, whose cathode electrode is connected to an output-terminaland to the first terminalof a cathode resistor, having second terminal connected to I said common lead, p I the gate electrode of said PUT is connected through a biasing resistor to said common lead and to the cathode electrode of a biasing diode, whose anode electrode is connected to the interconnection of the two PUT reference voltage resistors connected between said common and said supply lead.

2. Circuit as recited in claim 1 and having said timing resistor adjustable toprovide varying of the clock frequency thus, duration of allsequence intervals.

3. Circuit as recited in claim 1 and having said timing resistor adjustable, within said sequencing circuit, to provide independently adjustable intervals in each and every sequence.

4. Circuit as recited in claim 1 and having one single sequence by provision of a single set of contacts and a single sequencing circuit.

5. A sequencing timer having the plurality of sequences, the first sequence starting at the moment the power is supplied to the circuitry,'the second sequence starting at the end of the first sequence, the nth sequence starting at the end of n 1st sequence, a pulse is produced at the end of each sequence, said sequencing timer consisting of:

a d-c power source, having a positive and a negative terminal, said negative terminal is connected to a common lead, said positive terminal is connected to the first terminal of a power switch, while the second terminal of said power switch is connected to a supply lead,

a clock frequency source includes a timing resistor connected between said supply lead and a first terminal of a current limiting resistor whose second terminal is connected to the first plate of a storage capacitor having the second plate connected to said common lead,

interconnection of said current limiting resistor and said storage capacitor is connected to the anode electrode-of a Programmable Unijunction Transistor (PUT) whose cathode electrode is connected through a pulse forming resistor to said common lead, v v

gate electrode of said PUT is connected through a biasing resistor to said common lead, said interconnection of gate electrode and biasing resistor is connected also to the cathode electrode of a compensatingdiode having anode electrode connected to interconnection of two PUT reference voltage resistors connected between-said common and said supply lead, v 1

' said PUT cathode electrode is connected to. a pulse stretching circuit which includes anode electrode of a blocking diode whose cathode electrode is connected to the first plate of a capacitor, having the second plate connected to said common lead, a base resistor connected between the said diode-capacitor interconnection and a base electrodeof an n-p-n transistor having emitter electrode connected to said common lead and the collector electrode connected through a relay coil to said supply lead, a transient protection diode is connected across said relay coil having cathode electrode connected to the positive endof said coil, said relay coil operating "multiple setsof mutually isolated contacts, each set 1 of contacts is utilized to pulse at least onejsequencing circuit, the first set of contacts is utilized .to

pulse the first sequencing circuit which includes a normally open contact connected through a timing resistor to said supply lead,

, a common contact being connected through acurthe two PUT reference voltage resistors connected between said common and said supply lead, thefirst sequence output terminal is also connected to the gate electrode of the first Silicon Controlled Rectifier (SCR) having the cathode electrode connected to said common lead and anode electrode connected through a first anode resistor to said supply lead, said anode electrode is also connected through a first base resistor to the base electrode of a first p-n-p transistor whose emitter electrode is connected to said supply lead and, collector electrode connected to thenext sequencing circuit thus acts as the first supply lead,

a second setof contacts which consistsof a normally open contact and a common contact, these contacts being used to pulse a second sequencing circuit, which is of identical configuration as described first sequencing circuit, said second set of contacts operates associated circuit after the first sequencing time interval is over, said second se- "quence circuit being able to deliver a pulse at the end of said second sequence interval, and supply the power to the third sequencing circuit, an nth set of contacts which consists of a normally open contactand'a common contact, these contacts are used to pulse the nth sequencing circuit, n being an integer larger than two,

normally open contact is connected to the first termi nal of the nth timing resistor whose second terminal is connected to thecollector electrode of n 'l'st sequencing circuit, said collector electrode acting as the n-lst supply'lead,

the common contact is connected through the nth limiting resistor to t the first plate of an nth storage capacitor which ha the second plate connected-to said common lead, said first plate is also connected tothe anode electrode of the nth PUT having cathode electrode connected through the nth cathoderesistor to said common 6. The circuit of claim 5 and having said timing resistor adjustable to provide adjustable clock frequency which causes the change in duration of all sequences.

7. The circuit of claim 5 and having said first timing resistor adjustable, and said nth timing resistor adjustable to provide independently adjustable interval in each and every sequence.

8. The circuit of claim 5 having one single sequence 10 by provision of a single set of contacts and a single sequencing circuit.

Claims (8)

1. A sequencing timer having a plurality of sequences all starting at the same time and produces a pulse at the end of each sequence, consists of: a d-c power source, having a positive and a negative terminal, said negative terminal is connected to a common lead, said positive terminal is connected to the first terminal of a power switch, while the second terminal of said power switch is connected to a supply lead, a clock frequency source includes a timing resistor connected between said supply lead and a first terminal of a current limiting resistor whose second terminal is connected to the first plate of a storage capacitor having the second plate connected to said common lead, interconnection of said current limiting resistor and said storage capacitor is connected to the anode electrode of a Programmable Unijunction Transistor (PUT) whose cathode electrode is connected through a pulse forming resistor to said common lead, gate electrode of said PUT is connected through a biasing resistor to said common lead, said interconnection of gate electrode and biasing resistor is connected also to the cathode electrode of a compensating diode having anode electrode connected to interconnection of two PUT reference voltage resistors connected between said common and said supply lead, said PUT cathode electrode is connected to a pulse stretching circuit which includes anode electrode of a blocking diode whose cathode electrode is connected to the first plate of a capacitor, having the second plate connected to said common lead, a base resistor connected between the said diode-capacitor interconnection and a base electrode of an n-p-n transistor having emitter electrode connected to said common lead and the collector electrode connected through a relay coil to said supply lead, a transient protection diode is connected across said relay coil having cathode electrode connected to the positive end of said coil, said relay coil operating multiple sets of mutually isolated contacts, each set of contacts is utilized to pulse at least one sequencing circuit which includes a normally open contact connected through a timing resistor to said supply lead, a common contact being connected through a current limiting resistor to the interconnection of the first plate of a storage capacitor, having second plate connected to said common lead, and an anode electrode of a PUT, whose cathode electrode is connected to an output terminal and to the first terminal of a cathode resistor, having second terminal connected to said common lead, the gate electrode of said PUT is connected through a biasing resistor to said common lead and to the cathode electrode of a biasing diode, whose anode electrode is connected to the interconnection of the two PUT reference voltage resistors connected between said common and said supply lead.

2. Circuit as recited in claim 1 and having said timing resistor adjustable to provide varying of the clock frequency thus, duration of all sequence intervals.

3. Circuit as recited in claim 1 and having said timing resistor adjustable, within said sequencing circuit, to provide independently adjustable intervals in each and every sequence.

4. Circuit as recited in claim 1 and having one single sequence by provision of a single set of contacts and a single sequencing circuit.

5. A sequencing timer having the plurality of sequences, the first sequence starting at the moment the power is supplied to the circuitry, the second sequence starting at the end of the first sequence, the nth sequence starting at the end of n - 1st sequence, a pulse is produced at the end of each sequence, said sequencing timer consisting of: a d-c power source, having a positive and a negative terminal, said negative terminal is connected to a common lead, sAid positive terminal is connected to the first terminal of a power switch, while the second terminal of said power switch is connected to a supply lead, a clock frequency source includes a timing resistor connected between said supply lead and a first terminal of a current limiting resistor whose second terminal is connected to the first plate of a storage capacitor having the second plate connected to said common lead, interconnection of said current limiting resistor and said storage capacitor is connected to the anode electrode of a Programmable Unijunction Transistor (PUT) whose cathode electrode is connected through a pulse forming resistor to said common lead, gate electrode of said PUT is connected through a biasing resistor to said common lead, said interconnection of gate electrode and biasing resistor is connected also to the cathode electrode of a compensating diode having anode electrode connected to interconnection of two PUT reference voltage resistors connected between said common and said supply lead, said PUT cathode electrode is connected to a pulse stretching circuit which includes anode electrode of a blocking diode whose cathode electrode is connected to the first plate of a capacitor, having the second plate connected to said common lead, a base resistor connected between the said diode-capacitor interconnection and a base electrode of an n-p-n transistor having emitter electrode connected to said common lead and the collector electrode connected through a relay coil to said supply lead, a transient protection diode is connected across said relay coil having cathode electrode connected to the positive end of said coil, said relay coil operating multiple sets of mutually isolated contacts, each set of contacts is utilized to pulse at least one sequencing circuit, the first set of contacts is utilized to pulse the first sequencing circuit which includes a normally open contact connected through a timing resistor to said supply lead, a common contact being connected through a current limiting resistor to the interconnection of the first plate of a storage capacitor, having second plate connected to said common lead, and an anode electrode of a PUT, whose cathode electrode is connected to an output terminal and to the first terminal of a cathode resistor, having second terminal connected to said common lead, the gate electrode of said PUT is connected through a biasing resistor to said common lead and to the cathode electrode of a biasing diode, whose anode electrode is connected to the interconnection of the two PUT reference voltage resistors connected between said common and said supply lead, the first sequence output terminal is also connected to the gate electrode of the first Silicon Controlled Rectifier (SCR) having the cathode electrode connected to said common lead and anode electrode connected through a first anode resistor to said supply lead, said anode electrode is also connected through a first base resistor to the base electrode of a first p-n-p transistor whose emitter electrode is connected to said supply lead and, collector electrode connected to the next sequencing circuit thus acts as the first supply lead, a second set of contacts which consists of a normally open contact and a common contact, these contacts being used to pulse a second sequencing circuit, which is of identical configuration as described first sequencing circuit, said second set of contacts operates associated circuit after the first sequencing time interval is over, said second sequence circuit being able to deliver a pulse at the end of said second sequence interval, and supply the power to the third sequencing circuit, an nth set of contacts which consists of a normally open contact and a common contact, these contacts are used to pulse the nth sequencing circuit, n being an integer larger than two, normally open contact is connEcted to the first terminal of the nth timing resistor whose second terminal is connected to the collector electrode of n - 1st sequencing circuit, said collector electrode acting as the n-1st supply lead, the common contact is connected through the nth limiting resistor to the first plate of an nth storage capacitor which has the second plate connected to said common lead, said first plate is also connected to the anode electrode of the nth PUT having cathode electrode connected through the nth cathode resistor to said common lead, said cathode is also connected to an nth output terminal, gate electrode of said nth PUT is connected through an nth biasing resistor to said common lead, said interconnection of biasing resistor and gate electrode is connected also to the cathode electrode of an nth compensating diode whose anode electrode is connected to the interconnection of the two nth PUT reference voltage resistors connected between said common and said n - 1st supply lead, said nth sequence circuit being able to produce a pulse at the end of the nth sequence interval.

6. The circuit of claim 5 and having said timing resistor adjustable to provide adjustable clock frequency which causes the change in duration of all sequences.

7. The circuit of claim 5 and having said first timing resistor adjustable, and said nth timing resistor adjustable to provide independently adjustable interval in each and every sequence.

8. The circuit of claim 5 having one single sequence by provision of a single set of contacts and a single sequencing circuit.

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